data/myhdl-0.11/pylintrc:36: reenable ==> re-enable
data/myhdl-0.11/cosimulation/cver/Makefile.lnx:20: libaries ==> libraries
data/myhdl-0.11/cosimulation/cver/Makefile.lnx64:19: libaries ==> libraries
data/myhdl-0.11/cosimulation/cver/Makefile.osx:16: libaries ==> libraries
data/myhdl-0.11/cosimulation/cver/myhdl_vpi.c:479: boostrap ==> bootstrap
data/myhdl-0.11/cosimulation/modelsim-win/myhdl_vpi.c:520: boostrap ==> bootstrap
data/myhdl-0.11/cosimulation/modelsim/myhdl_vpi.c:494: boostrap ==> bootstrap
data/myhdl-0.11/doc/source/_static/pygments.css:30: nd ==> and, 2nd
data/myhdl-0.11/doc/source/manual/conversion_examples.rst:306: inout ==> input, in out
data/myhdl-0.11/doc/source/manual/conversion_examples.rst:371: dout ==> doubt
data/myhdl-0.11/doc/source/manual/conversion_examples.rst:383: dout ==> doubt
data/myhdl-0.11/doc/source/manual/conversion_examples.rst:392: dout ==> doubt
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data/myhdl-0.11/doc/source/manual/conversion_examples.rst:431: dout ==> doubt
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data/myhdl-0.11/doc/source/manual/conversion_examples.rst:477: dout ==> doubt
data/myhdl-0.11/doc/source/manual/conversion_examples.rst:481: dout ==> doubt
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data/myhdl-0.11/doc/source/manual/conversion_examples.rst:544: dout ==> doubt
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data/myhdl-0.11/doc/source/manual/conversion_examples.rst:547: dout ==> doubt
data/myhdl-0.11/doc/source/manual/highlevel.rst:335: dout ==> doubt
data/myhdl-0.11/doc/source/manual/highlevel.rst:340: dout ==> doubt
data/myhdl-0.11/doc/source/manual/highlevel.rst:357: dout ==> doubt
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data/myhdl-0.11/doc/source/manual/highlevel.rst:402: dout ==> doubt
data/myhdl-0.11/doc/source/manual/highlevel.rst:428: dout ==> doubt
data/myhdl-0.11/doc/source/manual/highlevel.rst:436: dout ==> doubt
data/myhdl-0.11/doc/source/manual/highlevel.rst:450: dout ==> doubt
data/myhdl-0.11/doc/source/manual/highlevel.rst:461: dout ==> doubt
data/myhdl-0.11/doc/source/manual/highlevel.rst:487: dout ==> doubt
data/myhdl-0.11/doc/source/manual/highlevel.rst:497: dout ==> doubt
data/myhdl-0.11/doc/source/manual/reference.rst:104: attribbute ==> attribute
data/myhdl-0.11/doc/source/manual/rtl.rst:114: asychronous ==> asynchronous
data/myhdl-0.11/doc/source/manual/structure.rst:85: dout ==> doubt
data/myhdl-0.11/doc/source/manual/structure.rst:89: dout ==> doubt
data/myhdl-0.11/doc/source/manual/structure.rst:102: dout ==> doubt
data/myhdl-0.11/doc/source/manual/structure.rst:108: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:238: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:250: dout ==> doubt
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data/myhdl-0.11/doc/source/whatsnew/0.5.rst:268: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:269: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:283: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:327: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:331: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:335: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:339: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:346: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:350: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:351: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:357: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:358: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:359: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:360: dout ==> doubt
data/myhdl-0.11/doc/source/whatsnew/0.5.rst:403: surprizing ==> surprising
data/myhdl-0.11/doc/source/whatsnew/0.9.rst:100: intergration ==> integration
data/myhdl-0.11/example/cookbook/stopwatch/bcd2led.py:14: convertor ==> converter
data/myhdl-0.11/example/manual/FramerCtrl.vhd:32: inout ==> input, in out
data/myhdl-0.11/example/manual/fifo.py:10: dout ==> doubt
data/myhdl-0.11/example/manual/fifo.py:15: dout ==> doubt
data/myhdl-0.11/example/manual/fifo.py:35: dout ==> doubt
data/myhdl-0.11/example/manual/fifo.py:43: dout ==> doubt
data/myhdl-0.11/example/manual/fifo.py:48: dout ==> doubt
data/myhdl-0.11/example/manual/fifo.py:69: dout ==> doubt
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data/myhdl-0.11/example/manual/fifo.py:83: dout ==> doubt
data/myhdl-0.11/example/manual/fifo.py:106: dout ==> doubt
data/myhdl-0.11/example/manual/fifo.py:106: dout ==> doubt
data/myhdl-0.11/example/manual/inc.vhd:15: inout ==> input, in out
data/myhdl-0.11/example/manual/ram.py:4: dout ==> doubt
data/myhdl-0.11/example/manual/ram.py:16: dout ==> doubt
data/myhdl-0.11/example/manual/ram.py:21: dout ==> doubt
data/myhdl-0.11/example/manual/ram.py:30: dout ==> doubt
data/myhdl-0.11/example/manual/ram.py:31: dout ==> doubt
data/myhdl-0.11/example/manual/ram.vhd:15: dout ==> doubt
data/myhdl-0.11/example/manual/ram.vhd:45: dout ==> doubt
data/myhdl-0.11/example/manual/ram_1.v:9: dout ==> doubt
data/myhdl-0.11/example/manual/ram_1.v:17: dout ==> doubt
data/myhdl-0.11/example/manual/ram_1.v:18: dout ==> doubt
data/myhdl-0.11/example/manual/ram_1.v:38: dout ==> doubt
data/myhdl-0.11/example/manual/rom.py:6: dout ==> doubt
data/myhdl-0.11/example/manual/rom.py:11: dout ==> doubt
data/myhdl-0.11/example/manual/rom.py:15: dout ==> doubt
data/myhdl-0.11/example/manual/rom.py:20: dout ==> doubt
data/myhdl-0.11/example/manual/rom.py:21: dout ==> doubt
data/myhdl-0.11/example/manual/rom.v:9: dout ==> doubt
data/myhdl-0.11/example/manual/rom.v:14: dout ==> doubt
data/myhdl-0.11/example/manual/rom.v:15: dout ==> doubt
data/myhdl-0.11/example/manual/rom.v:25: dout ==> doubt
data/myhdl-0.11/example/manual/rom.v:26: dout ==> doubt
data/myhdl-0.11/example/manual/rom.v:27: dout ==> doubt
data/myhdl-0.11/example/manual/rom.v:28: dout ==> doubt
data/myhdl-0.11/example/manual/rom.vhd:15: dout ==> doubt
data/myhdl-0.11/example/manual/rom.vhd:32: dout ==> doubt
data/myhdl-0.11/example/manual/rom.vhd:33: dout ==> doubt
data/myhdl-0.11/example/manual/rom.vhd:34: dout ==> doubt
data/myhdl-0.11/example/manual/rom.vhd:35: dout ==> doubt
data/myhdl-0.11/example/manual/sparseMemory.py:10: dout ==> doubt
data/myhdl-0.11/example/manual/sparseMemory.py:15: dout ==> doubt
data/myhdl-0.11/example/manual/sparseMemory.py:32: dout ==> doubt
data/myhdl-0.11/example/manual/sparseMemory.py:37: dout ==> doubt
data/myhdl-0.11/example/manual/sparseMemory.py:42: dout ==> doubt
data/myhdl-0.11/example/manual/sparseMemory.py:60: dout ==> doubt
data/myhdl-0.11/example/manual/sparseMemory.py:67: dout ==> doubt
data/myhdl-0.11/example/manual/sparseMemory.py:101: dout ==> doubt
data/myhdl-0.11/example/manual/sparseMemory.py:103: dout ==> doubt
data/myhdl-0.11/myhdl/_always_comb.py:37: inout ==> input, in out
data/myhdl-0.11/myhdl/_always_comb.py:60: inouts ==> inputs
data/myhdl-0.11/myhdl/_always_comb.py:60: inouts ==> inputs
data/myhdl-0.11/myhdl/_always_comb.py:61: inouts ==> inputs
data/myhdl-0.11/myhdl/_always_comb.py:62: inouts ==> inputs
data/myhdl-0.11/myhdl/_always_seq.py:106: inouts ==> inputs
data/myhdl-0.11/myhdl/_always_seq.py:107: inouts ==> inputs
data/myhdl-0.11/myhdl/_block.py:292: attibutes ==> attributes
data/myhdl-0.11/myhdl/_instance.py:110: inouts ==> inputs
data/myhdl-0.11/myhdl/_instance.py:110: inouts ==> inputs
data/myhdl-0.11/myhdl/_visitors.py:16: inouts ==> inputs
data/myhdl-0.11/myhdl/_visitors.py:52: inouts ==> inputs
data/myhdl-0.11/myhdl/conversion/_VHDLNameValidation.py:16: inout ==> input, in out
data/myhdl-0.11/myhdl/conversion/_analyze.py:193: contructs ==> constructs
data/myhdl-0.11/myhdl/conversion/_analyze.py:560: INOUT ==> INPUT, IN OUT
data/myhdl-0.11/myhdl/conversion/_analyze.py:604: suprize ==> surprise
data/myhdl-0.11/myhdl/conversion/_analyze.py:670: wether ==> weather, whether
data/myhdl-0.11/myhdl/conversion/_analyze.py:802: INOUT ==> INPUT, IN OUT
data/myhdl-0.11/myhdl/conversion/_analyze.py:805: INOUT ==> INPUT, IN OUT
data/myhdl-0.11/myhdl/conversion/_analyze.py:859: INOUT ==> INPUT, IN OUT
data/myhdl-0.11/myhdl/conversion/_misc.py:77: INOUT ==> INPUT, IN OUT
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:397: inout ==> input, in out
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:767: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:769: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:771: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:776: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:778: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:783: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:1513: interprete ==> interpret
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:1857: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:1860: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:1861: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:1863: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:2001: inout ==> input, in out
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:2002: inout ==> input, in out
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:2002: inout ==> input, in out
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:2048: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:2049: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:2148: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:2150: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVHDL.py:2151: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:299: inout ==> input, in out
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:333: inital ==> initial
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1168: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1173: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1175: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1402: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1405: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1406: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1408: tipe ==> type, tip
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1512: inout ==> input, in out
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1513: inout ==> input, in out
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1513: inout ==> input, in out
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1557: treatement ==> treatment
data/myhdl-0.11/myhdl/conversion/_toVerilog.py:1591: suprize ==> surprise
data/myhdl-0.11/myhdl/spec/Signal_spec.txt:119: comparision ==> comparison
data/myhdl-0.11/myhdl/test/bugs/test_bug_28.py:5: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_bug_28.py:8: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_bug_28.py:11: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_bug_28.py:16: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_122.py:6: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_122.py:12: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_122.py:13: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_122.py:15: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_122.py:20: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_122.py:25: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_122.py:26: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_18.py:6: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_18.py:18: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_18.py:23: dout ==> doubt
data/myhdl-0.11/myhdl/test/bugs/test_issue_18.py:32: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_dec.py:212: inout ==> input, in out
data/myhdl-0.11/myhdl/test/conversion/general/test_interfaces3.py:150: inteface ==> interface
data/myhdl-0.11/myhdl/test/conversion/general/test_interfaces3.py:187: convertor ==> converter
data/myhdl-0.11/myhdl/test/conversion/general/test_interfaces4.py:62: inlcude ==> include
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:10: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:22: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:26: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:37: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:42: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:56: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:62: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:74: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:80: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:82: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:95: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:103: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:110: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:125: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ram.py:126: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_rom.py:14: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_rom.py:20: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_rom.py:25: dout ==> doubt
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data/myhdl-0.11/myhdl/test/conversion/general/test_rom.py:79: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_set_dir.py:13: dout ==> doubt
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data/myhdl-0.11/myhdl/test/conversion/general/test_set_dir.py:79: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_set_dir.py:87: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_set_dir.py:107: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_set_dir.py:115: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:10: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:15: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:17: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:17: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:17: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:23: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:25: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:30: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:32: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:36: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:36: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:43: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:47: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:61: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/general/test_ternary.py:62: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVHDL/test_keywords.py:25: inout ==> input, in out
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_dec.py:207: inout ==> input, in out
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:12: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:27: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:32: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:43: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:47: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:61: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:65: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:77: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:83: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:85: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:85: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:86: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:99: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:104: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:111: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:118: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:119: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:134: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:136: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_ram.py:137: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:18: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:24: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:28: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:36: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:41: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:49: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:53: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:57: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:62: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:69: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:74: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:75: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:84: dout ==> doubt
data/myhdl-0.11/myhdl/test/conversion/toVerilog/test_rom.py:85: dout ==> doubt
data/myhdl-0.11/myhdl/test/core/test_ShadowSignal.py:38: ba ==> by, be
data/myhdl-0.11/myhdl/test/core/test_ShadowSignal.py:47: ba ==> by, be
data/myhdl-0.11/myhdl/test/core/test_ShadowSignal.py:176: ba ==> by, be
data/myhdl-0.11/myhdl/test/core/test_ShadowSignal.py:178: ba ==> by, be
data/myhdl-0.11/myhdl/test/core/test_ShadowSignal.py:186: ba ==> by, be
data/myhdl-0.11/myhdl/test/core/test_ShadowSignal.py:190: ba ==> by, be
data/myhdl-0.11/myhdl/test/core/test_ShadowSignal.py:195: ba ==> by, be