data/verilog-mode-20161124.fd230e6/TODO:9: hiearchy ==> hierarchy
data/verilog-mode-20161124.fd230e6/verilog-mode.el:542: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:543: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:1577: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:1657: Inout ==> Input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:1658: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:1726: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:2673: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:2686: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:2732: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:2961: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:3103: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:3116: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:3848: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5108: ket ==> kept
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5109: KET ==> KEPT
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5119: ket ==> kept
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5157: ket ==> kept
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5509: structres ==> structures
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5528: structres ==> structures
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5529: structres ==> structures
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5530: structres ==> structures
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5531: structres ==> structures
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5532: structres ==> structures
data/verilog-mode-20161124.fd230e6/verilog-mode.el:5669: structres ==> structures
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7212: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7296: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7296: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7297: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7297: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7298: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7298: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7299: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7299: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7300: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7300: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7301: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7301: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7477: ot ==> to, of, or
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7798: credate ==> created
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7819: credate ==> created
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7944: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7945: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7973: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:7974: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:8244: Inout ==> Input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:8408: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:8426: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:8431: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:8514: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:8711: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:8923: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:8990: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:9226: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:9494: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:10343: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:10362: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:10367: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:11115: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:11129: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:11147: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:11687: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:11788: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:11791: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12205: Synopsys ==> Synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12350: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12350: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12383: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12383: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12384: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12388: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12396: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12423: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12423: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12424: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12430: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12463: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12470: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12472: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12554: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12561: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12564: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12572: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12601: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12608: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12610: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12643: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12671: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12678: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12694: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12763: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12801: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12815: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12869: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12872: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:12875: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13344: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13348: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13433: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13461: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13466: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13471: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13472: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13473: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13490: Erro ==> Error
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13684: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:13705: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/verilog-mode.el:14137: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/verilog-mode.el:14139: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/attic/verilog-lex.el:24: Synopsys ==> Synopsis
data/verilog-mode-20161124.fd230e6/attic/verilog-lex.el:45: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/attic/verilog-lex.el:93: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/attic/verilog-lex.el:98: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoarg_string_bug259.v:5: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoarg_string_bug259.v:6: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoarg_string_bug259.v:7: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoarg_string_bug259.v:8: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoascii_myers.v:14: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoascii_myers.v:19: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoascii_myers.v:20: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoascii_myers.v:21: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoascii_myers.v:34: Erro ==> Error
data/verilog-mode-20161124.fd230e6/tests/autoascii_peltan.v:10: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoascii_peltan.v:13: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoascii_peltan.v:16: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoascii_peltan.v:30: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoascii_peltan_inc.v:1: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_ex.v:10: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_ex.v:14: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_ex.v:15: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_ex.v:16: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_frominc.v:9: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_onehot.v:9: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_onehot.v:16: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_param.v:8: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_reed.v:6: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_reed.v:15: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_reed.v:16: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_sm.v:10: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_sm.v:17: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_sm.v:21: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_sm.v:38: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_sm.v:38: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_sm.v:39: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoasciienum_sm.v:44: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoconst_gesmith.v:15: ot ==> to, of, or
data/verilog-mode-20161124.fd230e6/tests/autoconst_gesmith.v:17: ot ==> to, of, or
data/verilog-mode-20161124.fd230e6/tests/autoinout.v:22: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout.v:25: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_lovell.v:13: ba ==> by, be
data/verilog-mode-20161124.fd230e6/tests/autoinout_moller.v:4: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinout_moller.v:21: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autoinout_moller.v:21: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autoinout_moller.v:22: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_moller.v:29: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinout_moller.v:39: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinout_moller.v:47: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_regexp.v:22: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_regexp.v:25: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_v2k.v:29: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_v2k.v:30: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_v2k.v:31: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_v2k.v:46: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_v2k.v:47: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinout_v2k.v:48: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinoutcomp.v:6: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autoinoutmodule.v:9: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autoinoutmodule.v:14: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autoinput_concat_lau.v:4: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_bits_lba.v:16: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_bits_lba_gi.v:91: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_bits_lba_gi.v:92: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_for_myers.v:45: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_func.v:14: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_instname_all.v:8: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_instname_all.v:13: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_instname_carlh.v:9: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_instname_carlh.v:14: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_interface.v:5: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_interface.v:19: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_interface_star.v:5: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_interface_star.v:19: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_lopaz_srpad.v:4: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_lopaz_srpad.v:12: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_mplist.sv:37: Synopsys ==> Synopsis
data/verilog-mode-20161124.fd230e6/tests/autoinst_paramover.v:2: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_paramover.v:13: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_paramover.v:14: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_paramover.v:18: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_paramover_sub.v:2: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_paramover_sub.v:13: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_paramover_sub.v:14: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_paramvalue.v:4: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoinst_podolsky.v:14: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_precomment.v:15: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_rogoff.v:4: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard.v:23: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:2: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:13: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:14: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:15: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:16: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:17: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:18: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:19: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:20: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:21: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:22: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:23: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:24: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:25: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:26: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:27: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:28: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:29: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:30: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:31: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:32: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:33: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:34: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:35: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinst_wildcard_sub.v:36: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinstparam_first_sub.v:2: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests/autoinstparam_first_sub.v:14: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/autoinstparam_first_sub.v:15: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/automodport_ex.v:15: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests/autosense_aas_ifdef.v:3: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autosense_peers_func.v:26: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/autosense_smith.v:5: useable ==> usable
data/verilog-mode-20161124.fd230e6/tests/comment_strip.v:18: hidded ==> hidden
data/verilog-mode-20161124.fd230e6/tests/indent_comments.v:4: ouput ==> output
data/verilog-mode-20161124.fd230e6/tests/indent_decl.v:8: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/indent_dpi.v:27: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/indent_immediate_assertion.sv:22: immedate ==> immediate
data/verilog-mode-20161124.fd230e6/tests/indent_modansi.v:12: alls ==> all, falls
data/verilog-mode-20161124.fd230e6/tests/label_task.v:23: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/property_test.v:22: doesnt ==> doesn't, does not
data/verilog-mode-20161124.fd230e6/tests/src_frag.vs:8: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/src_frag.vs:21: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests/testcases.v:4: Synopsys ==> Synopsis
data/verilog-mode-20161124.fd230e6/tests/testcases.v:102: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests/testcases.v:126: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v:5: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v:18: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v:18: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v:19: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v:20: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v:38: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v:50: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v:57: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinout.v:60: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinst_lopaz.v:36: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinst_lopaz.v:53: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinst_lopaz.v:69: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_batch_ok/autoinst_star.v:27: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_string_bug259.v:5: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_string_bug259.v:6: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_string_bug259.v:7: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoarg_string_bug259.v:8: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_myers.v:14: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_myers.v:19: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_myers.v:20: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_myers.v:21: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_myers.v:34: Erro ==> Error
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_peltan.v:10: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_peltan.v:13: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_peltan.v:16: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_peltan.v:30: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoascii_peltan_inc.v:1: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_ex.v:10: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_ex.v:14: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_ex.v:15: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_ex.v:16: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_frominc.v:9: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_onehot.v:9: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_onehot.v:16: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_param.v:8: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_reed.v:6: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_reed.v:15: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_reed.v:16: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_sm.v:10: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_sm.v:17: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_sm.v:21: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_sm.v:38: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_sm.v:38: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_sm.v:39: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoasciienum_sm.v:44: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoconst_gesmith.v:15: ot ==> to, of, or
data/verilog-mode-20161124.fd230e6/tests_ok/autoconst_gesmith.v:17: ot ==> to, of, or
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v:5: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v:18: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v:18: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v:19: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v:20: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v:38: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v:50: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v:57: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout.v:60: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_lovell.v:5: ba ==> by, be
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_lovell.v:13: ba ==> by, be
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_lovell.v:32: ba ==> by, be
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_lovell.v:43: ba ==> by, be
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_moller.v:4: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_moller.v:21: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_moller.v:21: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_moller.v:22: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_moller.v:29: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_moller.v:39: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_moller.v:47: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v:5: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v:17: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v:17: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v:18: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v:35: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v:47: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v:54: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_regexp.v:57: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:17: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:17: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:18: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:19: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:20: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:44: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:60: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:79: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:80: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:81: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:96: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:97: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinout_v2k.v:98: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutcomp.v:11: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutcomp.v:15: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutin.v:7: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodport_bourduas_type.v:5: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule.v:9: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule.v:14: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_iface.v:5: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_ign.v:7: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_re2.v:9: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_re2.v:15: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_regexp.v:9: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinoutmodule_v2k.v:3: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau.v:2: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau.v:9: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau.v:23: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau.v:23: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau.v:24: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinput_concat_lau.v:35: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_atregexp.v:9: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_atregexp.v:13: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_atregexp.v:17: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_atregexp.v:27: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_atregexp.v:31: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_bits_lba.v:16: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_bits_lba_gi.v:91: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_bits_lba_gi.v:92: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_for_myers.v:45: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_func.v:14: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_instname_all.v:8: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_instname_all.v:13: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_instname_carlh.v:9: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_instname_carlh.v:14: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface.v:5: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface.v:19: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface_star.v:5: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_interface_star.v:19: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_lopaz.v:36: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_lopaz.v:53: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_lopaz.v:69: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_lopaz_srpad.v:4: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_lopaz_srpad.v:12: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_mplist.sv:41: Synopsys ==> Synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover.v:2: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover.v:13: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover.v:14: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover.v:18: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover_sub.v:2: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover_sub.v:13: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramover_sub.v:14: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_paramvalue.v:4: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_podolsky.v:14: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_precomment.v:15: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:4: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:4: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:5: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:6: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:7: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:8: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:9: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:10: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:11: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:12: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:13: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:14: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:25: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_regexp_match.v:59: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_rogoff.v:4: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_star.v:27: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_sv_shaw.v:4: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard.v:19: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:2: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:13: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:14: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:15: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:16: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:17: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:18: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:19: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:20: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:21: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:22: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:23: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:24: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:25: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:26: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:27: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:28: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:29: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:30: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:31: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:32: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:33: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:34: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:35: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinst_wildcard_sub.v:36: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_first.v:19: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_first.v:31: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_first.v:42: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_first.v:54: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_first_sub.v:2: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_first_sub.v:14: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/autoinstparam_first_sub.v:15: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/automodport_ex.v:15: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/automodport_full.v:10: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/automodport_full.v:18: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/automodport_full.v:28: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/autosense_aas_ifdef.v:3: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autosense_peers_func.v:26: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/autosense_smith.v:5: useable ==> usable
data/verilog-mode-20161124.fd230e6/tests_ok/autotieoff_signed.v:17: inouts ==> inputs
data/verilog-mode-20161124.fd230e6/tests_ok/comment_strip.v:18: hidded ==> hidden
data/verilog-mode-20161124.fd230e6/tests_ok/indent_comments.v:4: ouput ==> output
data/verilog-mode-20161124.fd230e6/tests_ok/indent_decl.v:8: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/indent_dpi.v:27: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/indent_immediate_assertion.sv:22: immedate ==> immediate
data/verilog-mode-20161124.fd230e6/tests_ok/indent_modansi.v:12: alls ==> all, falls
data/verilog-mode-20161124.fd230e6/tests_ok/inject_first.v:23: Inouts ==> Inputs
data/verilog-mode-20161124.fd230e6/tests_ok/label_task.v:23: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/property_test.v:22: doesnt ==> doesn't, does not
data/verilog-mode-20161124.fd230e6/tests_ok/src_frag.vs:8: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/src_frag.vs:21: inout ==> input, in out
data/verilog-mode-20161124.fd230e6/tests_ok/testcases.v:4: Synopsys ==> Synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/testcases.v:102: synopsys ==> synopsis
data/verilog-mode-20161124.fd230e6/tests_ok/testcases.v:126: synopsys ==> synopsis