data/yosys-0.9/CHANGELOG:66: upto ==> up to
data/yosys-0.9/CHANGELOG:149: combinatorical ==> combinatorial
data/yosys-0.9/CHANGELOG:210: concurent ==> concurrent
data/yosys-0.9/README.md:72: Similarily ==> Similarly
data/yosys-0.9/README.md:234: synopsys ==> synopsis
data/yosys-0.9/README.md:272: synopsys ==> synopsis
data/yosys-0.9/README.md:275: synopsys ==> synopsis
data/yosys-0.9/README.md:277: synopsys ==> synopsis
data/yosys-0.9/README.md:277: synopsys ==> synopsis
data/yosys-0.9/Makefile:319: manualy ==> manually
data/yosys-0.9/backends/blif/blif.cc:118: upto ==> up to
data/yosys-0.9/backends/blif/blif.cc:427: upto ==> up to
data/yosys-0.9/backends/edif/edif.cc:242: INOUT ==> INPUT, IN OUT
data/yosys-0.9/backends/edif/edif.cc:257: upto ==> up to
data/yosys-0.9/backends/edif/edif.cc:258: upto ==> up to
data/yosys-0.9/backends/edif/edif.cc:320: INOUT ==> INPUT, IN OUT
data/yosys-0.9/backends/edif/edif.cc:331: upto ==> up to
data/yosys-0.9/backends/edif/edif.cc:332: upto ==> up to
data/yosys-0.9/backends/firrtl/firrtl.cc:346: INOUT ==> INPUT, IN OUT
data/yosys-0.9/backends/firrtl/firrtl.cc:413: inout ==> input, in out
data/yosys-0.9/backends/ilang/ilang_backend.cc:124: upto ==> up to
data/yosys-0.9/backends/ilang/ilang_backend.cc:125: upto ==> up to
data/yosys-0.9/backends/ilang/ilang_backend.cc:133: inout ==> input, in out
data/yosys-0.9/backends/json/json.cc:128: inout ==> input, in out
data/yosys-0.9/backends/json/json.cc:131: upto ==> up to
data/yosys-0.9/backends/json/json.cc:132: upto ==> up to
data/yosys-0.9/backends/json/json.cc:167: inout ==> input, in out
data/yosys-0.9/backends/json/json.cc:198: upto ==> up to
data/yosys-0.9/backends/json/json.cc:199: upto ==> up to
data/yosys-0.9/backends/json/json.cc:302: inout ==> input, in out
data/yosys-0.9/backends/json/json.cc:320: inout ==> input, in out
data/yosys-0.9/backends/table/table.cc:106: inout ==> input, in out
data/yosys-0.9/backends/verilog/verilog_backend.cc:139: inout ==> input, in out
data/yosys-0.9/backends/verilog/verilog_backend.cc:175: upto ==> up to
data/yosys-0.9/backends/verilog/verilog_backend.cc:331: upto ==> up to
data/yosys-0.9/backends/verilog/verilog_backend.cc:336: upto ==> up to
data/yosys-0.9/backends/verilog/verilog_backend.cc:395: inout ==> input, in out
data/yosys-0.9/backends/verilog/verilog_backend.cc:405: upto ==> up to
data/yosys-0.9/backends/verilog/verilog_backend.cc:415: inout ==> input, in out
data/yosys-0.9/backends/verilog/verilog_backend.cc:801: synopsys ==> synopsis
data/yosys-0.9/examples/aiger/README:9: lates ==> later, latest
data/yosys-0.9/examples/cmos/cmos_cells.sp:28: nD ==> and, 2nd
data/yosys-0.9/examples/cmos/cmos_cells.sp:31: nD ==> and, 2nd
data/yosys-0.9/examples/igloo2/runme.sh:3: edn ==> end
data/yosys-0.9/frontends/aiger/aigerparse.cc:22: Linz ==> Lines
data/yosys-0.9/frontends/ast/ast.cc:404: inout ==> input, in out
data/yosys-0.9/frontends/ast/ast.cc:1275: inout ==> input, in out
data/yosys-0.9/frontends/ast/simplify.cc:466: asignment ==> assignment
data/yosys-0.9/frontends/ast/genrtlil.cc:889: upto ==> up to
data/yosys-0.9/frontends/ast/genrtlil.cc:936: upto ==> up to
data/yosys-0.9/frontends/ilang/ilang_lexer.l:60: upto ==> up to
data/yosys-0.9/frontends/ilang/ilang_lexer.l:65: inout ==> input, in out
data/yosys-0.9/frontends/ilang/ilang_parser.y:183: upto ==> up to
data/yosys-0.9/frontends/json/jsonparse.cc:295: upto ==> up to
data/yosys-0.9/frontends/json/jsonparse.cc:296: upto ==> up to
data/yosys-0.9/frontends/json/jsonparse.cc:298: upto ==> up to
data/yosys-0.9/frontends/json/jsonparse.cc:313: inout ==> input, in out
data/yosys-0.9/frontends/json/jsonparse.cc:387: upto ==> up to
data/yosys-0.9/frontends/json/jsonparse.cc:388: upto ==> up to
data/yosys-0.9/frontends/json/jsonparse.cc:390: upto ==> up to
data/yosys-0.9/frontends/liberty/liberty.cc:422: upto ==> up to
data/yosys-0.9/frontends/liberty/liberty.cc:442: upto ==> up to
data/yosys-0.9/frontends/liberty/liberty.cc:449: upto ==> up to
data/yosys-0.9/frontends/liberty/liberty.cc:582: inout ==> input, in out
data/yosys-0.9/frontends/liberty/liberty.cc:610: inout ==> input, in out
data/yosys-0.9/frontends/liberty/liberty.cc:628: upto ==> up to
data/yosys-0.9/frontends/liberty/liberty.cc:630: inout ==> input, in out
data/yosys-0.9/frontends/liberty/liberty.cc:633: inout ==> input, in out
data/yosys-0.9/frontends/liberty/liberty.cc:665: inout ==> input, in out
data/yosys-0.9/frontends/verilog/verilog_lexer.l:221: inout ==> input, in out
data/yosys-0.9/frontends/verilog/verilog_lexer.l:334: synopsys ==> synopsis
data/yosys-0.9/frontends/verilog/verilog_lexer.l:337: synopsys ==> synopsis
data/yosys-0.9/frontends/verilog/verilog_lexer.l:343: synopsys ==> synopsis
data/yosys-0.9/frontends/verilog/verilog_lexer.l:344: synopsys ==> synopsis
data/yosys-0.9/frontends/verilog/verilog_lexer.l:345: synopsys ==> synopsis
data/yosys-0.9/frontends/verilog/verilog_lexer.l:347: synopsys ==> synopsis
data/yosys-0.9/frontends/verilog/verilog_lexer.l:353: synopsys ==> synopsis
data/yosys-0.9/frontends/verilog/verilog_lexer.l:362: synopsys ==> synopsis
data/yosys-0.9/frontends/verilog/verilog_parser.y:29: ist ==> is, it, its, it's, sit, list
data/yosys-0.9/frontends/verilog/verilog_parser.y:1329: inout ==> input, in out
data/yosys-0.9/kernel/cellaigs.cc:100: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:104: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:119: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:125: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:154: bA ==> by, be
data/yosys-0.9/kernel/cellaigs.cc:156: bA ==> by, be
data/yosys-0.9/kernel/cellaigs.cc:160: bA ==> by, be
data/yosys-0.9/kernel/cellaigs.cc:162: bA ==> by, be
data/yosys-0.9/kernel/cellaigs.cc:163: bA ==> by, be
data/yosys-0.9/kernel/cellaigs.cc:296: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:306: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:307: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:323: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:325: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:326: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:335: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:337: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:354: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:356: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:358: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:360: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:391: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:392: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:421: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:422: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:423: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:431: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:432: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:433: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:441: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:442: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:443: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:444: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:452: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:453: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:454: inport ==> import
data/yosys-0.9/kernel/cellaigs.cc:455: inport ==> import
data/yosys-0.9/kernel/rtlil.cc:1793: upto ==> up to
data/yosys-0.9/kernel/rtlil.cc:1793: upto ==> up to
data/yosys-0.9/kernel/rtlil.cc:2354: upto ==> up to
data/yosys-0.9/kernel/rtlil.h:1239: upto ==> up to
data/yosys-0.9/libs/bigint/BigInteger.hh:145: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:146: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:147: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:150: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:151: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:152: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:155: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:156: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:157: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:174: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:175: ans ==> and
data/yosys-0.9/libs/bigint/BigInteger.hh:176: ans ==> and
data/yosys-0.9/libs/bigint/BigIntegerAlgorithms.cc:55: ans ==> and
data/yosys-0.9/libs/bigint/BigIntegerAlgorithms.cc:61: ans ==> and
data/yosys-0.9/libs/bigint/BigIntegerAlgorithms.cc:61: ans ==> and
data/yosys-0.9/libs/bigint/BigIntegerAlgorithms.cc:62: ans ==> and
data/yosys-0.9/libs/bigint/BigIntegerAlgorithms.cc:65: ans ==> and
data/yosys-0.9/libs/bigint/BigIntegerAlgorithms.cc:66: ans ==> and
data/yosys-0.9/libs/bigint/BigIntegerAlgorithms.cc:69: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.cc:238: unsucessfully ==> unsuccessfully
data/yosys-0.9/libs/bigint/BigUnsigned.hh:248: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:249: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:250: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:253: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:254: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:255: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:258: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:259: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:260: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:277: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:278: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:279: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:282: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:283: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:284: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:287: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:288: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:289: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:292: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:293: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:294: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:297: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:298: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsigned.hh:299: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsignedInABase.cc:63: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsignedInABase.cc:67: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsignedInABase.cc:68: ans ==> and
data/yosys-0.9/libs/bigint/BigUnsignedInABase.cc:70: ans ==> and
data/yosys-0.9/libs/bigint/testsuite.cc:284: ans ==> and
data/yosys-0.9/libs/bigint/testsuite.cc:285: ans ==> and
data/yosys-0.9/libs/bigint/testsuite.cc:286: ans ==> and
data/yosys-0.9/libs/bigint/testsuite.cc:301: ans ==> and
data/yosys-0.9/libs/bigint/testsuite.cc:302: ans ==> and
data/yosys-0.9/libs/bigint/testsuite.cc:303: ans ==> and
data/yosys-0.9/libs/ezsat/ezsat.cc:681: dervied ==> derived
data/yosys-0.9/libs/ezsat/testbench.cc:113: inconsistend ==> inconsistent
data/yosys-0.9/libs/minisat/00_PATCH_typofixes.patch:7: contraints ==> constraints
data/yosys-0.9/libs/minisat/00_PATCH_typofixes.patch:16: contraints ==> constraints
data/yosys-0.9/libs/minisat/Dimacs.h:35: lits ==> list
data/yosys-0.9/libs/minisat/Dimacs.h:37: lits ==> list
data/yosys-0.9/libs/minisat/Dimacs.h:43: lits ==> list
data/yosys-0.9/libs/minisat/Dimacs.h:49: lits ==> list
data/yosys-0.9/libs/minisat/Dimacs.h:70: lits ==> list
data/yosys-0.9/libs/minisat/Dimacs.h:71: lits ==> list
data/yosys-0.9/libs/minisat/SimpSolver.cc:504: wether ==> weather, whether
data/yosys-0.9/libs/minisat/SimpSolver.cc:645: assymetric ==> asymmetric
data/yosys-0.9/libs/minisat/SimpSolver.h:51: occurences ==> occurrences
data/yosys-0.9/libs/minisat/SimpSolver.h:73: managment ==> management
data/yosys-0.9/libs/minisat/SimpSolver.h:115: noticably ==> noticeably
data/yosys-0.9/libs/minisat/Solver.cc:644: assigment ==> assignment
data/yosys-0.9/libs/minisat/Solver.cc:704: assigment ==> assignment
data/yosys-0.9/libs/minisat/Solver.h:56: superflous ==> superfluous
data/yosys-0.9/libs/minisat/Solver.h:114: managment ==> management
data/yosys-0.9/libs/minisat/Solver.h:143: intitial ==> initial
data/yosys-0.9/libs/minisat/Solver.h:192: assigments ==> assignments
data/yosys-0.9/libs/minisat/Solver.h:222: exept ==> except, exempt
data/yosys-0.9/libs/minisat/Solver.h:222: wich ==> which
data/yosys-0.9/libs/minisat/SolverTypes.h:309: lits ==> list
data/yosys-0.9/libs/minisat/SolverTypes.h:311: lits ==> list
data/yosys-0.9/libs/minisat/SolverTypes.h:313: lits ==> list
data/yosys-0.9/libs/minisat/SolverTypes.h:314: lits ==> list
data/yosys-0.9/libs/minisat/SolverTypes.h:316: lits ==> list
data/yosys-0.9/libs/minisat/SolverTypes.h:316: lits ==> list
data/yosys-0.9/libs/minisat/SolverTypes.h:317: lits ==> list
data/yosys-0.9/libs/minisat/SolverTypes.h:317: lits ==> list
data/yosys-0.9/libs/minisat/SolverTypes.h:322: occurence ==> occurrence
data/yosys-0.9/libs/minisat/XAlloc.h:30: situtaions ==> situations
data/yosys-0.9/libs/subcircuit/README:140: Redundent ==> Redundant
data/yosys-0.9/libs/subcircuit/README:302: simly ==> simply, simile, smiley
data/yosys-0.9/manual/CHAPTER_Approach.tex:75: pass-thru ==> pass-through, pass through, passthrough
data/yosys-0.9/manual/CHAPTER_Eval.tex:51: Synopsys ==> Synopsis
data/yosys-0.9/manual/CHAPTER_Eval.tex:57: Synopsys ==> Synopsis
data/yosys-0.9/manual/CHAPTER_Eval.tex:61: Synopsys ==> Synopsis
data/yosys-0.9/manual/CHAPTER_Optimize.tex:314: Synopsys ==> Synopsis
data/yosys-0.9/manual/CHAPTER_Verilog.tex:107: synopsys ==> synopsis
data/yosys-0.9/manual/CHAPTER_Verilog.tex:108: synopsys ==> synopsis
data/yosys-0.9/manual/CHAPTER_Verilog.tex:111: synopsys ==> synopsis
data/yosys-0.9/manual/PRESENTATION_ExAdv.tex:181: mor ==> more
data/yosys-0.9/manual/PRESENTATION_ExAdv.tex:330: oder ==> order, odor
data/yosys-0.9/manual/PRESENTATION_Prog.tex:216: inout ==> input, in out
data/yosys-0.9/manual/PRESENTATION_Prog.tex:217: inout ==> input, in out
data/yosys-0.9/manual/literature.bib:115: Synopsys ==> Synopsis
data/yosys-0.9/manual/weblinks.bib:35: Verison ==> Version
data/yosys-0.9/manual/weblinks.bib:57: Linz ==> Lines
data/yosys-0.9/manual/weblinks.bib:125: Synopsys ==> Synopsis
data/yosys-0.9/manual/weblinks.bib:126: synopsys ==> synopsis
data/yosys-0.9/manual/APPNOTE_011_Design_Investigation.tex:1066: ist ==> is, it, its, it's, sit, list
data/yosys-0.9/manual/manual.tex:114: inout ==> input, in out
data/yosys-0.9/manual/CHAPTER_Overview.tex:237: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:183: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:373: folling ==> following, falling, rolling
data/yosys-0.9/manual/command-reference-manual.tex:586: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:591: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:1357: Synopsys ==> Synopsis
data/yosys-0.9/manual/command-reference-manual.tex:1403: thow ==> throw, tow
data/yosys-0.9/manual/command-reference-manual.tex:1448: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:1551: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:1559: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:3065: als ==> also
data/yosys-0.9/manual/command-reference-manual.tex:3193: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:4477: subract ==> subtract
data/yosys-0.9/manual/command-reference-manual.tex:5043: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:5061: inout ==> input, in out
data/yosys-0.9/manual/command-reference-manual.tex:5217: writen ==> written
data/yosys-0.9/manual/presentation.tex:52: inout ==> input, in out
data/yosys-0.9/manual/APPNOTE_011_Design_Investigation/foobaraddsub.v:1: ba ==> by, be
data/yosys-0.9/manual/APPNOTE_011_Design_Investigation/foobaraddsub.v:3: ba ==> by, be
data/yosys-0.9/manual/APPNOTE_011_Design_Investigation/foobaraddsub.v:6: ba ==> by, be
data/yosys-0.9/manual/CHAPTER_Prog/stubnets.cc:37: uniqe ==> unique
data/yosys-0.9/manual/PRESENTATION_ExSyn/memory_01.v:3: DOUT ==> DOUBT
data/yosys-0.9/manual/PRESENTATION_ExSyn/memory_01.v:7: DOUT ==> DOUBT
data/yosys-0.9/misc/yosys-config.in:11: ba ==> by, be
data/yosys-0.9/misc/yosys.proto:162: explicitely ==> explicitly
data/yosys-0.9/passes/cmds/add.cc:98: inout ==> input, in out
data/yosys-0.9/passes/cmds/show.cc:653: inout ==> input, in out
data/yosys-0.9/passes/cmds/splitnets.cc:40: upto ==> up to
data/yosys-0.9/passes/cmds/splitnets.cc:50: upto ==> up to
data/yosys-0.9/passes/equiv/equiv_miter.cc:197: inout ==> input, in out
data/yosys-0.9/passes/fsm/fsm_recode.cc:144: Synopsys ==> Synopsis
data/yosys-0.9/passes/hierarchy/hierarchy.cc:91: inout ==> input, in out
data/yosys-0.9/passes/hierarchy/hierarchy.cc:112: inout ==> input, in out
data/yosys-0.9/passes/hierarchy/hierarchy.cc:627: inout ==> input, in out
data/yosys-0.9/passes/hierarchy/hierarchy.cc:687: inout ==> input, in out
data/yosys-0.9/passes/hierarchy/submod.cc:90: inout ==> input, in out
data/yosys-0.9/passes/hierarchy/submod.cc:107: inout ==> input, in out
data/yosys-0.9/passes/hierarchy/submod.cc:160: inout ==> input, in out
data/yosys-0.9/passes/opt/pmux2shiftx.cc:686: creat ==> create
data/yosys-0.9/passes/pmgen/README.md:161: calulated ==> calculated
data/yosys-0.9/passes/sat/sat.cc:22: ist ==> is, it, its, it's, sit, list
data/yosys-0.9/passes/techmap/deminout.cc:27: inout ==> input, in out
data/yosys-0.9/passes/techmap/deminout.cc:33: inout ==> input, in out
data/yosys-0.9/passes/techmap/deminout.cc:38: inout ==> input, in out
data/yosys-0.9/passes/techmap/deminout.cc:130: inout ==> input, in out
data/yosys-0.9/passes/techmap/flowmap.cc:515: nd ==> and, 2nd
data/yosys-0.9/passes/techmap/iopadmap.cc:54: inout ==> input, in out
data/yosys-0.9/passes/techmap/iopadmap.cc:62: inout ==> input, in out
data/yosys-0.9/passes/techmap/iopadmap.cc:350: inout ==> input, in out
data/yosys-0.9/passes/techmap/libparse.cc:117: identifer ==> identifier
data/yosys-0.9/passes/techmap/libparse.cc:153: charater ==> character
data/yosys-0.9/passes/techmap/muxcover.cc:295: BA ==> BY, BE
data/yosys-0.9/techlibs/achronix/speedster22i/cells_map.v:47: dout ==> doubt
data/yosys-0.9/techlibs/achronix/speedster22i/cells_map.v:51: dout ==> doubt
data/yosys-0.9/techlibs/achronix/speedster22i/cells_map.v:55: dout ==> doubt
data/yosys-0.9/techlibs/achronix/speedster22i/cells_map.v:59: dout ==> doubt
data/yosys-0.9/techlibs/achronix/speedster22i/cells_sim.v:35: dout ==> doubt
data/yosys-0.9/techlibs/achronix/speedster22i/cells_sim.v:68: dout ==> doubt
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:55: dout ==> doubt
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:262: numer ==> number
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:719: ba ==> by, be
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:720: inout ==> input, in out
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:736: ba ==> by, be
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:737: inout ==> input, in out
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:751: inout ==> input, in out
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:775: NODEL ==> MODEL, NODAL
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:784: NODEL ==> MODEL, NODAL
data/yosys-0.9/techlibs/anlogic/eagle_bb.v:1017: dout ==> doubt
data/yosys-0.9/techlibs/coolrunner2/cells_sim.v:5: inout ==> input, in out
data/yosys-0.9/techlibs/ecp5/cells_map.v:80: OT ==> TO, OF, OR
data/yosys-0.9/techlibs/ecp5/cells_map.v:80: OT ==> TO, OF, OR
data/yosys-0.9/techlibs/ecp5/cells_map.v:81: inout ==> input, in out
data/yosys-0.9/techlibs/ecp5/cells_map.v:82: inout ==> input, in out
data/yosys-0.9/techlibs/ecp5/cells_map.v:83: inout ==> input, in out
data/yosys-0.9/techlibs/ecp5/cells_sim.v:256: inout ==> input, in out
data/yosys-0.9/techlibs/ecp5/cells_sim.v:566: OT ==> TO, OF, OR
data/yosys-0.9/techlibs/ecp5/cells_sim.v:566: OT ==> TO, OF, OR
data/yosys-0.9/techlibs/ecp5/cells_sim.v:567: inout ==> input, in out
data/yosys-0.9/techlibs/ecp5/cells_sim.v:568: inout ==> input, in out
data/yosys-0.9/techlibs/ecp5/cells_sim.v:569: inout ==> input, in out
data/yosys-0.9/techlibs/greenpak4/cells_sim_digital.v:723: inout ==> input, in out
data/yosys-0.9/techlibs/greenpak4/cells_sim_wip.v:104: inout ==> input, in out
data/yosys-0.9/techlibs/ice40/cells_sim.v:8: inout ==> input, in out
data/yosys-0.9/techlibs/ice40/cells_sim.v:25: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:59: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:67: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:69: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:75: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:76: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:77: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:83: inout ==> input, in out
data/yosys-0.9/techlibs/ice40/cells_sim.v:961: CURREN ==> CURRENT
data/yosys-0.9/techlibs/ice40/cells_sim.v:1034: inout ==> input, in out
data/yosys-0.9/techlibs/ice40/cells_sim.v:1083: inout ==> input, in out
data/yosys-0.9/techlibs/ice40/cells_sim.v:1131: inout ==> input, in out
data/yosys-0.9/techlibs/ice40/cells_sim.v:1151: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1176: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1184: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1186: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1192: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1193: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1194: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1200: inout ==> input, in out
data/yosys-0.9/techlibs/ice40/cells_sim.v:1215: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1240: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1248: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1250: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1256: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1257: dout ==> doubt
data/yosys-0.9/techlibs/ice40/cells_sim.v:1258: dout ==> doubt
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:233: ACI ==> ACPI
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:237: ACI ==> ACPI
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:258: ACI ==> ACPI
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:262: ACI ==> ACPI
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:283: ACI ==> ACPI
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:287: ACI ==> ACPI
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:308: ACI ==> ACPI
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:312: ACI ==> ACPI
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:333: ACI ==> ACPI
data/yosys-0.9/techlibs/ice40/tests/test_dsp_model.v:337: ACI ==> ACPI
data/yosys-0.9/techlibs/intel/common/altpll_bb.v:342: inout ==> input, in out
data/yosys-0.9/techlibs/sf2/cells_map.v:2: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_map.v:6: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_map.v:10: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_map.v:14: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_map.v:18: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_map.v:22: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_map.v:26: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_map.v:30: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_map.v:34: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_map.v:38: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_sim.v:114: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_sim.v:127: ADn ==> and
data/yosys-0.9/techlibs/sf2/cells_sim.v:138: ADn ==> and
data/yosys-0.9/techlibs/sf2/sf2_iobs.cc:63: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_sim.v:89: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.sh:11: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:110: DOUT ==> DOUBT
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2200: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2212: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2227: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2241: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2254: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2255: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2269: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2270: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2285: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2286: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2303: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2304: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:2368: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3302: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3303: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3304: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3305: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3306: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3307: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3308: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3309: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3310: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3311: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3312: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3313: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3314: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3315: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3316: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3317: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3318: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3319: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3320: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3321: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3322: inout ==> input, in out
data/yosys-0.9/techlibs/xilinx/cells_xtra.v:3827: OT ==> TO, OF, OR
data/yosys-0.9/tests/asicworld/code_hdl_models_arbiter.v:3: orginally ==> originally
data/yosys-0.9/tests/asicworld/code_hdl_models_gray_counter.v:11: hight ==> height, high
data/yosys-0.9/tests/asicworld/code_verilog_tutorial_addbit.v:12: Ouput ==> Output
data/yosys-0.9/tests/asicworld/code_verilog_tutorial_first_counter.v:31: trigged ==> triggered
data/yosys-0.9/tests/asicworld/code_verilog_tutorial_parity.v:22: Ouput ==> Output
data/yosys-0.9/tests/hana/test_parse2synthtrans.v:91: inout ==> input, in out
data/yosys-0.9/tests/hana/test_parse2synthtrans.v:99: inout ==> input, in out
data/yosys-0.9/tests/hana/test_parse2synthtrans.v:100: inout ==> input, in out
data/yosys-0.9/tests/hana/test_parser.v:11: inout ==> input, in out
data/yosys-0.9/tests/hana/test_parser.v:14: inout ==> input, in out
data/yosys-0.9/tests/hana/test_parser.v:22: inout ==> input, in out
data/yosys-0.9/tests/hana/test_parser.v:25: inout ==> input, in out
data/yosys-0.9/tests/simple/implicit_ports.v:12: Explicitely ==> Explicitly
data/yosys-0.9/tests/simple/mem2reg.v:97: dout ==> doubt
data/yosys-0.9/tests/simple/mem2reg.v:99: dout ==> doubt
data/yosys-0.9/tests/simple/mem2reg.v:113: dout ==> doubt
data/yosys-0.9/tests/simple/mem2reg.v:114: dout ==> doubt
data/yosys-0.9/tests/simple/memory.v:140: dout ==> doubt
data/yosys-0.9/tests/simple/memory.v:156: dout ==> doubt
data/yosys-0.9/tests/simple/memory.v:159: dout ==> doubt
data/yosys-0.9/tests/simple/memory.v:175: dout ==> doubt
data/yosys-0.9/tests/simple/memory.v:233: dout ==> doubt
data/yosys-0.9/tests/simple/memory.v:244: dout ==> doubt
data/yosys-0.9/tests/simple/muxtree.v:34: synopsys ==> synopsis
data/yosys-0.9/tests/various/chparam.sh:10: dout ==> doubt
data/yosys-0.9/tests/various/chparam.sh:12: dout ==> doubt
data/yosys-0.9/tests/various/chparam.sh:18: dout ==> doubt
data/yosys-0.9/tests/various/chparam.sh:20: dout ==> doubt
data/yosys-0.9/tests/various/chparam.sh:31: dout ==> doubt
data/yosys-0.9/tests/various/chparam.sh:33: dout ==> doubt
data/yosys-0.9/tests/various/chparam.sh:34: dout ==> doubt
data/yosys-0.9/debian/yosys.lintian-overrides:2: upto ==> up to
data/yosys-0.9/debian/patches/0009-Some-spelling-errors-fixed.patch:19: continous ==> continuous
data/yosys-0.9/debian/patches/0009-Some-spelling-errors-fixed.patch:32: busses ==> buses
data/yosys-0.9/debian/patches/0009-Some-spelling-errors-fixed.patch:45: busses ==> buses
data/yosys-0.9/.pc/01_gitrevision.patch/Makefile:319: manualy ==> manually
data/yosys-0.9/.pc/02_removeabc.patch/Makefile:319: manualy ==> manually
data/yosys-0.9/.pc/switch-to-free-font.patch/manual/APPNOTE_011_Design_Investigation.tex:1066: ist ==> is, it, its, it's, sit, list
data/yosys-0.9/.pc/switch-to-free-font.patch/manual/manual.tex:114: inout ==> input, in out
data/yosys-0.9/.pc/switch-to-free-font.patch/manual/presentation.tex:52: inout ==> input, in out
data/yosys-0.9/.pc/0007-Disable-pretty-build.patch/Makefile:319: manualy ==> manually
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/frontends/ast/genrtlil.cc:561: continous ==> continuous
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/frontends/ast/genrtlil.cc:889: upto ==> up to
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/frontends/ast/genrtlil.cc:936: upto ==> up to
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/CHAPTER_Overview.tex:237: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/CHAPTER_Overview.tex:243: busses ==> buses
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:183: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:373: folling ==> following, falling, rolling
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:586: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:591: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:1357: Synopsys ==> Synopsis
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:1403: thow ==> throw, tow
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:1448: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:1551: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:1559: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:3065: als ==> also
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:3185: busses ==> buses
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:3193: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:4477: subract ==> subtract
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:5043: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:5061: inout ==> input, in out
data/yosys-0.9/.pc/0009-Some-spelling-errors-fixed.patch/manual/command-reference-manual.tex:5217: writen ==> written
data/yosys-0.9/.pc/0010-Fix-reproducibility-of-PDF-documents-in-yosys-doc.patch/Makefile:319: manualy ==> manually
data/yosys-0.9/.pc/0010-Fix-reproducibility-of-PDF-documents-in-yosys-doc.patch/manual/presentation.tex:52: inout ==> input, in out
data/yosys-0.9/.pc/0011-Do-not-show-g-build-flags-in-Version-string.patch/Makefile:319: manualy ==> manually
data/yosys-0.9/.pc/0012-Skip-non-deterministic-test-causing-random-FTBFS-on-.patch/Makefile:319: manualy ==> manually
data/yosys-0.9/.pc/0013-Let-dpkg-buildpackage-handle-stripping-of-binaries.patch/Makefile:319: manualy ==> manually