===========================================================
.___ __ __
_________________ __ __ __| _/|__|/ |_
/ ___\_` __ \__ \ | | \/ __ | | \\_ __\
/ /_/ > | \// __ \| | / /_/ | | || |
\___ /|__| (____ /____/\____ | |__||__|
/_____/ \/ \/
grep rough audit - static analysis tool
v2.8 written by @Wireghoul
=================================[justanotherhacker.com]===
qemu-5.1+dfsg/accel/kvm/kvm-all.c-578- ram_addr_t start = section->offset_within_region +
qemu-5.1+dfsg/accel/kvm/kvm-all.c:579: memory_region_get_ram_addr(section->mr);
qemu-5.1+dfsg/accel/kvm/kvm-all.c-580- ram_addr_t pages = int128_get64(section->size) / qemu_real_host_page_size;
##############################################
qemu-5.1+dfsg/accel/tcg/cpu-exec.c-148-
qemu-5.1+dfsg/accel/tcg/cpu-exec.c:149: qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
qemu-5.1+dfsg/accel/tcg/cpu-exec.c-150- "Trace %d: %p ["
##############################################
qemu-5.1+dfsg/accel/tcg/cpu-exec.c-183- CPUClass *cc = CPU_GET_CLASS(cpu);
qemu-5.1+dfsg/accel/tcg/cpu-exec.c:184: qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc,
qemu-5.1+dfsg/accel/tcg/cpu-exec.c-185- "Stopped execution of TB chain before %p ["
##############################################
qemu-5.1+dfsg/accel/tcg/cpu-exec.c-383-
qemu-5.1+dfsg/accel/tcg/cpu-exec.c:384: qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
qemu-5.1+dfsg/accel/tcg/cpu-exec.c-385- "Linking TBs %p [" TARGET_FMT_lx
##############################################
qemu-5.1+dfsg/accel/tcg/cputlb.c-883- if (is_ram) {
qemu-5.1+dfsg/accel/tcg/cputlb.c:884: iotlb = memory_region_get_ram_addr(section->mr) + xlat;
qemu-5.1+dfsg/accel/tcg/cputlb.c-885- /*
##############################################
qemu-5.1+dfsg/accel/tcg/tcg-runtime.c-158- }
qemu-5.1+dfsg/accel/tcg/tcg-runtime.c:159: qemu_log_mask_and_addr(CPU_LOG_EXEC, pc,
qemu-5.1+dfsg/accel/tcg/tcg-runtime.c-160- "Chain %d: %p ["
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-167- */
qemu-5.1+dfsg/accel/tcg/user-exec.c:168: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-169- cpu_exit_tb_from_sighandler(cpu, old_set);
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-185- sigprocmask(SIG_SETMASK, old_set, NULL);
qemu-5.1+dfsg/accel/tcg/user-exec.c:186: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-187-
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-914-
qemu-5.1+dfsg/accel/tcg/user-exec.c:915: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-916- ret = cpu_ldub_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:917: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-918- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-924-
qemu-5.1+dfsg/accel/tcg/user-exec.c:925: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-926- ret = cpu_ldsb_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:927: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-928- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-934-
qemu-5.1+dfsg/accel/tcg/user-exec.c:935: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-936- ret = cpu_lduw_be_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:937: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-938- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-944-
qemu-5.1+dfsg/accel/tcg/user-exec.c:945: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-946- ret = cpu_ldsw_be_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:947: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-948- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-954-
qemu-5.1+dfsg/accel/tcg/user-exec.c:955: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-956- ret = cpu_ldl_be_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:957: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-958- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-964-
qemu-5.1+dfsg/accel/tcg/user-exec.c:965: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-966- ret = cpu_ldq_be_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:967: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-968- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-974-
qemu-5.1+dfsg/accel/tcg/user-exec.c:975: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-976- ret = cpu_lduw_le_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:977: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-978- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-984-
qemu-5.1+dfsg/accel/tcg/user-exec.c:985: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-986- ret = cpu_ldsw_le_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:987: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-988- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-994-
qemu-5.1+dfsg/accel/tcg/user-exec.c:995: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-996- ret = cpu_ldl_le_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:997: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-998- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1004-
qemu-5.1+dfsg/accel/tcg/user-exec.c:1005: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1006- ret = cpu_ldq_le_data(env, ptr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:1007: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1008- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1076-{
qemu-5.1+dfsg/accel/tcg/user-exec.c:1077: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1078- cpu_stb_data(env, ptr, val);
qemu-5.1+dfsg/accel/tcg/user-exec.c:1079: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1080-}
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1084-{
qemu-5.1+dfsg/accel/tcg/user-exec.c:1085: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1086- cpu_stw_be_data(env, ptr, val);
qemu-5.1+dfsg/accel/tcg/user-exec.c:1087: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1088-}
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1092-{
qemu-5.1+dfsg/accel/tcg/user-exec.c:1093: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1094- cpu_stl_be_data(env, ptr, val);
qemu-5.1+dfsg/accel/tcg/user-exec.c:1095: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1096-}
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1100-{
qemu-5.1+dfsg/accel/tcg/user-exec.c:1101: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1102- cpu_stq_be_data(env, ptr, val);
qemu-5.1+dfsg/accel/tcg/user-exec.c:1103: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1104-}
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1108-{
qemu-5.1+dfsg/accel/tcg/user-exec.c:1109: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1110- cpu_stw_le_data(env, ptr, val);
qemu-5.1+dfsg/accel/tcg/user-exec.c:1111: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1112-}
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1116-{
qemu-5.1+dfsg/accel/tcg/user-exec.c:1117: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1118- cpu_stl_le_data(env, ptr, val);
qemu-5.1+dfsg/accel/tcg/user-exec.c:1119: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1120-}
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1124-{
qemu-5.1+dfsg/accel/tcg/user-exec.c:1125: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1126- cpu_stq_le_data(env, ptr, val);
qemu-5.1+dfsg/accel/tcg/user-exec.c:1127: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1128-}
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1133-
qemu-5.1+dfsg/accel/tcg/user-exec.c:1134: set_helper_retaddr(1);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1135- ret = ldub_p(g2h(ptr));
qemu-5.1+dfsg/accel/tcg/user-exec.c:1136: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1137- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1143-
qemu-5.1+dfsg/accel/tcg/user-exec.c:1144: set_helper_retaddr(1);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1145- ret = lduw_p(g2h(ptr));
qemu-5.1+dfsg/accel/tcg/user-exec.c:1146: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1147- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1153-
qemu-5.1+dfsg/accel/tcg/user-exec.c:1154: set_helper_retaddr(1);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1155- ret = ldl_p(g2h(ptr));
qemu-5.1+dfsg/accel/tcg/user-exec.c:1156: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1157- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1163-
qemu-5.1+dfsg/accel/tcg/user-exec.c:1164: set_helper_retaddr(1);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1165- ret = ldq_p(g2h(ptr));
qemu-5.1+dfsg/accel/tcg/user-exec.c:1166: clear_helper_retaddr();
qemu-5.1+dfsg/accel/tcg/user-exec.c-1167- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1178- void *ret = g2h(addr);
qemu-5.1+dfsg/accel/tcg/user-exec.c:1179: set_helper_retaddr(retaddr);
qemu-5.1+dfsg/accel/tcg/user-exec.c-1180- return ret;
##############################################
qemu-5.1+dfsg/accel/tcg/user-exec.c-1185-#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
qemu-5.1+dfsg/accel/tcg/user-exec.c:1186:#define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0)
qemu-5.1+dfsg/accel/tcg/user-exec.c-1187-#define ATOMIC_MMU_IDX MMU_USER_IDX
##############################################
qemu-5.1+dfsg/accel/xen/xen-all.c-132-
qemu-5.1+dfsg/accel/xen/xen-all.c:133:static bool xen_get_igd_gfx_passthru(Object *obj, Error **errp)
qemu-5.1+dfsg/accel/xen/xen-all.c-134-{
##############################################
qemu-5.1+dfsg/accel/xen/xen-all.c-137-
qemu-5.1+dfsg/accel/xen/xen-all.c:138:static void xen_set_igd_gfx_passthru(Object *obj, bool value, Error **errp)
qemu-5.1+dfsg/accel/xen/xen-all.c-139-{
##############################################
qemu-5.1+dfsg/audio/audio.c-126-# elif defined _MSC_VER
qemu-5.1+dfsg/audio/audio.c:127: _asm _emit 0xcc;
qemu-5.1+dfsg/audio/audio.c-128-# else
##############################################
qemu-5.1+dfsg/backends/dbus-vmstate.c-434-static char *
qemu-5.1+dfsg/backends/dbus-vmstate.c:435:get_dbus_addr(Object *o, Error **errp)
qemu-5.1+dfsg/backends/dbus-vmstate.c-436-{
##############################################
qemu-5.1+dfsg/backends/dbus-vmstate.c-442-static void
qemu-5.1+dfsg/backends/dbus-vmstate.c:443:set_dbus_addr(Object *o, const char *str, Error **errp)
qemu-5.1+dfsg/backends/dbus-vmstate.c-444-{
##############################################
qemu-5.1+dfsg/block/qcow2-cache.c-46-
qemu-5.1+dfsg/block/qcow2-cache.c:47:static inline void *qcow2_cache_get_table_addr(Qcow2Cache *c, int table)
qemu-5.1+dfsg/block/qcow2-cache.c-48-{
##############################################
qemu-5.1+dfsg/block/qcow2-cache.c-75-#ifdef CONFIG_LINUX
qemu-5.1+dfsg/block/qcow2-cache.c:76: void *t = qcow2_cache_get_table_addr(c, i);
qemu-5.1+dfsg/block/qcow2-cache.c-77- int align = qemu_real_host_page_size;
##############################################
qemu-5.1+dfsg/block/qcow2-cache.c-225- ret = bdrv_pwrite(bs->file, c->entries[i].offset,
qemu-5.1+dfsg/block/qcow2-cache.c:226: qcow2_cache_get_table_addr(c, i), c->table_size);
qemu-5.1+dfsg/block/qcow2-cache.c-227- if (ret < 0) {
##############################################
qemu-5.1+dfsg/block/qcow2-cache.c-381- ret = bdrv_pread(bs->file, offset,
qemu-5.1+dfsg/block/qcow2-cache.c:382: qcow2_cache_get_table_addr(c, i),
qemu-5.1+dfsg/block/qcow2-cache.c-383- c->table_size);
##############################################
qemu-5.1+dfsg/block/qcow2-cache.c-393- c->entries[i].ref++;
qemu-5.1+dfsg/block/qcow2-cache.c:394: *table = qcow2_cache_get_table_addr(c, i);
qemu-5.1+dfsg/block/qcow2-cache.c-395-
##############################################
qemu-5.1+dfsg/block/qcow2-cache.c-440- if (c->entries[i].offset == offset) {
qemu-5.1+dfsg/block/qcow2-cache.c:441: return qcow2_cache_get_table_addr(c, i);
qemu-5.1+dfsg/block/qcow2-cache.c-442- }
##############################################
qemu-5.1+dfsg/block/ssh.c-683- /* Open the socket and connect. */
qemu-5.1+dfsg/block/ssh.c:684: new_sock = inet_connect_saddr(s->inet, errp);
qemu-5.1+dfsg/block/ssh.c-685- if (new_sock < 0) {
##############################################
qemu-5.1+dfsg/block/vvfat.c-49-/* LATER TODO: add automatic boot sector generation from
qemu-5.1+dfsg/block/vvfat.c:50: BOOTEASY.ASM and Ranish Partition Manager
qemu-5.1+dfsg/block/vvfat.c-51- Note that DOS assumes the system files to be the first files in the
##############################################
qemu-5.1+dfsg/bsd-user/strace.c-110-
qemu-5.1+dfsg/bsd-user/strace.c:111:static void print_syscall_ret_addr(const struct syscallname *name, abi_long ret)
qemu-5.1+dfsg/bsd-user/strace.c-112-{
##############################################
qemu-5.1+dfsg/chardev/char-socket.c-1465-static void
qemu-5.1+dfsg/chardev/char-socket.c:1466:char_socket_get_addr(Object *obj, Visitor *v, const char *name,
qemu-5.1+dfsg/chardev/char-socket.c-1467- void *opaque, Error **errp)
##############################################
qemu-5.1+dfsg/configure-3075-
qemu-5.1+dfsg/configure:3076: maj=`libgcrypt-config --version | awk -F . '{print $1}'`
qemu-5.1+dfsg/configure:3077: min=`libgcrypt-config --version | awk -F . '{print $2}'`
qemu-5.1+dfsg/configure-3078-
##############################################
qemu-5.1+dfsg/configure-8058- esac
qemu-5.1+dfsg/configure:8059: # For non-KVM architectures we will not have asm headers
qemu-5.1+dfsg/configure-8060- if [ -e "$source_path/linux-headers/asm-$linux_arch" ]; then
##############################################
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-134-
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c:135:static uint64_t get_paddr(uint64_t va, uint64_t pte)
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-136-{
##############################################
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-149-
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c:150:static uint64_t get_1GB_paddr(uint64_t va, uint64_t pdpte)
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-151-{
##############################################
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-154-
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c:155:static uint64_t get_2MB_paddr(uint64_t va, uint64_t pgd_entry)
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-156-{
##############################################
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-174- if (page_size_flag(pdpe)) {
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c:175: return get_1GB_paddr(va, pdpe);
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-176- }
##############################################
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-183- if (page_size_flag(pgd)) {
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c:184: return get_2MB_paddr(va, pgd);
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-185- }
##############################################
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-191-
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c:192: return get_paddr(va, pte);
qemu-5.1+dfsg/contrib/elf2dmp/addrspace.c-193-}
##############################################
qemu-5.1+dfsg/contrib/elf2dmp/main.c-32-
qemu-5.1+dfsg/contrib/elf2dmp/main.c:33:static uint64_t idt_desc_addr(idt_desc_t desc)
qemu-5.1+dfsg/contrib/elf2dmp/main.c-34-{
##############################################
qemu-5.1+dfsg/contrib/elf2dmp/main.c-509- }
qemu-5.1+dfsg/contrib/elf2dmp/main.c:510: printf("CPU #0 IDT[0] -> 0x%016"PRIx64"\n", idt_desc_addr(first_idt_desc));
qemu-5.1+dfsg/contrib/elf2dmp/main.c-511-
qemu-5.1+dfsg/contrib/elf2dmp/main.c:512: KernBase = idt_desc_addr(first_idt_desc) & ~(PAGE_SIZE - 1);
qemu-5.1+dfsg/contrib/elf2dmp/main.c-513- printf("Searching kernel downwards from 0x%016"PRIx64"...\n", KernBase);
##############################################
qemu-5.1+dfsg/crypto/aes.c-1600-
qemu-5.1+dfsg/crypto/aes.c:1601:#endif /* AES_ASM */
qemu-5.1+dfsg/crypto/aes.c-1602-
##############################################
qemu-5.1+dfsg/crypto/afalg.c-19-static bool
qemu-5.1+dfsg/crypto/afalg.c:20:qcrypto_afalg_build_saddr(const char *type, const char *name,
qemu-5.1+dfsg/crypto/afalg.c-21- struct sockaddr_alg *salg, Error **errp)
##############################################
qemu-5.1+dfsg/crypto/afalg.c-49-
qemu-5.1+dfsg/crypto/afalg.c:50: if (!qcrypto_afalg_build_saddr(type, name, &salg, errp)) {
qemu-5.1+dfsg/crypto/afalg.c-51- return -1;
##############################################
qemu-5.1+dfsg/disas/arm-a64.cc-29-static Decoder *vixl_decoder = NULL;
qemu-5.1+dfsg/disas/arm-a64.cc:30:static Disassembler *vixl_disasm = NULL;
qemu-5.1+dfsg/disas/arm-a64.cc-31-
##############################################
qemu-5.1+dfsg/disas/arm-a64.cc-67- vixl_decoder = new Decoder();
qemu-5.1+dfsg/disas/arm-a64.cc:68: vixl_disasm = new QEMUDisassembler();
qemu-5.1+dfsg/disas/arm-a64.cc-69- vixl_decoder->AppendVisitor(vixl_disasm);
##############################################
qemu-5.1+dfsg/disas/i386.c-288-/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
qemu-5.1+dfsg/disas/i386.c:289: to ADDR (exclusive) are valid. Returns 1 for success, longjmps
qemu-5.1+dfsg/disas/i386.c-290- on error. */
##############################################
qemu-5.1+dfsg/disas/libvixl/vixl/a64/disasm-a64.cc-2649-void Disassembler::ProcessOutput(const Instruction* /*instr*/) {
qemu-5.1+dfsg/disas/libvixl/vixl/a64/disasm-a64.cc:2650: // The base disasm does nothing more than disassembling into a buffer.
qemu-5.1+dfsg/disas/libvixl/vixl/a64/disasm-a64.cc-2651-}
##############################################
qemu-5.1+dfsg/disas/m68k.c-627-/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
qemu-5.1+dfsg/disas/m68k.c:628: to ADDR (exclusive) are valid. Returns 1 for success, longjmps
qemu-5.1+dfsg/disas/m68k.c-629- on error. */
##############################################
qemu-5.1+dfsg/disas/s390.c-206-static void
qemu-5.1+dfsg/disas/s390.c:207:init_disasm (struct disassemble_info *info)
qemu-5.1+dfsg/disas/s390.c-208-{
##############################################
qemu-5.1+dfsg/disas/s390.c-288- if (init_flag == 0)
qemu-5.1+dfsg/disas/s390.c:289: init_disasm (info);
qemu-5.1+dfsg/disas/s390.c-290-
##############################################
qemu-5.1+dfsg/disas.c-534- } else {
qemu-5.1+dfsg/disas.c:535: g_string_printf(s, "cs_disasm failed");
qemu-5.1+dfsg/disas.c-536- }
##############################################
qemu-5.1+dfsg/disas.c-765- monitor_printf(mon, "0x" TARGET_FMT_lx
qemu-5.1+dfsg/disas.c:766: ": Asm output not supported on this arch\n", pc);
qemu-5.1+dfsg/disas.c-767- return;
##############################################
qemu-5.1+dfsg/docs/devel/build-system.txt-73- if ! $pkg_config --exists "gnutls"; then
qemu-5.1+dfsg/docs/devel/build-system.txt:74: gnutls_cflags=`$pkg_config --cflags gnutls`
qemu-5.1+dfsg/docs/devel/build-system.txt:75: gnutls_libs=`$pkg_config --libs gnutls`
qemu-5.1+dfsg/docs/devel/build-system.txt-76- libs_softmmu="$gnutls_libs $libs_softmmu"
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-44-3. Add the test to ``tests/Makefile.include``. First, name the unit test
qemu-5.1+dfsg/docs/devel/testing.rst:45: program and add it to ``$(check-unit-y)``; then add a rule to build the
qemu-5.1+dfsg/docs/devel/testing.rst-46- executable. For example:
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-56-``gdb``. However there can still be differences in behavior between ``make``
qemu-5.1+dfsg/docs/devel/testing.rst:57:invocations and your manual run, due to ``$MALLOC_PERTURB_`` environment
qemu-5.1+dfsg/docs/devel/testing.rst-58-variable (which affects memory reclamation and catches invalid pointers better)
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-104-
qemu-5.1+dfsg/docs/devel/testing.rst:105: ``check-qtest-generic-y = tests/qtest/foo-test$(EXESUF)``
qemu-5.1+dfsg/docs/devel/testing.rst-106-
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-109-
qemu-5.1+dfsg/docs/devel/testing.rst:110: ``tests/qtest/foo-test$(EXESUF): tests/qtest/foo-test.o $(libqos-obj-y)``
qemu-5.1+dfsg/docs/devel/testing.rst-111-
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-134-
qemu-5.1+dfsg/docs/devel/testing.rst:135: * ``${casename}.json`` - the file contains the JSON input for feeding the
qemu-5.1+dfsg/docs/devel/testing.rst-136- parser
qemu-5.1+dfsg/docs/devel/testing.rst:137: * ``${casename}.out`` - the file contains the expected stdout from the parser
qemu-5.1+dfsg/docs/devel/testing.rst:138: * ``${casename}.err`` - the file contains the expected stderr from the parser
qemu-5.1+dfsg/docs/devel/testing.rst:139: * ``${casename}.exit`` - the expected error code
qemu-5.1+dfsg/docs/devel/testing.rst-140-
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-145-
qemu-5.1+dfsg/docs/devel/testing.rst:146: ``$EDITOR tests/qapi-schema/foo.{json,out,err,exit}``.
qemu-5.1+dfsg/docs/devel/testing.rst-147-
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-393- container and enable verbose output.
qemu-5.1+dfsg/docs/devel/testing.rst:394:* ``J=$N``: the number of parallel tasks in make commands in the container,
qemu-5.1+dfsg/docs/devel/testing.rst:395: similar to the ``-j $N`` option in top level ``make``. (The ``-j`` option in
qemu-5.1+dfsg/docs/devel/testing.rst-396- top level ``make`` will not be propagated into the container.)
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-540-
qemu-5.1+dfsg/docs/devel/testing.rst:541:The ``-j$X`` option in the make command line is not propagated into the VM,
qemu-5.1+dfsg/docs/devel/testing.rst:542:specify ``J=$X`` to control the make jobs in the guest.
qemu-5.1+dfsg/docs/devel/testing.rst-543-
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-554-Each guest script is an executable script with the same command line options.
qemu-5.1+dfsg/docs/devel/testing.rst:555:For example to work with the netbsd guest, use ``$QEMU_SRC/tests/vm/netbsd``:
qemu-5.1+dfsg/docs/devel/testing.rst-556-
##############################################
qemu-5.1+dfsg/docs/devel/testing.rst-594- - SSH service is enabled and started on boot,
qemu-5.1+dfsg/docs/devel/testing.rst:595: ``$QEMU_SRC/tests/keys/id_rsa.pub`` is added to ssh's ``authorized_keys``
qemu-5.1+dfsg/docs/devel/testing.rst-596- file of both root and the normal user
##############################################
qemu-5.1+dfsg/docs/system/deprecated.rst-569-
qemu-5.1+dfsg/docs/system/deprecated.rst:570:The ``qemu-nbd --partition $digit`` code (also spelled ``-P``)
qemu-5.1+dfsg/docs/system/deprecated.rst-571-could only handle MBR partitions, and never correctly handled logical
##############################################
qemu-5.1+dfsg/docs/system/deprecated.rst-590-
qemu-5.1+dfsg/docs/system/deprecated.rst:591:``qemu-img create -b bad file $size`` (removed in 5.1)
qemu-5.1+dfsg/docs/system/deprecated.rst-592-''''''''''''''''''''''''''''''''''''''''''''''''''''''
##############################################
qemu-5.1+dfsg/docs/system/gdb.rst-42-
qemu-5.1+dfsg/docs/system/gdb.rst:43:2. Use ``x/10i $eip`` to display the code at the PC position.
qemu-5.1+dfsg/docs/system/gdb.rst-44-
qemu-5.1+dfsg/docs/system/gdb.rst-45-3. Use ``set architecture i8086`` to dump 16 bit code. Then use
qemu-5.1+dfsg/docs/system/gdb.rst:46: ``x/10i $cs*16+$eip`` to dump the code at the PC position.
qemu-5.1+dfsg/docs/system/gdb.rst-47-
##############################################
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-523-
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst:524: ``$model``
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-525- is the CPU model defined for the guest (defaults to the model of
##############################################
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-531- is ``ap=on``. AP facilities must be installed on the guest if a
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst:532: vfio-ap device (``-device vfio-ap,sysfsdev=$path``) is configured
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-533- for the guest, or the guest will fail to start.
##############################################
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-546-
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst:547: ``$model``
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-548- is the CPU model defined for the guest
##############################################
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-576-
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst:577: ``$model``
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-578- is the CPU model defined for the guest (defaults to the model of
##############################################
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-610-
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst:611:Where the ``$path-to-mdev`` value specifies the absolute path to a mediated
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-612-device to which AP resources to be used by the guest have been assigned.
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst:613:``$id`` is the name value for the optional id parameter.
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-614-
##############################################
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-637-
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst:638:Where ``$id`` is the same id that was specified at device creation.
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-639-
##############################################
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-644-
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst:645:The command will fail if the ``$path-to-mdev`` specified on the ``device_del`` command
qemu-5.1+dfsg/docs/system/s390x/vfio-ap.rst-646-does not match the value specified when the vfio-ap device was attached to
##############################################
qemu-5.1+dfsg/docs/system/tls.rst-39-The recommendation is for the server to keep its certificates in either
qemu-5.1+dfsg/docs/system/tls.rst:40:``/etc/pki/qemu`` or for unprivileged users in ``$HOME/.pki/qemu``.
qemu-5.1+dfsg/docs/system/tls.rst-41-
##############################################
qemu-5.1+dfsg/docs/system/vnc-security.rst-73-Unprivileged users will want to use a private directory, for example
qemu-5.1+dfsg/docs/system/vnc-security.rst:74:``$HOME/.pki/qemu``. NB the ``server-key.pem`` file should be protected
qemu-5.1+dfsg/docs/system/vnc-security.rst-75-with file mode 0600 to only be readable by the user owning it.
##############################################
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-38- If *BINARY* is not an absolute path, it will be located by searching
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst:39: the directories listed in the ``$PATH`` environment variable.
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-40-
##############################################
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-55- To filter the list to only cover probes related to QEMU's cryptographic
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst:56: subsystem, in a binary outside ``$PATH``
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-57-
##############################################
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-67- If *BINARY* is not an absolute path, it will be located by searching
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst:68: the directories listed in the ``$PATH`` environment variable.
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-69-
##############################################
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-92- For example, to monitor all processes executing ``qemu-system-x86_64``
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst:93: as found on ``$PATH``, displaying all I/O related probes:
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-94-
##############################################
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-105- To monitor QEMU processes running an alternative binary outside of
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst:106: ``$PATH``, displaying verbose information about setup of the
qemu-5.1+dfsg/docs/tools/qemu-trace-stap.rst-107- tracing environment:
##############################################
qemu-5.1+dfsg/docs/user/main.rst-101- ``/usr/local/qemu-i386/bin/wine-conf.sh``. Your previous
qemu-5.1+dfsg/docs/user/main.rst:102: ``${HOME}/.wine`` directory is saved to ``${HOME}/.wine.org``.
qemu-5.1+dfsg/docs/user/main.rst-103-
##############################################
qemu-5.1+dfsg/dump/dump.c-1112-
qemu-5.1+dfsg/dump/dump.c:1113:static uint64_t dump_pfn_to_paddr(DumpState *s, uint64_t pfn)
qemu-5.1+dfsg/dump/dump.c-1114-{
##############################################
qemu-5.1+dfsg/dump/dump.c-1146- *pfnptr = *pfnptr + 1;
qemu-5.1+dfsg/dump/dump.c:1147: addr = dump_pfn_to_paddr(s, *pfnptr);
qemu-5.1+dfsg/dump/dump.c-1148-
##############################################
qemu-5.1+dfsg/exec.c-316-
qemu-5.1+dfsg/exec.c:317:static inline bool section_covers_addr(const MemoryRegionSection *section,
qemu-5.1+dfsg/exec.c-318- hwaddr addr)
##############################################
qemu-5.1+dfsg/exec.c-343-
qemu-5.1+dfsg/exec.c:344: if (section_covers_addr(§ions[lp.ptr], addr)) {
qemu-5.1+dfsg/exec.c-345- return §ions[lp.ptr];
##############################################
qemu-5.1+dfsg/exec.c-359- if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
qemu-5.1+dfsg/exec.c:360: !section_covers_addr(section, addr)) {
qemu-5.1+dfsg/exec.c-361- section = phys_page_find(d, addr);
##############################################
qemu-5.1+dfsg/exec.c-973-#if defined(CONFIG_USER_ONLY)
qemu-5.1+dfsg/exec.c:974:void tb_invalidate_phys_addr(target_ulong addr)
qemu-5.1+dfsg/exec.c-975-{
##############################################
qemu-5.1+dfsg/exec.c-982-{
qemu-5.1+dfsg/exec.c:983: tb_invalidate_phys_addr(pc);
qemu-5.1+dfsg/exec.c-984-}
qemu-5.1+dfsg/exec.c-985-#else
qemu-5.1+dfsg/exec.c:986:void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
qemu-5.1+dfsg/exec.c-987-{
##############################################
qemu-5.1+dfsg/exec.c-1001- }
qemu-5.1+dfsg/exec.c:1002: ram_addr = memory_region_get_ram_addr(mr) + addr;
qemu-5.1+dfsg/exec.c-1003- tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
##############################################
qemu-5.1+dfsg/exec.c-1355- DirtyMemoryBlocks *blocks;
qemu-5.1+dfsg/exec.c:1356: ram_addr_t start = memory_region_get_ram_addr(mr) + offset;
qemu-5.1+dfsg/exec.c-1357- unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
##############################################
qemu-5.1+dfsg/exec.c-1984-
qemu-5.1+dfsg/exec.c:1985:void *qemu_ram_get_host_addr(RAMBlock *rb)
qemu-5.1+dfsg/exec.c-1986-{
##############################################
qemu-5.1+dfsg/exec.c-3074- uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
qemu-5.1+dfsg/exec.c:3075: addr += memory_region_get_ram_addr(mr);
qemu-5.1+dfsg/exec.c-3076-
##############################################
qemu-5.1+dfsg/.gitlab-ci.d/edk2/Dockerfile-21- make \
qemu-5.1+dfsg/.gitlab-ci.d/edk2/Dockerfile:22: nasm \
qemu-5.1+dfsg/.gitlab-ci.d/edk2/Dockerfile-23- python \
##############################################
qemu-5.1+dfsg/hmp-commands.hx-470- can be x (hex), d (signed decimal), u (unsigned decimal), o (octal),
qemu-5.1+dfsg/hmp-commands.hx:471: c (char) or i (asm instruction).
qemu-5.1+dfsg/hmp-commands.hx-472- *size*
##############################################
qemu-5.1+dfsg/hw/arm/armv7m.c-28-/* Get the byte address of the real memory for a bitband access. */
qemu-5.1+dfsg/hw/arm/armv7m.c:29:static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
qemu-5.1+dfsg/hw/arm/armv7m.c-30-{
##############################################
qemu-5.1+dfsg/hw/arm/armv7m.c-45- /* Find address in underlying memory and round down to multiple of size */
qemu-5.1+dfsg/hw/arm/armv7m.c:46: addr = bitband_addr(s, offset) & (-size);
qemu-5.1+dfsg/hw/arm/armv7m.c-47- res = address_space_read(&s->source_as, addr, attrs, buf, size);
##############################################
qemu-5.1+dfsg/hw/arm/armv7m.c-70- /* Find address in underlying memory and round down to multiple of size */
qemu-5.1+dfsg/hw/arm/armv7m.c:71: addr = bitband_addr(s, offset) & (-size);
qemu-5.1+dfsg/hw/arm/armv7m.c-72- res = address_space_read(&s->source_as, addr, attrs, buf, size);
##############################################
qemu-5.1+dfsg/hw/arm/exynos4210.c-80-#define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000
qemu-5.1+dfsg/hw/arm/exynos4210.c:81:#define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \
qemu-5.1+dfsg/hw/arm/exynos4210.c-82- 0x00010000 * (n))
##############################################
qemu-5.1+dfsg/hw/arm/exynos4210.c-431- sysbus_realize_and_unref(busdev, &error_fatal);
qemu-5.1+dfsg/hw/arm/exynos4210.c:432: sysbus_mmio_map(busdev, 0, EXYNOS4210_SDHCI_ADDR(n));
qemu-5.1+dfsg/hw/arm/exynos4210.c-433- sysbus_connect_irq(busdev, 0, s->irq_table[exynos4210_get_irq(29, n)]);
##############################################
qemu-5.1+dfsg/hw/arm/highbank.c-44-#define MVBAR_ADDR 0x200
qemu-5.1+dfsg/hw/arm/highbank.c:45:#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
qemu-5.1+dfsg/hw/arm/highbank.c-46-
##############################################
qemu-5.1+dfsg/hw/arm/kzm.c-57-
qemu-5.1+dfsg/hw/arm/kzm.c:58:#define KZM_RAM_ADDR (FSL_IMX31_SDRAM0_ADDR)
qemu-5.1+dfsg/hw/arm/kzm.c:59:#define KZM_FPGA_ADDR (FSL_IMX31_CS4_ADDR + 0x1040)
qemu-5.1+dfsg/hw/arm/kzm.c:60:#define KZM_LAN9118_ADDR (FSL_IMX31_CS5_ADDR)
qemu-5.1+dfsg/hw/arm/kzm.c-61-
##############################################
qemu-5.1+dfsg/hw/arm/omap1.c-3824-/* DMA ports for OMAP1 */
qemu-5.1+dfsg/hw/arm/omap1.c:3825:static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
qemu-5.1+dfsg/hw/arm/omap1.c-3826- hwaddr addr)
##############################################
qemu-5.1+dfsg/hw/arm/omap1.c-3830-
qemu-5.1+dfsg/hw/arm/omap1.c:3831:static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
qemu-5.1+dfsg/hw/arm/omap1.c-3832- hwaddr addr)
##############################################
qemu-5.1+dfsg/hw/arm/omap1.c-3837-
qemu-5.1+dfsg/hw/arm/omap1.c:3838:static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
qemu-5.1+dfsg/hw/arm/omap1.c-3839- hwaddr addr)
##############################################
qemu-5.1+dfsg/hw/arm/omap1.c-3843-
qemu-5.1+dfsg/hw/arm/omap1.c:3844:static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
qemu-5.1+dfsg/hw/arm/omap1.c-3845- hwaddr addr)
##############################################
qemu-5.1+dfsg/hw/arm/omap1.c-3849-
qemu-5.1+dfsg/hw/arm/omap1.c:3850:static int omap_validate_local_addr(struct omap_mpu_state_s *s,
qemu-5.1+dfsg/hw/arm/omap1.c-3851- hwaddr addr)
##############################################
qemu-5.1+dfsg/hw/arm/omap1.c-3855-
qemu-5.1+dfsg/hw/arm/omap1.c:3856:static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
qemu-5.1+dfsg/hw/arm/omap1.c-3857- hwaddr addr)
##############################################
qemu-5.1+dfsg/hw/arm/omap2.c-2266-
qemu-5.1+dfsg/hw/arm/omap2.c:2267:static int omap2_validate_addr(struct omap_mpu_state_s *s,
qemu-5.1+dfsg/hw/arm/omap2.c-2268- hwaddr addr)
##############################################
qemu-5.1+dfsg/hw/arm/raspi.c-29-#define MVBAR_ADDR 0x400 /* secure vectors */
qemu-5.1+dfsg/hw/arm/raspi.c:30:#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
qemu-5.1+dfsg/hw/arm/raspi.c-31-#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
##############################################
qemu-5.1+dfsg/hw/arm/smmuv3.c-162- EVT_SET_SSV(&evt, info->u.f_uut.ssv);
qemu-5.1+dfsg/hw/arm/smmuv3.c:163: EVT_SET_ADDR(&evt, info->u.f_uut.addr);
qemu-5.1+dfsg/hw/arm/smmuv3.c-164- EVT_SET_RNW(&evt, info->u.f_uut.rnw);
##############################################
qemu-5.1+dfsg/hw/arm/smmuv3.c-183- case SMMU_EVT_F_TRANS_FORBIDDEN:
qemu-5.1+dfsg/hw/arm/smmuv3.c:184: EVT_SET_ADDR(&evt, info->u.f_transl_forbidden.addr);
qemu-5.1+dfsg/hw/arm/smmuv3.c-185- EVT_SET_RNW(&evt, info->u.f_transl_forbidden.rnw);
##############################################
qemu-5.1+dfsg/hw/arm/smmuv3.c-192- EVT_SET_SSV(&evt, info->u.f_cd_fetch.ssv);
qemu-5.1+dfsg/hw/arm/smmuv3.c:193: EVT_SET_ADDR(&evt, info->u.f_cd_fetch.addr);
qemu-5.1+dfsg/hw/arm/smmuv3.c-194- break;
##############################################
qemu-5.1+dfsg/hw/arm/smmuv3.c-208- EVT_SET_S2(&evt, info->u.f_walk_eabt.s2);
qemu-5.1+dfsg/hw/arm/smmuv3.c:209: EVT_SET_ADDR(&evt, info->u.f_walk_eabt.addr);
qemu-5.1+dfsg/hw/arm/smmuv3.c-210- EVT_SET_RNW(&evt, info->u.f_walk_eabt.rnw);
##############################################
qemu-5.1+dfsg/hw/arm/smmuv3.c-991- {
qemu-5.1+dfsg/hw/arm/smmuv3.c:992: dma_addr_t addr = CMD_ADDR(&cmd);
qemu-5.1+dfsg/hw/arm/smmuv3.c-993- uint16_t vmid = CMD_VMID(&cmd);
##############################################
qemu-5.1+dfsg/hw/arm/smmuv3.c-1003- uint16_t vmid = CMD_VMID(&cmd);
qemu-5.1+dfsg/hw/arm/smmuv3.c:1004: dma_addr_t addr = CMD_ADDR(&cmd);
qemu-5.1+dfsg/hw/arm/smmuv3.c-1005- bool leaf = CMD_LEAF(&cmd);
##############################################
qemu-5.1+dfsg/hw/arm/smmuv3-internal.h-313-#define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5)
qemu-5.1+dfsg/hw/arm/smmuv3-internal.h:314:#define CMD_ADDR(x) ({ \
qemu-5.1+dfsg/hw/arm/smmuv3-internal.h-315- uint64_t high = (uint64_t)(x)->word[3]; \
##############################################
qemu-5.1+dfsg/hw/arm/smmuv3-internal.h-456-#define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v))
qemu-5.1+dfsg/hw/arm/smmuv3-internal.h:457:#define EVT_SET_ADDR(x, addr) \
qemu-5.1+dfsg/hw/arm/smmuv3-internal.h-458- do { \
##############################################
qemu-5.1+dfsg/hw/arm/spitz.c-772-
qemu-5.1+dfsg/hw/arm/spitz.c:773:static void spitz_wm8750_addr(void *opaque, int line, int level)
qemu-5.1+dfsg/hw/arm/spitz.c-774-{
##############################################
qemu-5.1+dfsg/hw/arm/spitz.c-791-
qemu-5.1+dfsg/hw/arm/spitz.c:792: spitz_wm8750_addr(wm, 0, 0);
qemu-5.1+dfsg/hw/arm/spitz.c-793- qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_WM,
##############################################
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-225-
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c:226: mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-227- nodename = g_strdup_printf("%s/%s@%" PRIx64, parent_node,
##############################################
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-238- for (i = 0; i < vbasedev->num_regions; i++) {
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c:239: mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, i);
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-240- reg_attr[2 * i] = cpu_to_be32(mmio_base);
##############################################
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-359- /* combined XGBE/PHY node */
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c:360: mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-361- nodename = g_strdup_printf("%s/%s@%" PRIx64, parent_node,
##############################################
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-375- for (i = 0; i < vbasedev->num_regions; i++) {
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c:376: mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, i);
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-377- reg_attr[2 * i] = cpu_to_be32(mmio_base);
##############################################
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-456-
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c:457: mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
qemu-5.1+dfsg/hw/arm/sysbus-fdt.c-458- nodename = g_strdup_printf("%s/tpm_tis@%" PRIx64, parent_node, mmio_base);
##############################################
qemu-5.1+dfsg/hw/arm/virt-acpi-build.c-379-
qemu-5.1+dfsg/hw/arm/virt-acpi-build.c:380: tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
qemu-5.1+dfsg/hw/arm/virt-acpi-build.c-381- assert(tpm_base != -1);
##############################################
qemu-5.1+dfsg/hw/audio/intel-hda.c-225-
qemu-5.1+dfsg/hw/audio/intel-hda.c:226:static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
qemu-5.1+dfsg/hw/audio/intel-hda.c-227-{
##############################################
qemu-5.1+dfsg/hw/audio/intel-hda.c-335- rp = (d->corb_rp + 1) & 0xff;
qemu-5.1+dfsg/hw/audio/intel-hda.c:336: addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
qemu-5.1+dfsg/hw/audio/intel-hda.c-337- verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
##############################################
qemu-5.1+dfsg/hw/audio/intel-hda.c-367- wp = (d->rirb_wp + 1) & 0xff;
qemu-5.1+dfsg/hw/audio/intel-hda.c:368: addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
qemu-5.1+dfsg/hw/audio/intel-hda.c-369- stl_le_pci_dma(&d->pci, addr + 8*wp, response);
##############################################
qemu-5.1+dfsg/hw/audio/intel-hda.c-450- s = st - d->st;
qemu-5.1+dfsg/hw/audio/intel-hda.c:451: addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
qemu-5.1+dfsg/hw/audio/intel-hda.c-452- stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
##############################################
qemu-5.1+dfsg/hw/audio/intel-hda.c-468-
qemu-5.1+dfsg/hw/audio/intel-hda.c:469: addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
qemu-5.1+dfsg/hw/audio/intel-hda.c-470- st->bentries = st->lvi +1;
##############################################
qemu-5.1+dfsg/hw/audio/intel-hda.c-908-
qemu-5.1+dfsg/hw/audio/intel-hda.c:909:static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
qemu-5.1+dfsg/hw/audio/intel-hda.c-910-{
##############################################
qemu-5.1+dfsg/hw/audio/intel-hda.c-954-
qemu-5.1+dfsg/hw/audio/intel-hda.c:955: addr = intel_hda_reg_addr(d, reg);
qemu-5.1+dfsg/hw/audio/intel-hda.c-956- old = *addr;
##############################################
qemu-5.1+dfsg/hw/audio/intel-hda.c-988- } else {
qemu-5.1+dfsg/hw/audio/intel-hda.c:989: addr = intel_hda_reg_addr(d, reg);
qemu-5.1+dfsg/hw/audio/intel-hda.c-990- ret = *addr;
##############################################
qemu-5.1+dfsg/hw/audio/intel-hda.c-1031- }
qemu-5.1+dfsg/hw/audio/intel-hda.c:1032: addr = intel_hda_reg_addr(d, regtab + i);
qemu-5.1+dfsg/hw/audio/intel-hda.c-1033- *addr = regtab[i].reset;
##############################################
qemu-5.1+dfsg/hw/block/nvme.c-570- if (unlikely(!prp1 || prp1 & (n->page_size - 1))) {
qemu-5.1+dfsg/hw/block/nvme.c:571: trace_pci_nvme_err_invalid_create_sq_addr(prp1);
qemu-5.1+dfsg/hw/block/nvme.c-572- return NVME_INVALID_FIELD | NVME_DNR;
##############################################
qemu-5.1+dfsg/hw/block/nvme.c-658- if (unlikely(!prp1)) {
qemu-5.1+dfsg/hw/block/nvme.c:659: trace_pci_nvme_err_invalid_create_cq_addr(prp1);
qemu-5.1+dfsg/hw/block/nvme.c-660- return NVME_INVALID_FIELD | NVME_DNR;
##############################################
qemu-5.1+dfsg/hw/block/nvme.c-1148- n->bar.asq = data;
qemu-5.1+dfsg/hw/block/nvme.c:1149: trace_pci_nvme_mmio_asqaddr(data);
qemu-5.1+dfsg/hw/block/nvme.c-1150- break;
##############################################
qemu-5.1+dfsg/hw/block/nvme.c-1155- case 0x30: /* ACQ */
qemu-5.1+dfsg/hw/block/nvme.c:1156: trace_pci_nvme_mmio_acqaddr(data);
qemu-5.1+dfsg/hw/block/nvme.c-1157- n->bar.acq = data;
##############################################
qemu-5.1+dfsg/hw/block/onenand.c-408- void *buf;
qemu-5.1+dfsg/hw/block/onenand.c:409:#define SETADDR(block, page) \
qemu-5.1+dfsg/hw/block/onenand.c-410- sec = (s->addr[page] & 3) + \
##############################################
qemu-5.1+dfsg/hw/block/onenand.c-425- case 0x00: /* Load single/multiple sector data unit into buffer */
qemu-5.1+dfsg/hw/block/onenand.c:426: SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
qemu-5.1+dfsg/hw/block/onenand.c-427-
##############################################
qemu-5.1+dfsg/hw/block/onenand.c-444- case 0x13: /* Load single/multiple spare sector into buffer */
qemu-5.1+dfsg/hw/block/onenand.c:445: SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
qemu-5.1+dfsg/hw/block/onenand.c-446-
##############################################
qemu-5.1+dfsg/hw/block/onenand.c-457- case 0x80: /* Program single/multiple sector data unit from buffer */
qemu-5.1+dfsg/hw/block/onenand.c:458: SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
qemu-5.1+dfsg/hw/block/onenand.c-459-
##############################################
qemu-5.1+dfsg/hw/block/onenand.c-476- case 0x1a: /* Program single/multiple spare area sector from buffer */
qemu-5.1+dfsg/hw/block/onenand.c:477: SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
qemu-5.1+dfsg/hw/block/onenand.c-478-
##############################################
qemu-5.1+dfsg/hw/block/onenand.c-491-
qemu-5.1+dfsg/hw/block/onenand.c:492: SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
qemu-5.1+dfsg/hw/block/onenand.c-493- if (onenand_load_main(s, sec, s->count, buf))
##############################################
qemu-5.1+dfsg/hw/block/onenand.c-495-
qemu-5.1+dfsg/hw/block/onenand.c:496: SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE)
qemu-5.1+dfsg/hw/block/onenand.c-497- if (onenand_prog_main(s, sec, s->count, buf))
##############################################
qemu-5.1+dfsg/hw/block/onenand.c-686- if (value == 0x0000) {
qemu-5.1+dfsg/hw/block/onenand.c:687: SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
qemu-5.1+dfsg/hw/block/onenand.c-688- onenand_load_main(s, sec,
##############################################
qemu-5.1+dfsg/hw/block/trace-events-52-pci_nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=0x%"PRIx64""
qemu-5.1+dfsg/hw/block/trace-events:53:pci_nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue address=0x%"PRIx64""
qemu-5.1+dfsg/hw/block/trace-events:54:pci_nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue address=0x%"PRIx64""
qemu-5.1+dfsg/hw/block/trace-events-55-pci_nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin submission queue high half=0x%"PRIx64", new_address=0x%"PRIx64""
##############################################
qemu-5.1+dfsg/hw/block/trace-events-75-pci_nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submission queue, invalid qsize=%"PRIu16""
qemu-5.1+dfsg/hw/block/trace-events:76:pci_nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submission queue, addr=0x%"PRIx64""
qemu-5.1+dfsg/hw/block/trace-events-77-pci_nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating submission queue, qflags=%"PRIu16""
##############################################
qemu-5.1+dfsg/hw/block/trace-events-81-pci_nvme_err_invalid_create_cq_size(uint16_t size) "failed creating completion queue, size=%"PRIu16""
qemu-5.1+dfsg/hw/block/trace-events:82:pci_nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating completion queue, addr=0x%"PRIx64""
qemu-5.1+dfsg/hw/block/trace-events-83-pci_nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating completion queue, vector=%"PRIu16""
##############################################
qemu-5.1+dfsg/hw/block/vhost-user-blk.c-281-
qemu-5.1+dfsg/hw/block/vhost-user-blk.c:282: if (!virtio_queue_get_desc_addr(vdev, i)) {
qemu-5.1+dfsg/hw/block/vhost-user-blk.c-283- continue;
##############################################
qemu-5.1+dfsg/hw/char/sh_serial.c-409- 0, 0x28);
qemu-5.1+dfsg/hw/char/sh_serial.c:410: memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
qemu-5.1+dfsg/hw/char/sh_serial.c-411-
##############################################
qemu-5.1+dfsg/hw/char/sh_serial.c-413- 0, 0x28);
qemu-5.1+dfsg/hw/char/sh_serial.c:414: memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
qemu-5.1+dfsg/hw/char/sh_serial.c-415-
##############################################
qemu-5.1+dfsg/hw/core/loader.c-213- (N_MAGIC(x) == QMAGIC ? 0 : sizeof (struct exec)))
qemu-5.1+dfsg/hw/core/loader.c:214:#define N_TXTADDR(x, target_page_size) (N_MAGIC(x) == QMAGIC ? target_page_size : 0)
qemu-5.1+dfsg/hw/core/loader.c-215-#define _N_SEGMENT_ROUND(x, target_page_size) (((x) + target_page_size - 1) & ~(target_page_size - 1))
qemu-5.1+dfsg/hw/core/loader.c-216-
qemu-5.1+dfsg/hw/core/loader.c:217:#define _N_TXTENDADDR(x, target_page_size) (N_TXTADDR(x, target_page_size)+(x).a_text)
qemu-5.1+dfsg/hw/core/loader.c-218-
qemu-5.1+dfsg/hw/core/loader.c:219:#define N_DATADDR(x, target_page_size) \
qemu-5.1+dfsg/hw/core/loader.c:220: (N_MAGIC(x)==OMAGIC? (_N_TXTENDADDR(x, target_page_size)) \
qemu-5.1+dfsg/hw/core/loader.c:221: : (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size), target_page_size)))
qemu-5.1+dfsg/hw/core/loader.c-222-
##############################################
qemu-5.1+dfsg/hw/core/loader.c-256- case NMAGIC:
qemu-5.1+dfsg/hw/core/loader.c:257: if (N_DATADDR(e, target_page_size) + e.a_data > max_sz)
qemu-5.1+dfsg/hw/core/loader.c-258- goto fail;
##############################################
qemu-5.1+dfsg/hw/core/loader.c-262- goto fail;
qemu-5.1+dfsg/hw/core/loader.c:263: ret = read_targphys(filename, fd, addr + N_DATADDR(e, target_page_size),
qemu-5.1+dfsg/hw/core/loader.c-264- e.a_data);
##############################################
qemu-5.1+dfsg/hw/core/loader-fit.c-93-
qemu-5.1+dfsg/hw/core/loader-fit.c:94:static int fit_image_addr(const void *itb, int img, const char *name,
qemu-5.1+dfsg/hw/core/loader-fit.c-95- hwaddr *addr, Error **errp)
##############################################
qemu-5.1+dfsg/hw/core/loader-fit.c-142-
qemu-5.1+dfsg/hw/core/loader-fit.c:143: err = fit_image_addr(itb, img_off, "load", &load_addr, errp);
qemu-5.1+dfsg/hw/core/loader-fit.c-144- if (err) {
##############################################
qemu-5.1+dfsg/hw/core/loader-fit.c-149-
qemu-5.1+dfsg/hw/core/loader-fit.c:150: err = fit_image_addr(itb, img_off, "entry", &entry_addr, errp);
qemu-5.1+dfsg/hw/core/loader-fit.c-151- if (err) {
##############################################
qemu-5.1+dfsg/hw/core/loader-fit.c-200-
qemu-5.1+dfsg/hw/core/loader-fit.c:201: ret = fit_image_addr(itb, img_off, "load", &load_addr, &err);
qemu-5.1+dfsg/hw/core/loader-fit.c-202- if (ret == -ENOENT) {
##############################################
qemu-5.1+dfsg/hw/core/platform-bus.c-53- */
qemu-5.1+dfsg/hw/core/platform-bus.c:54:hwaddr platform_bus_get_mmio_addr(PlatformBusDevice *pbus, SysBusDevice *sbdev,
qemu-5.1+dfsg/hw/core/platform-bus.c-55- int n)
##############################################
qemu-5.1+dfsg/hw/core/qdev-properties.c-911-
qemu-5.1+dfsg/hw/core/qdev-properties.c:912:static void get_pci_host_devaddr(Object *obj, Visitor *v, const char *name,
qemu-5.1+dfsg/hw/core/qdev-properties.c-913- void *opaque, Error **errp)
##############################################
qemu-5.1+dfsg/hw/core/qdev-properties.c-938- */
qemu-5.1+dfsg/hw/core/qdev-properties.c:939:static void set_pci_host_devaddr(Object *obj, Visitor *v, const char *name,
qemu-5.1+dfsg/hw/core/qdev-properties.c-940- void *opaque, Error **errp)
##############################################
qemu-5.1+dfsg/hw/core/qdev-properties.c-1270-
qemu-5.1+dfsg/hw/core/qdev-properties.c:1271:void qdev_prop_set_macaddr(DeviceState *dev, const char *name,
qemu-5.1+dfsg/hw/core/qdev-properties.c-1272- const uint8_t *value)
##############################################
qemu-5.1+dfsg/hw/core/qdev-properties-system.c-457-{
qemu-5.1+dfsg/hw/core/qdev-properties-system.c:458: qdev_prop_set_macaddr(dev, "mac", nd->macaddr.a);
qemu-5.1+dfsg/hw/core/qdev-properties-system.c-459- if (nd->netdev) {
##############################################
qemu-5.1+dfsg/hw/display/pxa2xx_lcd.c-165-#define FBR_BINT (1 << 1)
qemu-5.1+dfsg/hw/display/pxa2xx_lcd.c:166:#define FBR_SRCADDR (0xfffffff << 4)
qemu-5.1+dfsg/hw/display/pxa2xx_lcd.c-167-#define LCSR0_LDD (1 << 0)
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-280-#define SM501_DC_PANEL_COLOR_KEY (0x008)
qemu-5.1+dfsg/hw/display/sm501.c:281:#define SM501_DC_PANEL_FB_ADDR (0x00C)
qemu-5.1+dfsg/hw/display/sm501.c-282-#define SM501_DC_PANEL_FB_OFFSET (0x010)
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-293-#define SM501_DC_VIDEO_CONTROL (0x040)
qemu-5.1+dfsg/hw/display/sm501.c:294:#define SM501_DC_VIDEO_FB0_ADDR (0x044)
qemu-5.1+dfsg/hw/display/sm501.c-295-#define SM501_DC_VIDEO_FB_WIDTH (0x048)
qemu-5.1+dfsg/hw/display/sm501.c:296:#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
qemu-5.1+dfsg/hw/display/sm501.c-297-#define SM501_DC_VIDEO_TL_LOC (0x050)
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-301-#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
qemu-5.1+dfsg/hw/display/sm501.c:302:#define SM501_DC_VIDEO_FB1_ADDR (0x064)
qemu-5.1+dfsg/hw/display/sm501.c:303:#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
qemu-5.1+dfsg/hw/display/sm501.c-304-
qemu-5.1+dfsg/hw/display/sm501.c-305-#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
qemu-5.1+dfsg/hw/display/sm501.c:306:#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
qemu-5.1+dfsg/hw/display/sm501.c-307-#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
qemu-5.1+dfsg/hw/display/sm501.c:308:#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
qemu-5.1+dfsg/hw/display/sm501.c-309-#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-316-#define SM501_DC_PANEL_HWC_BASE (0x0F0)
qemu-5.1+dfsg/hw/display/sm501.c:317:#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
qemu-5.1+dfsg/hw/display/sm501.c-318-#define SM501_DC_PANEL_HWC_LOC (0x0F4)
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-323-
qemu-5.1+dfsg/hw/display/sm501.c:324:#define SM501_OFF_HWC_ADDR (0x00)
qemu-5.1+dfsg/hw/display/sm501.c-325-#define SM501_OFF_HWC_LOC (0x04)
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-329-#define SM501_DC_ALPHA_CONTROL (0x100)
qemu-5.1+dfsg/hw/display/sm501.c:330:#define SM501_DC_ALPHA_FB_ADDR (0x104)
qemu-5.1+dfsg/hw/display/sm501.c-331-#define SM501_DC_ALPHA_FB_OFFSET (0x108)
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-354-
qemu-5.1+dfsg/hw/display/sm501.c:355:#define SM501_DC_CRT_FB_ADDR (0x204)
qemu-5.1+dfsg/hw/display/sm501.c-356-#define SM501_DC_CRT_FB_OFFSET (0x208)
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-365-#define SM501_DC_CRT_HWC_BASE (0x230)
qemu-5.1+dfsg/hw/display/sm501.c:366:#define SM501_DC_CRT_HWC_ADDR (0x230)
qemu-5.1+dfsg/hw/display/sm501.c-367-#define SM501_DC_CRT_HWC_LOC (0x234)
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-563-
qemu-5.1+dfsg/hw/display/sm501.c:564:static ram_addr_t get_fb_addr(SM501State *s, int crt)
qemu-5.1+dfsg/hw/display/sm501.c-565-{
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-671- memory_region_set_dirty(&s->local_mem_region,
qemu-5.1+dfsg/hw/display/sm501.c:672: get_fb_addr(s, crt) + start, end - start);
qemu-5.1+dfsg/hw/display/sm501.c-673-}
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-856-
qemu-5.1+dfsg/hw/display/sm501.c:857: if (dst_base >= get_fb_addr(s, crt) &&
qemu-5.1+dfsg/hw/display/sm501.c:858: dst_base <= get_fb_addr(s, crt) + fb_len) {
qemu-5.1+dfsg/hw/display/sm501.c-859- int dst_len = MIN(fb_len, ((dst_y + height - 1) * dst_pitch +
##############################################
qemu-5.1+dfsg/hw/display/sm501.c-1715- /* draw each line according to conditions */
qemu-5.1+dfsg/hw/display/sm501.c:1716: offset = get_fb_addr(s, crt);
qemu-5.1+dfsg/hw/display/sm501.c-1717- snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region,
##############################################
qemu-5.1+dfsg/hw/display/vmware_vga.c-866- = container_of(s, struct pci_vmsvga_state_s, chip);
qemu-5.1+dfsg/hw/display/vmware_vga.c:867: ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1);
qemu-5.1+dfsg/hw/display/vmware_vga.c-868- break;
##############################################
qemu-5.1+dfsg/hw/display/vmware_vga.c-902- = container_of(s, struct pci_vmsvga_state_s, chip);
qemu-5.1+dfsg/hw/display/vmware_vga.c:903: ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2);
qemu-5.1+dfsg/hw/display/vmware_vga.c-904- break;
##############################################
qemu-5.1+dfsg/hw/dma/pxa2xx_dma.c-97-#define DCMD_FLOWSRC (1 << 29)
qemu-5.1+dfsg/hw/dma/pxa2xx_dma.c:98:#define DCMD_INCTRGADDR (1 << 30)
qemu-5.1+dfsg/hw/dma/pxa2xx_dma.c:99:#define DCMD_INCSRCADDR (1 << 31)
qemu-5.1+dfsg/hw/dma/pxa2xx_dma.c-100-#define DCSR_BUSERRINTR (1 << 0)
##############################################
qemu-5.1+dfsg/hw/dma/xilinx_axidma.c-181-/* Map an offset addr into a channel index. */
qemu-5.1+dfsg/hw/dma/xilinx_axidma.c:182:static inline int streamid_from_addr(hwaddr addr)
qemu-5.1+dfsg/hw/dma/xilinx_axidma.c-183-{
##############################################
qemu-5.1+dfsg/hw/dma/xilinx_axidma.c-442-
qemu-5.1+dfsg/hw/dma/xilinx_axidma.c:443: sid = streamid_from_addr(addr);
qemu-5.1+dfsg/hw/dma/xilinx_axidma.c-444- s = &d->streams[sid];
##############################################
qemu-5.1+dfsg/hw/dma/xilinx_axidma.c-476-
qemu-5.1+dfsg/hw/dma/xilinx_axidma.c:477: sid = streamid_from_addr(addr);
qemu-5.1+dfsg/hw/dma/xilinx_axidma.c-478- s = &d->streams[sid];
##############################################
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c-345-
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c:346:static void zdma_update_descr_addr(XlnxZDMA *s, bool type,
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c-347- unsigned int basereg)
##############################################
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c-381- dst_type = FIELD_EX32(s->dsc_dst.words[3], ZDMA_CH_DST_DSCR_WORD3, TYPE);
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c:382: zdma_update_descr_addr(s, dst_type, R_ZDMA_CH_DST_CUR_DSCR_LSB);
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c-383-}
##############################################
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c-532-
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c:533: zdma_update_descr_addr(s, src_type, R_ZDMA_CH_SRC_CUR_DSCR_LSB);
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c-534-}
##############################################
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c-575- ZDMA_CH_SRC_DSCR_WORD3, TYPE);
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c:576: zdma_update_descr_addr(s, src_type,
qemu-5.1+dfsg/hw/dma/xlnx-zdma.c-577- R_ZDMA_CH_SRC_CUR_DSCR_LSB);
##############################################
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c-72-#define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c:73:#define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) /* Removed */
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c:74:#define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c:75:#define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c:76:#define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c-77-#define I2CD_INTR_SLAVE_ADDR_RX_MATCH (0x1 << 7) /* use RX_DONE */
##############################################
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c-359-
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c:360:static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus)
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c-361-{
##############################################
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c-453-
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c:454: addr = aspeed_i2c_get_addr(bus);
qemu-5.1+dfsg/hw/i2c/aspeed_i2c.c-455-
##############################################
qemu-5.1+dfsg/hw/i386/amd_iommu.c-998-
qemu-5.1+dfsg/hw/i386/amd_iommu.c:999:static inline bool amdvi_is_interrupt_addr(hwaddr addr)
qemu-5.1+dfsg/hw/i386/amd_iommu.c-1000-{
##############################################
qemu-5.1+dfsg/hw/i386/amd_iommu.c-1025- return ret;
qemu-5.1+dfsg/hw/i386/amd_iommu.c:1026: } else if (amdvi_is_interrupt_addr(addr)) {
qemu-5.1+dfsg/hw/i386/amd_iommu.c-1027- ret.iova = addr & AMDVI_PAGE_MASK_4K;
##############################################
qemu-5.1+dfsg/hw/i386/amd_iommu.h-195-
qemu-5.1+dfsg/hw/i386/amd_iommu.h:196:#define AMDVI_MAX_VA_ADDR (48UL << 5)
qemu-5.1+dfsg/hw/i386/amd_iommu.h:197:#define AMDVI_MAX_PH_ADDR (40UL << 8)
qemu-5.1+dfsg/hw/i386/amd_iommu.h:198:#define AMDVI_MAX_GVA_ADDR (48UL << 15)
qemu-5.1+dfsg/hw/i386/amd_iommu.h-199-
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-623-
qemu-5.1+dfsg/hw/i386/intel_iommu.c:624:static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw)
qemu-5.1+dfsg/hw/i386/intel_iommu.c-625-{
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1070- }
qemu-5.1+dfsg/hw/i386/intel_iommu.c:1071: addr = vtd_get_slpte_addr(slpte, aw_bits);
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1072- level--;
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1235- */
qemu-5.1+dfsg/hw/i386/intel_iommu.c:1236: ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw),
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1237- iova, MIN(iova_next, end), level - 1,
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1252- /* NOTE: this is only meaningful if entry_valid == true */
qemu-5.1+dfsg/hw/i386/intel_iommu.c:1253: entry.translated_addr = vtd_get_slpte_addr(slpte, info->aw);
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1254- ret = vtd_page_walk_one(&entry, info);
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1632-
qemu-5.1+dfsg/hw/i386/intel_iommu.c:1633:static inline bool vtd_is_interrupt_addr(hwaddr addr)
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1634-{
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1696- */
qemu-5.1+dfsg/hw/i386/intel_iommu.c:1697: assert(!vtd_is_interrupt_addr(addr));
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1698-
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1775- entry->iova = addr & page_mask;
qemu-5.1+dfsg/hw/i386/intel_iommu.c:1776: entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask;
qemu-5.1+dfsg/hw/i386/intel_iommu.c-1777- entry->addr_mask = ~page_mask;
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-2053- am = VTD_IVA_AM(addr);
qemu-5.1+dfsg/hw/i386/intel_iommu.c:2054: addr = VTD_IVA_ADDR(addr);
qemu-5.1+dfsg/hw/i386/intel_iommu.c-2055- if (am > VTD_MAMV) {
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-2375- domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
qemu-5.1+dfsg/hw/i386/intel_iommu.c:2376: addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
qemu-5.1+dfsg/hw/i386/intel_iommu.c-2377- am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu.c-2423-
qemu-5.1+dfsg/hw/i386/intel_iommu.c:2424: addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
qemu-5.1+dfsg/hw/i386/intel_iommu.c-2425- sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu_internal.h-133-/* IVA_REG */
qemu-5.1+dfsg/hw/i386/intel_iommu_internal.h:134:#define VTD_IVA_ADDR(val) ((val) & ~0xfffULL)
qemu-5.1+dfsg/hw/i386/intel_iommu_internal.h-135-#define VTD_IVA_AM(val) ((val) & 0x3fULL)
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu_internal.h-377-#define VTD_INV_DESC_IOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
qemu-5.1+dfsg/hw/i386/intel_iommu_internal.h:378:#define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL)
qemu-5.1+dfsg/hw/i386/intel_iommu_internal.h-379-#define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL)
##############################################
qemu-5.1+dfsg/hw/i386/intel_iommu_internal.h-383-/* Mask for Device IOTLB Invalidate Descriptor */
qemu-5.1+dfsg/hw/i386/intel_iommu_internal.h:384:#define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL)
qemu-5.1+dfsg/hw/i386/intel_iommu_internal.h-385-#define VTD_INV_DESC_DEVICE_IOTLB_SIZE(val) ((val) & 0x1)
##############################################
qemu-5.1+dfsg/hw/i386/kvmvapic.c-156-
qemu-5.1+dfsg/hw/i386/kvmvapic.c:157:static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env)
qemu-5.1+dfsg/hw/i386/kvmvapic.c-158-{
##############################################
qemu-5.1+dfsg/hw/i386/kvmvapic.c-699- }
qemu-5.1+dfsg/hw/i386/kvmvapic.c:700: if (find_real_tpr_addr(s, env) < 0) {
qemu-5.1+dfsg/hw/i386/kvmvapic.c-701- break;
##############################################
qemu-5.1+dfsg/hw/i386/x86.c-387- */
qemu-5.1+dfsg/hw/i386/x86.c:388:static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
qemu-5.1+dfsg/hw/i386/x86.c-389-{
##############################################
qemu-5.1+dfsg/hw/i386/xen/xen-hvm.c-311-
qemu-5.1+dfsg/hw/i386/xen/xen-hvm.c:312:static hwaddr xen_phys_offset_to_gaddr(hwaddr phys_offset, ram_addr_t size)
qemu-5.1+dfsg/hw/i386/xen/xen-hvm.c-313-{
##############################################
qemu-5.1+dfsg/hw/i386/xen/xen-hvm.c-372- hwaddr pfn, start_gpfn;
qemu-5.1+dfsg/hw/i386/xen/xen-hvm.c:373: hwaddr phys_offset = memory_region_get_ram_addr(mr);
qemu-5.1+dfsg/hw/i386/xen/xen-hvm.c-374- const char *mr_name;
##############################################
qemu-5.1+dfsg/hw/i386/xen/xen-hvm.c-1590-
qemu-5.1+dfsg/hw/i386/xen/xen-hvm.c:1591: start = xen_phys_offset_to_gaddr(start, length);
qemu-5.1+dfsg/hw/i386/xen/xen-hvm.c-1592-
##############################################
qemu-5.1+dfsg/hw/i386/xen/xen-mapcache.c-326- if (!translated && mapcache->phys_offset_to_gaddr) {
qemu-5.1+dfsg/hw/i386/xen/xen-mapcache.c:327: phys_addr = mapcache->phys_offset_to_gaddr(phys_addr, size);
qemu-5.1+dfsg/hw/i386/xen/xen-mapcache.c-328- translated = true;
##############################################
qemu-5.1+dfsg/hw/input/adb-kbd.c-258- d->devaddr = buf[1] & 0xf;
qemu-5.1+dfsg/hw/input/adb-kbd.c:259: trace_adb_device_kbd_request_change_addr(d->devaddr);
qemu-5.1+dfsg/hw/input/adb-kbd.c-260- break;
##############################################
qemu-5.1+dfsg/hw/input/adb-mouse.c-154- d->devaddr = buf[1] & 0xf;
qemu-5.1+dfsg/hw/input/adb-mouse.c:155: trace_adb_device_mouse_request_change_addr(d->devaddr);
qemu-5.1+dfsg/hw/input/adb-mouse.c-156- break;
##############################################
qemu-5.1+dfsg/hw/input/trace-events-6-adb_device_kbd_readreg(int reg, uint8_t val0, uint8_t val1) "reg %d obuf[0] 0x%2.2x obuf[1] 0x%2.2x"
qemu-5.1+dfsg/hw/input/trace-events:7:adb_device_kbd_request_change_addr(int devaddr) "change addr to 0x%x"
qemu-5.1+dfsg/hw/input/trace-events-8-adb_device_kbd_request_change_addr_and_handler(int devaddr, int handler) "change addr and handler to 0x%x, 0x%x"
##############################################
qemu-5.1+dfsg/hw/input/trace-events-13-adb_device_mouse_readreg(int reg, uint8_t val0, uint8_t val1) "reg %d obuf[0] 0x%2.2x obuf[1] 0x%2.2x"
qemu-5.1+dfsg/hw/input/trace-events:14:adb_device_mouse_request_change_addr(int devaddr) "change addr to 0x%x"
qemu-5.1+dfsg/hw/input/trace-events-15-adb_device_mouse_request_change_addr_and_handler(int devaddr, int handler) "change addr and handler to 0x%x, 0x%x"
##############################################
qemu-5.1+dfsg/hw/intc/pnv_xive.c-219-
qemu-5.1+dfsg/hw/intc/pnv_xive.c:220:static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk,
qemu-5.1+dfsg/hw/intc/pnv_xive.c-221- uint32_t idx)
##############################################
qemu-5.1+dfsg/hw/intc/pnv_xive.c-237-
qemu-5.1+dfsg/hw/intc/pnv_xive.c:238: return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0;
qemu-5.1+dfsg/hw/intc/pnv_xive.c-239- }
##############################################
qemu-5.1+dfsg/hw/intc/pnv_xive.c-251- const XiveVstInfo *info = &vst_infos[type];
qemu-5.1+dfsg/hw/intc/pnv_xive.c:252: uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx);
qemu-5.1+dfsg/hw/intc/pnv_xive.c-253-
##############################################
qemu-5.1+dfsg/hw/intc/pnv_xive.c-267- const XiveVstInfo *info = &vst_infos[type];
qemu-5.1+dfsg/hw/intc/pnv_xive.c:268: uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx);
qemu-5.1+dfsg/hw/intc/pnv_xive.c-269-
##############################################
qemu-5.1+dfsg/hw/intc/sh_intc.c-323- memory_region_init_alias(iomem_p4, NULL, name, iomem, INTC_A7(address), 4);
qemu-5.1+dfsg/hw/intc/sh_intc.c:324: memory_region_add_subregion(sysmem, P4ADDR(address), iomem_p4);
qemu-5.1+dfsg/hw/intc/sh_intc.c-325-
##############################################
qemu-5.1+dfsg/hw/intc/sh_intc.c-327- memory_region_init_alias(iomem_a7, NULL, name, iomem, INTC_A7(address), 4);
qemu-5.1+dfsg/hw/intc/sh_intc.c:328: memory_region_add_subregion(sysmem, A7ADDR(address), iomem_a7);
qemu-5.1+dfsg/hw/intc/sh_intc.c-329-#undef SH_INTC_IOMEM_FORMAT
##############################################
qemu-5.1+dfsg/hw/intc/spapr_xive.c-135-{
qemu-5.1+dfsg/hw/intc/spapr_xive.c:136: uint64_t qaddr_base = xive_end_qaddr(end);
qemu-5.1+dfsg/hw/intc/spapr_xive.c-137- uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1);
##############################################
qemu-5.1+dfsg/hw/intc/spapr_xive.c-1475- if (xive_end_is_enqueue(end)) {
qemu-5.1+dfsg/hw/intc/spapr_xive.c:1476: args[1] = xive_end_qaddr(end);
qemu-5.1+dfsg/hw/intc/spapr_xive.c-1477- args[2] = xive_get_field32(END_W0_QSIZE, end->w0) + 12;
##############################################
qemu-5.1+dfsg/hw/intc/spapr_xive_kvm.c-445- kvm_eq.qshift = xive_get_field32(END_W0_QSIZE, end->w0) + 12;
qemu-5.1+dfsg/hw/intc/spapr_xive_kvm.c:446: kvm_eq.qaddr = xive_end_qaddr(end);
qemu-5.1+dfsg/hw/intc/spapr_xive_kvm.c-447- /*
##############################################
qemu-5.1+dfsg/hw/intc/xive.c-1210-{
qemu-5.1+dfsg/hw/intc/xive.c:1211: uint64_t qaddr_base = xive_end_qaddr(end);
qemu-5.1+dfsg/hw/intc/xive.c-1212- uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0);
##############################################
qemu-5.1+dfsg/hw/intc/xive.c-1240-{
qemu-5.1+dfsg/hw/intc/xive.c:1241: uint64_t qaddr_base = xive_end_qaddr(end);
qemu-5.1+dfsg/hw/intc/xive.c-1242- uint32_t qindex = xive_get_field32(END_W1_PAGE_OFF, end->w1);
##############################################
qemu-5.1+dfsg/hw/intc/xive.c-1280-{
qemu-5.1+dfsg/hw/intc/xive.c:1281: uint64_t qaddr_base = xive_end_qaddr(end);
qemu-5.1+dfsg/hw/intc/xive.c-1282- uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0);
##############################################
qemu-5.1+dfsg/hw/ipack/tpci200.c-87-
qemu-5.1+dfsg/hw/ipack/tpci200.c:88:static void adjust_addr(bool big_endian, hwaddr *addr, unsigned size)
qemu-5.1+dfsg/hw/ipack/tpci200.c-89-{
##############################################
qemu-5.1+dfsg/hw/ipack/tpci200.c-314-
qemu-5.1+dfsg/hw/ipack/tpci200.c:315: adjust_addr(s->big_endian[1], &addr, size);
qemu-5.1+dfsg/hw/ipack/tpci200.c-316-
##############################################
qemu-5.1+dfsg/hw/ipack/tpci200.c-375-
qemu-5.1+dfsg/hw/ipack/tpci200.c:376: adjust_addr(s->big_endian[1], &addr, size);
qemu-5.1+dfsg/hw/ipack/tpci200.c-377- adjust_value(s->big_endian[1], &val, size);
##############################################
qemu-5.1+dfsg/hw/ipack/tpci200.c-424-
qemu-5.1+dfsg/hw/ipack/tpci200.c:425: adjust_addr(s->big_endian[2], &addr, size);
qemu-5.1+dfsg/hw/ipack/tpci200.c-426-
##############################################
qemu-5.1+dfsg/hw/ipack/tpci200.c-454-
qemu-5.1+dfsg/hw/ipack/tpci200.c:455: adjust_addr(s->big_endian[2], &addr, size);
qemu-5.1+dfsg/hw/ipack/tpci200.c-456- adjust_value(s->big_endian[2], &val, size);
##############################################
qemu-5.1+dfsg/hw/mem/memory-device.c-26- const MemoryDeviceClass *mdc_b = MEMORY_DEVICE_GET_CLASS(b);
qemu-5.1+dfsg/hw/mem/memory-device.c:27: const uint64_t addr_a = mdc_a->get_addr(md_a);
qemu-5.1+dfsg/hw/mem/memory-device.c:28: const uint64_t addr_b = mdc_b->get_addr(md_b);
qemu-5.1+dfsg/hw/mem/memory-device.c-29-
##############################################
qemu-5.1+dfsg/hw/mem/memory-device.c-96-
qemu-5.1+dfsg/hw/mem/memory-device.c:97:static uint64_t memory_device_get_free_addr(MachineState *ms,
qemu-5.1+dfsg/hw/mem/memory-device.c-98- const uint64_t *hint,
##############################################
qemu-5.1+dfsg/hw/mem/memory-device.c-167-
qemu-5.1+dfsg/hw/mem/memory-device.c:168: range_init_nofail(&tmp, mdc->get_addr(md),
qemu-5.1+dfsg/hw/mem/memory-device.c-169- memory_device_get_region_size(md, &error_abort));
##############################################
qemu-5.1+dfsg/hw/mem/memory-device.c-269- align = legacy_align ? *legacy_align : memory_region_get_alignment(mr);
qemu-5.1+dfsg/hw/mem/memory-device.c:270: addr = mdc->get_addr(md);
qemu-5.1+dfsg/hw/mem/memory-device.c:271: addr = memory_device_get_free_addr(ms, !addr ? NULL : &addr, align,
qemu-5.1+dfsg/hw/mem/memory-device.c-272- memory_region_size(mr), &local_err);
##############################################
qemu-5.1+dfsg/hw/mem/memory-device.c-275- }
qemu-5.1+dfsg/hw/mem/memory-device.c:276: mdc->set_addr(md, addr, &local_err);
qemu-5.1+dfsg/hw/mem/memory-device.c-277- if (!local_err) {
##############################################
qemu-5.1+dfsg/hw/mem/memory-device.c-287- const MemoryDeviceClass *mdc = MEMORY_DEVICE_GET_CLASS(md);
qemu-5.1+dfsg/hw/mem/memory-device.c:288: const uint64_t addr = mdc->get_addr(md);
qemu-5.1+dfsg/hw/mem/memory-device.c-289- MemoryRegion *mr;
##############################################
qemu-5.1+dfsg/hw/mem/memory-device.c-316- trace_memory_device_unplug(DEVICE(md)->id ? DEVICE(md)->id : "",
qemu-5.1+dfsg/hw/mem/memory-device.c:317: mdc->get_addr(md));
qemu-5.1+dfsg/hw/mem/memory-device.c-318-}
##############################################
qemu-5.1+dfsg/hw/mem/pc-dimm.c-217-
qemu-5.1+dfsg/hw/mem/pc-dimm.c:218:static uint64_t pc_dimm_md_get_addr(const MemoryDeviceState *md)
qemu-5.1+dfsg/hw/mem/pc-dimm.c-219-{
##############################################
qemu-5.1+dfsg/hw/mem/pc-dimm.c-223-
qemu-5.1+dfsg/hw/mem/pc-dimm.c:224:static void pc_dimm_md_set_addr(MemoryDeviceState *md, uint64_t addr,
qemu-5.1+dfsg/hw/mem/pc-dimm.c-225- Error **errp)
##############################################
qemu-5.1+dfsg/hw/mips/gt64xxx_pci.c-135-#define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
qemu-5.1+dfsg/hw/mips/gt64xxx_pci.c:136:#define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
qemu-5.1+dfsg/hw/mips/gt64xxx_pci.c-137-
##############################################
qemu-5.1+dfsg/hw/mips/gt64xxx_pci.c-208-#define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
qemu-5.1+dfsg/hw/mips/gt64xxx_pci.c:209:#define GT_PCI1_CFGADDR (0xcf0 >> 2)
qemu-5.1+dfsg/hw/mips/gt64xxx_pci.c-210-#define GT_PCI1_CFGDATA (0xcf4 >> 2)
qemu-5.1+dfsg/hw/mips/gt64xxx_pci.c:211:#define GT_PCI0_CFGADDR (0xcf8 >> 2)
qemu-5.1+dfsg/hw/mips/gt64xxx_pci.c-212-#define GT_PCI0_CFGDATA (0xcfc >> 2)
##############################################
qemu-5.1+dfsg/hw/misc/bcm2835_property.c-366- .fields = (VMStateField[]) {
qemu-5.1+dfsg/hw/misc/bcm2835_property.c:367: VMSTATE_MACADDR(macaddr, BCM2835PropertyState),
qemu-5.1+dfsg/hw/misc/bcm2835_property.c-368- VMSTATE_UINT32(addr, BCM2835PropertyState),
##############################################
qemu-5.1+dfsg/hw/misc/edu.c-123-
qemu-5.1+dfsg/hw/misc/edu.c:124:static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr)
qemu-5.1+dfsg/hw/misc/edu.c-125-{
##############################################
qemu-5.1+dfsg/hw/misc/edu.c-147- dst -= DMA_START;
qemu-5.1+dfsg/hw/misc/edu.c:148: pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src),
qemu-5.1+dfsg/hw/misc/edu.c-149- edu->dma_buf + dst, edu->dma.cnt);
##############################################
qemu-5.1+dfsg/hw/misc/edu.c-153- src -= DMA_START;
qemu-5.1+dfsg/hw/misc/edu.c:154: pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst),
qemu-5.1+dfsg/hw/misc/edu.c-155- edu->dma_buf + src, edu->dma.cnt);
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-721- /* Accept packets -w- hash match? */
qemu-5.1+dfsg/hw/net/cadence_gem.c:722: is_mc = is_multicast_ether_addr(packet);
qemu-5.1+dfsg/hw/net/cadence_gem.c-723- if ((is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-867-
qemu-5.1+dfsg/hw/net/cadence_gem.c:868:static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q)
qemu-5.1+dfsg/hw/net/cadence_gem.c-869-{
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-886-
qemu-5.1+dfsg/hw/net/cadence_gem.c:887:static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q)
qemu-5.1+dfsg/hw/net/cadence_gem.c-888-{
qemu-5.1+dfsg/hw/net/cadence_gem.c:889: return gem_get_queue_base_addr(s, true, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-890-}
qemu-5.1+dfsg/hw/net/cadence_gem.c-891-
qemu-5.1+dfsg/hw/net/cadence_gem.c:892:static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q)
qemu-5.1+dfsg/hw/net/cadence_gem.c-893-{
qemu-5.1+dfsg/hw/net/cadence_gem.c:894: return gem_get_queue_base_addr(s, false, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-895-}
qemu-5.1+dfsg/hw/net/cadence_gem.c-896-
qemu-5.1+dfsg/hw/net/cadence_gem.c:897:static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
qemu-5.1+dfsg/hw/net/cadence_gem.c-898-{
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-908-
qemu-5.1+dfsg/hw/net/cadence_gem.c:909:static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q)
qemu-5.1+dfsg/hw/net/cadence_gem.c-910-{
qemu-5.1+dfsg/hw/net/cadence_gem.c:911: return gem_get_desc_addr(s, true, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-912-}
qemu-5.1+dfsg/hw/net/cadence_gem.c-913-
qemu-5.1+dfsg/hw/net/cadence_gem.c:914:static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q)
qemu-5.1+dfsg/hw/net/cadence_gem.c-915-{
qemu-5.1+dfsg/hw/net/cadence_gem.c:916: return gem_get_desc_addr(s, false, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-917-}
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-920-{
qemu-5.1+dfsg/hw/net/cadence_gem.c:921: hwaddr desc_addr = gem_get_rx_desc_addr(s, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-922-
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-1089- /* Descriptor write-back. */
qemu-5.1+dfsg/hw/net/cadence_gem.c:1090: desc_addr = gem_get_rx_desc_addr(s, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-1091- address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-1097- DB_PRINT("wrapping RX descriptor list\n");
qemu-5.1+dfsg/hw/net/cadence_gem.c:1098: s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-1099- } else {
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-1192- /* read current descriptor */
qemu-5.1+dfsg/hw/net/cadence_gem.c:1193: packet_desc_addr = gem_get_tx_desc_addr(s, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-1194-
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-1239- uint32_t desc_first[DESC_MAX_NUM_WORDS];
qemu-5.1+dfsg/hw/net/cadence_gem.c:1240: hwaddr desc_addr = gem_get_tx_desc_addr(s, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-1241-
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-1253- if (tx_desc_get_wrap(desc)) {
qemu-5.1+dfsg/hw/net/cadence_gem.c:1254: s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-1255- } else {
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-1298- }
qemu-5.1+dfsg/hw/net/cadence_gem.c:1299: packet_desc_addr |= gem_get_tx_queue_base_addr(s, q);
qemu-5.1+dfsg/hw/net/cadence_gem.c-1300- } else {
##############################################
qemu-5.1+dfsg/hw/net/cadence_gem.c-1509- for (i = 0; i < s->num_priority_queues; i++) {
qemu-5.1+dfsg/hw/net/cadence_gem.c:1510: s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i);
qemu-5.1+dfsg/hw/net/cadence_gem.c-1511- }
##############################################
qemu-5.1+dfsg/hw/net/e1000.c-388-
qemu-5.1+dfsg/hw/net/e1000.c:389: e1000x_reset_mac_addr(d->nic, d->mac_reg, macaddr);
qemu-5.1+dfsg/hw/net/e1000.c-390-}
##############################################
qemu-5.1+dfsg/hw/net/e1000e.c-142- case E1000_IOADDR:
qemu-5.1+dfsg/hw/net/e1000e.c:143: trace_e1000e_io_read_addr(s->ioaddr);
qemu-5.1+dfsg/hw/net/e1000e.c-144- return s->ioaddr;
##############################################
qemu-5.1+dfsg/hw/net/e1000e.c-166- case E1000_IOADDR:
qemu-5.1+dfsg/hw/net/e1000e.c:167: trace_e1000e_io_write_addr(val);
qemu-5.1+dfsg/hw/net/e1000e.c-168- s->ioaddr = (uint32_t) val;
##############################################
qemu-5.1+dfsg/hw/net/e1000e_core.c-1076-e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc,
qemu-5.1+dfsg/hw/net/e1000e_core.c:1077: hwaddr (*buff_addr)[MAX_PS_BUFFERS])
qemu-5.1+dfsg/hw/net/e1000e_core.c-1078-{
##############################################
qemu-5.1+dfsg/hw/net/e1000e_core.c-1092-e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc,
qemu-5.1+dfsg/hw/net/e1000e_core.c:1093: hwaddr (*buff_addr)[MAX_PS_BUFFERS])
qemu-5.1+dfsg/hw/net/e1000e_core.c-1094-{
##############################################
qemu-5.1+dfsg/hw/net/e1000e_core.c-1379-e1000e_write_hdr_to_rx_buffers(E1000ECore *core,
qemu-5.1+dfsg/hw/net/e1000e_core.c:1380: hwaddr (*ba)[MAX_PS_BUFFERS],
qemu-5.1+dfsg/hw/net/e1000e_core.c-1381- e1000e_ba_state *bastate,
##############################################
qemu-5.1+dfsg/hw/net/e1000e_core.c-1394-e1000e_write_to_rx_buffers(E1000ECore *core,
qemu-5.1+dfsg/hw/net/e1000e_core.c:1395: hwaddr (*ba)[MAX_PS_BUFFERS],
qemu-5.1+dfsg/hw/net/e1000e_core.c-1396- e1000e_ba_state *bastate,
##############################################
qemu-5.1+dfsg/hw/net/e1000e_core.c-1844- trace_e1000e_core_ctrl_sw_reset();
qemu-5.1+dfsg/hw/net/e1000e_core.c:1845: e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
qemu-5.1+dfsg/hw/net/e1000e_core.c-1846- }
##############################################
qemu-5.1+dfsg/hw/net/e1000e_core.c-2725-static void
qemu-5.1+dfsg/hw/net/e1000e_core.c:2726:e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
qemu-5.1+dfsg/hw/net/e1000e_core.c-2727-{
##############################################
qemu-5.1+dfsg/hw/net/e1000e_core.c-3476-
qemu-5.1+dfsg/hw/net/e1000e_core.c:3477: e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
qemu-5.1+dfsg/hw/net/e1000e_core.c-3478-
##############################################
qemu-5.1+dfsg/hw/net/e1000x_common.c-134-
qemu-5.1+dfsg/hw/net/e1000x_common.c:135:void e1000x_reset_mac_addr(NICState *nic, uint32_t *mac_regs,
qemu-5.1+dfsg/hw/net/e1000x_common.c-136- uint8_t *mac_addr)
##############################################
qemu-5.1+dfsg/hw/net/e1000x_common.h-190-
qemu-5.1+dfsg/hw/net/e1000x_common.h:191:void e1000x_reset_mac_addr(NICState *nic, uint32_t *mac_regs,
qemu-5.1+dfsg/hw/net/e1000x_common.h-192- uint8_t *mac_addr);
##############################################
qemu-5.1+dfsg/hw/net/eepro100.c-1774- VMSTATE_UNUSED(3*4),
qemu-5.1+dfsg/hw/net/eepro100.c:1775: VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
qemu-5.1+dfsg/hw/net/eepro100.c-1776- VMSTATE_UNUSED(19*4),
##############################################
qemu-5.1+dfsg/hw/net/etraxfs_eth.c-473- bits (m). The has function is a simple nible xor of the group addr. */
qemu-5.1+dfsg/hw/net/etraxfs_eth.c:474:static int eth_match_groupaddr(ETRAXFSEthState *eth, const unsigned char *sa)
qemu-5.1+dfsg/hw/net/etraxfs_eth.c-475-{
##############################################
qemu-5.1+dfsg/hw/net/etraxfs_eth.c-536- && (!r_bcast || memcmp(buf, sa_bcast, 6))
qemu-5.1+dfsg/hw/net/etraxfs_eth.c:537: && !eth_match_groupaddr(eth, buf)) {
qemu-5.1+dfsg/hw/net/etraxfs_eth.c-538- return size;
##############################################
qemu-5.1+dfsg/hw/net/mcf_fec.c-317-#define MMFR_READ_OP (2 << 28)
qemu-5.1+dfsg/hw/net/mcf_fec.c:318:#define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f)
qemu-5.1+dfsg/hw/net/mcf_fec.c-319-#define MMFR_REGNUM(v) (((v) >> 18) & 0x1f)
##############################################
qemu-5.1+dfsg/hw/net/mcf_fec.c-326- return s->mmfr;
qemu-5.1+dfsg/hw/net/mcf_fec.c:327: if (MMFR_PHYADDR(s->mmfr) != 1)
qemu-5.1+dfsg/hw/net/mcf_fec.c-328- return s->mmfr |= 0xffff;
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-117-
qemu-5.1+dfsg/hw/net/pcnet.c:118:#define PHYSADDR(S,A) \
qemu-5.1+dfsg/hw/net/pcnet.c-119- (BCR_SSIZE32(S) ? (A) : (A) | ((0xff00 & (uint32_t)(S)->csr[2])<<16))
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-647-
qemu-5.1+dfsg/hw/net/pcnet.c:648:static inline hwaddr pcnet_rdra_addr(PCNetState *s, int idx)
qemu-5.1+dfsg/hw/net/pcnet.c-649-{
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-775-
qemu-5.1+dfsg/hw/net/pcnet.c:776: trace_pcnet_init(s, PHYSADDR(s, CSR_IADR(s)));
qemu-5.1+dfsg/hw/net/pcnet.c-777-
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-779- struct pcnet_initblk32 initblk;
qemu-5.1+dfsg/hw/net/pcnet.c:780: s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
qemu-5.1+dfsg/hw/net/pcnet.c-781- (uint8_t *)&initblk, sizeof(initblk), 0);
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-795- struct pcnet_initblk16 initblk;
qemu-5.1+dfsg/hw/net/pcnet.c:796: s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
qemu-5.1+dfsg/hw/net/pcnet.c-797- (uint8_t *)&initblk, sizeof(initblk), 0);
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-826- s->csr[14] = padr[2];
qemu-5.1+dfsg/hw/net/pcnet.c:827: s->rdra = PHYSADDR(s, rdra);
qemu-5.1+dfsg/hw/net/pcnet.c:828: s->tdra = PHYSADDR(s, tdra);
qemu-5.1+dfsg/hw/net/pcnet.c-829-
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-878-#if 1
qemu-5.1+dfsg/hw/net/pcnet.c:879: hwaddr crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
qemu-5.1+dfsg/hw/net/pcnet.c:880: hwaddr nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
qemu-5.1+dfsg/hw/net/pcnet.c:881: hwaddr nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
qemu-5.1+dfsg/hw/net/pcnet.c-882-#else
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-921- struct pcnet_RMD rmd;
qemu-5.1+dfsg/hw/net/pcnet.c:922: RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
qemu-5.1+dfsg/hw/net/pcnet.c-923- CSR_CRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-926- printf("CRDA=0x%08x CRST=0x%04x RCVRC=%d RMDL=0x%04x RMDS=0x%04x RMDM=0x%08x\n",
qemu-5.1+dfsg/hw/net/pcnet.c:927: PHYSADDR(s,CSR_CRDA(s)), CSR_CRST(s), CSR_RCVRC(s),
qemu-5.1+dfsg/hw/net/pcnet.c-928- rmd.buf_length, rmd.status, rmd.msg_length);
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-936- struct pcnet_RMD rmd;
qemu-5.1+dfsg/hw/net/pcnet.c:937: RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
qemu-5.1+dfsg/hw/net/pcnet.c-938- CSR_NRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-972-
qemu-5.1+dfsg/hw/net/pcnet.c:973: TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
qemu-5.1+dfsg/hw/net/pcnet.c-974-
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1088-
qemu-5.1+dfsg/hw/net/pcnet.c:1089: RMDLOAD(&rmd, PHYSADDR(s,crda));
qemu-5.1+dfsg/hw/net/pcnet.c-1090- /*if (!CSR_LAPPEN(s))*/
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1094- int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
qemu-5.1+dfsg/hw/net/pcnet.c:1095: hwaddr rbadr = PHYSADDR(s, rmd.rbadr); \
qemu-5.1+dfsg/hw/net/pcnet.c-1096- s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1098- SET_FIELD(&rmd.status, RMDS, OWN, 0); \
qemu-5.1+dfsg/hw/net/pcnet.c:1099: RMDSTORE(&rmd, PHYSADDR(s,crda)); \
qemu-5.1+dfsg/hw/net/pcnet.c-1100- pktcount++; \
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1109-#endif
qemu-5.1+dfsg/hw/net/pcnet.c:1110: RMDLOAD(&rmd, PHYSADDR(s,nrda));
qemu-5.1+dfsg/hw/net/pcnet.c-1111- if (GET_FIELD(rmd.status, RMDS, OWN)) {
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1117- if ((remaining > 0) && (nrda=CSR_NNRD(s))) {
qemu-5.1+dfsg/hw/net/pcnet.c:1118: RMDLOAD(&rmd, PHYSADDR(s,nrda));
qemu-5.1+dfsg/hw/net/pcnet.c-1119- if (GET_FIELD(rmd.status, RMDS, OWN)) {
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1128-
qemu-5.1+dfsg/hw/net/pcnet.c:1129: RMDLOAD(&rmd, PHYSADDR(s,crda));
qemu-5.1+dfsg/hw/net/pcnet.c-1130- if (remaining == 0) {
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1144- }
qemu-5.1+dfsg/hw/net/pcnet.c:1145: RMDSTORE(&rmd, PHYSADDR(s,crda));
qemu-5.1+dfsg/hw/net/pcnet.c-1146- s->csr[0] |= 0x0400;
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1149- printf("RCVRC=%d CRDA=0x%08x BLKS=%d\n",
qemu-5.1+dfsg/hw/net/pcnet.c:1150: CSR_RCVRC(s), PHYSADDR(s,CSR_CRDA(s)), pktcount);
qemu-5.1+dfsg/hw/net/pcnet.c-1151-#endif
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1200-
qemu-5.1+dfsg/hw/net/pcnet.c:1201: TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
qemu-5.1+dfsg/hw/net/pcnet.c-1202-
qemu-5.1+dfsg/hw/net/pcnet.c-1203-#ifdef PCNET_DEBUG_TMD
qemu-5.1+dfsg/hw/net/pcnet.c:1204: printf(" TMDLOAD 0x%08x\n", PHYSADDR(s,CSR_CXDA(s)));
qemu-5.1+dfsg/hw/net/pcnet.c-1205- PRINT_TMD(&tmd);
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1208- s->xmit_pos = 0;
qemu-5.1+dfsg/hw/net/pcnet.c:1209: xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
qemu-5.1+dfsg/hw/net/pcnet.c-1210- if (BCR_SWSTYLE(s) != 1)
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1237-
qemu-5.1+dfsg/hw/net/pcnet.c:1238: s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
qemu-5.1+dfsg/hw/net/pcnet.c-1239- s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
##############################################
qemu-5.1+dfsg/hw/net/pcnet.c-1267- SET_FIELD(&tmd.status, TMDS, OWN, 0);
qemu-5.1+dfsg/hw/net/pcnet.c:1268: TMDSTORE(&tmd, PHYSADDR(s,CSR_CXDA(s)));
qemu-5.1+dfsg/hw/net/pcnet.c-1269- if (!CSR_TOKINTD(s)
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker.c-309-
qemu-5.1+dfsg/hw/net/rocker/rocker.c:310: fp_port_get_macaddr(fp_port, &macaddr);
qemu-5.1+dfsg/hw/net/rocker/rocker.c-311- mode = world_type(fp_port_get_world(fp_port));
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker.c-396- sizeof(macaddr.a));
qemu-5.1+dfsg/hw/net/rocker/rocker.c:397: fp_port_set_macaddr(fp_port, &macaddr);
qemu-5.1+dfsg/hw/net/rocker/rocker.c-398- }
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker.c-806- case ROCKER_DMA_DESC_ADDR_OFFSET + 4:
qemu-5.1+dfsg/hw/net/rocker/rocker.c:807: desc_ring_set_base_addr(r->rings[index],
qemu-5.1+dfsg/hw/net/rocker/rocker.c-808- ((uint64_t)val) << 32 | r->lower32);
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker.c-885- case ROCKER_DMA_DESC_ADDR_OFFSET:
qemu-5.1+dfsg/hw/net/rocker/rocker.c:886: desc_ring_set_base_addr(r->rings[index], val);
qemu-5.1+dfsg/hw/net/rocker/rocker.c-887- break;
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker.c-1054- case ROCKER_DMA_DESC_ADDR_OFFSET:
qemu-5.1+dfsg/hw/net/rocker/rocker.c:1055: ret = (uint32_t)desc_ring_get_base_addr(r->rings[index]);
qemu-5.1+dfsg/hw/net/rocker/rocker.c-1056- break;
qemu-5.1+dfsg/hw/net/rocker/rocker.c-1057- case ROCKER_DMA_DESC_ADDR_OFFSET + 4:
qemu-5.1+dfsg/hw/net/rocker/rocker.c:1058: ret = (uint32_t)(desc_ring_get_base_addr(r->rings[index]) >> 32);
qemu-5.1+dfsg/hw/net/rocker/rocker.c-1059- break;
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker.c-1145- case ROCKER_DMA_DESC_ADDR_OFFSET:
qemu-5.1+dfsg/hw/net/rocker/rocker.c:1146: ret = desc_ring_get_base_addr(r->rings[index]);
qemu-5.1+dfsg/hw/net/rocker/rocker.c-1147- break;
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker.c-1496- DEFINE_PROP_STRING("world", Rocker, world_name),
qemu-5.1+dfsg/hw/net/rocker/rocker.c:1497: DEFINE_PROP_MACADDR("fp_start_macaddr", Rocker,
qemu-5.1+dfsg/hw/net/rocker/rocker.c-1498- fp_start_macaddr),
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.c-103-
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.c:104:bool desc_ring_set_base_addr(DescRing *ring, uint64_t base_addr)
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.c-105-{
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.c-106- if (base_addr & 0x7) {
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.c:107: DPRINTF("ERROR: ring[%d] desc base addr (0x" TARGET_FMT_plx
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.c-108- ") not 8-byte aligned\n", ring->index, base_addr);
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.c-116-
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.c:117:uint64_t desc_ring_get_base_addr(DescRing *ring)
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.c-118-{
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.h-30-int desc_ring_index(DescRing *ring);
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.h:31:bool desc_ring_set_base_addr(DescRing *ring, uint64_t base_addr);
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.h:32:uint64_t desc_ring_get_base_addr(DescRing *ring);
qemu-5.1+dfsg/hw/net/rocker/rocker_desc.h-33-bool desc_ring_set_size(DescRing *ring, uint32_t size);
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.c-63-
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.c:64:void fp_port_get_macaddr(FpPort *port, MACAddr *macaddr)
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.c-65-{
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.c-68-
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.c:69:void fp_port_set_macaddr(FpPort *port, MACAddr *macaddr)
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.c-70-{
##############################################
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.h-31-void fp_port_get_info(FpPort *port, RockerPortList *info);
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.h:32:void fp_port_get_macaddr(FpPort *port, MACAddr *macaddr);
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.h:33:void fp_port_set_macaddr(FpPort *port, MACAddr *macaddr);
qemu-5.1+dfsg/hw/net/rocker/rocker_fp.h-34-uint8_t fp_port_get_learning(FpPort *port);
##############################################
qemu-5.1+dfsg/hw/net/rtl8139.c-3227- VMSTATE_UNUSED(4),
qemu-5.1+dfsg/hw/net/rtl8139.c:3228: VMSTATE_MACADDR(conf.macaddr, RTL8139State),
qemu-5.1+dfsg/hw/net/rtl8139.c-3229- VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
##############################################
qemu-5.1+dfsg/hw/net/spapr_llan.c-61-#define VLAN_BD_ADDR_MASK 0x00000000ffffffffULL
qemu-5.1+dfsg/hw/net/spapr_llan.c:62:#define VLAN_BD_ADDR(bd) ((bd) & VLAN_BD_ADDR_MASK)
qemu-5.1+dfsg/hw/net/spapr_llan.c-63-
##############################################
qemu-5.1+dfsg/hw/net/spapr_llan.c-237- /* Transfer the packet data */
qemu-5.1+dfsg/hw/net/spapr_llan.c:238: if (spapr_vio_dma_write(sdev, VLAN_BD_ADDR(bd) + 8, buf, size) < 0) {
qemu-5.1+dfsg/hw/net/spapr_llan.c-239- return -1;
##############################################
qemu-5.1+dfsg/hw/net/spapr_llan.c-249-
qemu-5.1+dfsg/hw/net/spapr_llan.c:250: handle = vio_ldq(sdev, VLAN_BD_ADDR(bd));
qemu-5.1+dfsg/hw/net/spapr_llan.c:251: vio_stq(sdev, VLAN_BD_ADDR(rxq_bd) + dev->rxq_ptr + 8, handle);
qemu-5.1+dfsg/hw/net/spapr_llan.c:252: vio_stl(sdev, VLAN_BD_ADDR(rxq_bd) + dev->rxq_ptr + 4, size);
qemu-5.1+dfsg/hw/net/spapr_llan.c:253: vio_sth(sdev, VLAN_BD_ADDR(rxq_bd) + dev->rxq_ptr + 2, 8);
qemu-5.1+dfsg/hw/net/spapr_llan.c:254: vio_stb(sdev, VLAN_BD_ADDR(rxq_bd) + dev->rxq_ptr, control);
qemu-5.1+dfsg/hw/net/spapr_llan.c-255-
qemu-5.1+dfsg/hw/net/spapr_llan.c-256- trace_spapr_vlan_receive_wrote(dev->rxq_ptr,
qemu-5.1+dfsg/hw/net/spapr_llan.c:257: vio_ldq(sdev, VLAN_BD_ADDR(rxq_bd) +
qemu-5.1+dfsg/hw/net/spapr_llan.c-258- dev->rxq_ptr),
qemu-5.1+dfsg/hw/net/spapr_llan.c:259: vio_ldq(sdev, VLAN_BD_ADDR(rxq_bd) +
qemu-5.1+dfsg/hw/net/spapr_llan.c-260- dev->rxq_ptr + 8));
##############################################
qemu-5.1+dfsg/hw/net/spapr_llan.c-421-{
qemu-5.1+dfsg/hw/net/spapr_llan.c:422: if ((VLAN_BD_ADDR(bd) % alignment)
qemu-5.1+dfsg/hw/net/spapr_llan.c-423- || (VLAN_BD_LEN(bd) % alignment)) {
##############################################
qemu-5.1+dfsg/hw/net/spapr_llan.c-426-
qemu-5.1+dfsg/hw/net/spapr_llan.c:427: if (!spapr_vio_dma_valid(&dev->sdev, VLAN_BD_ADDR(bd),
qemu-5.1+dfsg/hw/net/spapr_llan.c-428- VLAN_BD_LEN(bd), DMA_DIRECTION_FROM_DEVICE)
qemu-5.1+dfsg/hw/net/spapr_llan.c:429: || !spapr_vio_dma_valid(&dev->sdev, VLAN_BD_ADDR(bd),
qemu-5.1+dfsg/hw/net/spapr_llan.c-430- VLAN_BD_LEN(bd), DMA_DIRECTION_TO_DEVICE)) {
##############################################
qemu-5.1+dfsg/hw/net/spapr_llan.c-493- /* Initialize the receive queue */
qemu-5.1+dfsg/hw/net/spapr_llan.c:494: spapr_vio_dma_set(sdev, VLAN_BD_ADDR(rec_queue), 0, VLAN_BD_LEN(rec_queue));
qemu-5.1+dfsg/hw/net/spapr_llan.c-495-
##############################################
qemu-5.1+dfsg/hw/net/spapr_llan.c-734- for (i = 0; i < nbufs; i++) {
qemu-5.1+dfsg/hw/net/spapr_llan.c:735: ret = spapr_vio_dma_read(sdev, VLAN_BD_ADDR(bufs[i]),
qemu-5.1+dfsg/hw/net/spapr_llan.c-736- p, VLAN_BD_LEN(bufs[i]));
##############################################
qemu-5.1+dfsg/hw/net/sungem.c-1399- VMSTATE_PCI_DEVICE(pdev, SunGEMState),
qemu-5.1+dfsg/hw/net/sungem.c:1400: VMSTATE_MACADDR(conf.macaddr, SunGEMState),
qemu-5.1+dfsg/hw/net/sungem.c-1401- VMSTATE_UINT32(phy_addr, SunGEMState),
##############################################
qemu-5.1+dfsg/hw/net/sunhme.c-938- VMSTATE_PCI_DEVICE(parent_obj, SunHMEState),
qemu-5.1+dfsg/hw/net/sunhme.c:939: VMSTATE_MACADDR(conf.macaddr, SunHMEState),
qemu-5.1+dfsg/hw/net/sunhme.c-940- VMSTATE_UINT32_ARRAY(sebregs, SunHMEState, (HME_SEB_REG_SIZE >> 2)),
##############################################
qemu-5.1+dfsg/hw/net/trace-events-270-
qemu-5.1+dfsg/hw/net/trace-events:271:e1000e_io_write_addr(uint64_t addr) "IOADDR write 0x%"PRIx64
qemu-5.1+dfsg/hw/net/trace-events-272-e1000e_io_write_data(uint64_t addr, uint64_t val) "IODATA write 0x%"PRIx64", value: 0x%"PRIx64
qemu-5.1+dfsg/hw/net/trace-events:273:e1000e_io_read_addr(uint64_t addr) "IOADDR read 0x%"PRIx64
qemu-5.1+dfsg/hw/net/trace-events-274-e1000e_io_read_data(uint64_t addr, uint64_t val) "IODATA read 0x%"PRIx64", value: 0x%"PRIx64
##############################################
qemu-5.1+dfsg/hw/net/tulip.c-607-
qemu-5.1+dfsg/hw/net/tulip.c:608:static void tulip_setup_filter_addr(TULIPState *s, uint8_t *buf, int n)
qemu-5.1+dfsg/hw/net/tulip.c-609-{
##############################################
qemu-5.1+dfsg/hw/net/tulip.c-636- for (i = 0; i < 16; i++) {
qemu-5.1+dfsg/hw/net/tulip.c:637: tulip_setup_filter_addr(s, buf, i);
qemu-5.1+dfsg/hw/net/tulip.c-638- }
##############################################
qemu-5.1+dfsg/hw/net/vmware_utils.h-141-*/
qemu-5.1+dfsg/hw/net/vmware_utils.h:142:#define VMW_IS_MULTIREG_ADDR(addr, base, cnt, regsize) \
qemu-5.1+dfsg/hw/net/vmware_utils.h-143- range_covers_byte(base, cnt * regsize, addr)
##############################################
qemu-5.1+dfsg/hw/net/vmware_utils.h-149-*/
qemu-5.1+dfsg/hw/net/vmware_utils.h:150:#define VMW_MULTIREG_IDX_BY_ADDR(addr, base, regsize) \
qemu-5.1+dfsg/hw/net/vmware_utils.h-151- (((addr) - (base)) / (regsize))
##############################################
qemu-5.1+dfsg/hw/net/vmxnet3.c-1090-
qemu-5.1+dfsg/hw/net/vmxnet3.c:1091: if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
qemu-5.1+dfsg/hw/net/vmxnet3.c-1092- VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
qemu-5.1+dfsg/hw/net/vmxnet3.c-1093- int tx_queue_idx =
qemu-5.1+dfsg/hw/net/vmxnet3.c:1094: VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
qemu-5.1+dfsg/hw/net/vmxnet3.c-1095- VMXNET3_REG_ALIGN);
##############################################
qemu-5.1+dfsg/hw/net/vmxnet3.c-1100-
qemu-5.1+dfsg/hw/net/vmxnet3.c:1101: if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
qemu-5.1+dfsg/hw/net/vmxnet3.c-1102- VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
qemu-5.1+dfsg/hw/net/vmxnet3.c:1103: int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
qemu-5.1+dfsg/hw/net/vmxnet3.c-1104- VMXNET3_REG_ALIGN);
##############################################
qemu-5.1+dfsg/hw/net/vmxnet3.c-1111-
qemu-5.1+dfsg/hw/net/vmxnet3.c:1112: if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
qemu-5.1+dfsg/hw/net/vmxnet3.c-1113- VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
qemu-5.1+dfsg/hw/net/vmxnet3.c:1114: VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
qemu-5.1+dfsg/hw/net/vmxnet3.c-1115- VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
##############################################
qemu-5.1+dfsg/hw/net/vmxnet3.c-1127-
qemu-5.1+dfsg/hw/net/vmxnet3.c:1128: if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
qemu-5.1+dfsg/hw/net/vmxnet3.c-1129- VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
qemu-5.1+dfsg/hw/net/vmxnet3.c:1130: int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
qemu-5.1+dfsg/hw/net/vmxnet3.c-1131- VMXNET3_REG_ALIGN);
##############################################
qemu-5.1+dfsg/hw/net/vmxnet3.h-173-#define VMXNET3_IO_TYPE_VD 1
qemu-5.1+dfsg/hw/net/vmxnet3.h:174:#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
qemu-5.1+dfsg/hw/net/vmxnet3.h-175-#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
##############################################
qemu-5.1+dfsg/hw/net/xen_nic.c-291-
qemu-5.1+dfsg/hw/net/xen_nic.c:292: if (net_parse_macaddr(netdev->conf.macaddr.a, netdev->mac) < 0) {
qemu-5.1+dfsg/hw/net/xen_nic.c-293- return -1;
##############################################
qemu-5.1+dfsg/hw/net/xilinx_axienet.c-680-
qemu-5.1+dfsg/hw/net/xilinx_axienet.c:681:static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
qemu-5.1+dfsg/hw/net/xilinx_axienet.c-682-{
##############################################
qemu-5.1+dfsg/hw/net/xilinx_axienet.c-763- if (unicast) {
qemu-5.1+dfsg/hw/net/xilinx_axienet.c:764: if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
qemu-5.1+dfsg/hw/net/xilinx_axienet.c-765- return size;
##############################################
qemu-5.1+dfsg/hw/net/xilinx_axienet.c-781- for (i = 0; i < 4; i++) {
qemu-5.1+dfsg/hw/net/xilinx_axienet.c:782: if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
qemu-5.1+dfsg/hw/net/xilinx_axienet.c-783- drop = 0;
##############################################
qemu-5.1+dfsg/hw/net/xilinx_axienet.c-797- if (unicast) {
qemu-5.1+dfsg/hw/net/xilinx_axienet.c:798: if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
qemu-5.1+dfsg/hw/net/xilinx_axienet.c-799- return size;
##############################################
qemu-5.1+dfsg/hw/pci-host/bonito.c-171-#define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */
qemu-5.1+dfsg/hw/pci-host/bonito.c:172:#define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */
qemu-5.1+dfsg/hw/pci-host/bonito.c-173-#define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */
##############################################
qemu-5.1+dfsg/hw/pci-host/bonito.c-196-
qemu-5.1+dfsg/hw/pci-host/bonito.c:197:#define PCI_ADDR(busno , devno , funno , regno) \
qemu-5.1+dfsg/hw/pci-host/bonito.c-198- ((((busno) << 16) & 0xff0000) + (((devno) << 11) & 0xf800) + \
##############################################
qemu-5.1+dfsg/hw/pci-host/bonito.c-445-
qemu-5.1+dfsg/hw/pci-host/bonito.c:446:static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
qemu-5.1+dfsg/hw/pci-host/bonito.c-447-{
##############################################
qemu-5.1+dfsg/hw/pci-host/bonito.c-475- }
qemu-5.1+dfsg/hw/pci-host/bonito.c:476: pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
qemu-5.1+dfsg/hw/pci-host/bonito.c-477- DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
##############################################
qemu-5.1+dfsg/hw/pci-host/bonito.c-494-
qemu-5.1+dfsg/hw/pci-host/bonito.c:495: pciaddr = bonito_sbridge_pciaddr(s, addr);
qemu-5.1+dfsg/hw/pci-host/bonito.c-496-
##############################################
qemu-5.1+dfsg/hw/pci-host/bonito.c-520-
qemu-5.1+dfsg/hw/pci-host/bonito.c:521: pciaddr = bonito_sbridge_pciaddr(s, addr);
qemu-5.1+dfsg/hw/pci-host/bonito.c-522-
##############################################
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c-21-
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c:22:static uint64_t phb3_msi_ive_addr(PnvPHB3 *phb, int srcno)
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c-23-{
##############################################
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c-50-
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c:51: ive_addr = phb3_msi_ive_addr(phb, srcno);
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c-52- if (!ive_addr) {
##############################################
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c-70-
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c:71: ive_addr = phb3_msi_ive_addr(msi->phb, srcno);
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c-72- if (!ive_addr) {
##############################################
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c-86-
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c:87: ive_addr = phb3_msi_ive_addr(msi->phb, srcno);
qemu-5.1+dfsg/hw/pci-host/pnv_phb3_msi.c-88- if (!ive_addr) {
##############################################
qemu-5.1+dfsg/hw/pci/pci.c-674- */
qemu-5.1+dfsg/hw/pci/pci.c:675:static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
qemu-5.1+dfsg/hw/pci/pci.c-676- unsigned int *slotp, unsigned int *funcp)
##############################################
qemu-5.1+dfsg/hw/pci/pci.c-1241-
qemu-5.1+dfsg/hw/pci/pci.c:1242:pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
qemu-5.1+dfsg/hw/pci/pci.c-1243-{
##############################################
qemu-5.1+dfsg/hw/pci/pci.c-1934- } else {
qemu-5.1+dfsg/hw/pci/pci.c:1935: if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
qemu-5.1+dfsg/hw/pci/pci.c-1936- error_report("Invalid PCI device address %s for device %s",
##############################################
qemu-5.1+dfsg/hw/pci/pcie_host.c-28-/* a helper function to get a PCIDevice for a given mmconfig address */
qemu-5.1+dfsg/hw/pci/pcie_host.c:29:static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
qemu-5.1+dfsg/hw/pci/pcie_host.c-30- uint32_t mmcfg_addr)
##############################################
qemu-5.1+dfsg/hw/pci/pcie_host.c-40- PCIBus *s = e->pci.bus;
qemu-5.1+dfsg/hw/pci/pcie_host.c:41: PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
qemu-5.1+dfsg/hw/pci/pcie_host.c-42- uint32_t addr;
##############################################
qemu-5.1+dfsg/hw/pci/pcie_host.c-58- PCIBus *s = e->pci.bus;
qemu-5.1+dfsg/hw/pci/pcie_host.c:59: PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
qemu-5.1+dfsg/hw/pci/pcie_host.c-60- uint32_t addr;
##############################################
qemu-5.1+dfsg/hw/pci/pci_host.c-48-/* the helper function to get a PCIDevice* for a given pci address */
qemu-5.1+dfsg/hw/pci/pci_host.c:49:static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
qemu-5.1+dfsg/hw/pci/pci_host.c-50-{
##############################################
qemu-5.1+dfsg/hw/pci/pci_host.c-112-{
qemu-5.1+dfsg/hw/pci/pci_host.c:113: PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
qemu-5.1+dfsg/hw/pci/pci_host.c-114- uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
##############################################
qemu-5.1+dfsg/hw/pci/pci_host.c-125-{
qemu-5.1+dfsg/hw/pci/pci_host.c:126: PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
qemu-5.1+dfsg/hw/pci/pci_host.c-127- uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
##############################################
qemu-5.1+dfsg/hw/ppc/e500.c-216- PlatformBusDevice *pbus = data->pbus;
qemu-5.1+dfsg/hw/ppc/e500.c:217: hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
qemu-5.1+dfsg/hw/ppc/e500.c-218- int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
##############################################
qemu-5.1+dfsg/hw/ppc/spapr.c-3381- /* get rtas addr from fdt */
qemu-5.1+dfsg/hw/ppc/spapr.c:3382: rtas_addr = spapr_get_rtas_addr();
qemu-5.1+dfsg/hw/ppc/spapr.c-3383- if (!rtas_addr) {
##############################################
qemu-5.1+dfsg/hw/ppc/spapr_events.c-833- /* get rtas addr from fdt */
qemu-5.1+dfsg/hw/ppc/spapr_events.c:834: rtas_addr = spapr_get_rtas_addr();
qemu-5.1+dfsg/hw/ppc/spapr_events.c-835- if (!rtas_addr) {
##############################################
qemu-5.1+dfsg/hw/ppc/spapr_ovec.c-153-
qemu-5.1+dfsg/hw/ppc/spapr_ovec.c:154:static target_ulong vector_addr(target_ulong table_addr, int vector)
qemu-5.1+dfsg/hw/ppc/spapr_ovec.c-155-{
##############################################
qemu-5.1+dfsg/hw/ppc/spapr_ovec.c-181-
qemu-5.1+dfsg/hw/ppc/spapr_ovec.c:182: addr = vector_addr(table_addr, vector);
qemu-5.1+dfsg/hw/ppc/spapr_ovec.c-183- if (!addr) {
##############################################
qemu-5.1+dfsg/hw/ppc/spapr_pci.c-95-
qemu-5.1+dfsg/hw/ppc/spapr_pci.c:96:static uint32_t rtas_pci_cfgaddr(uint32_t arg)
qemu-5.1+dfsg/hw/ppc/spapr_pci.c-97-{
##############################################
qemu-5.1+dfsg/hw/ppc/spapr_pci.c-115- pci_dev = spapr_pci_find_dev(spapr, buid, addr);
qemu-5.1+dfsg/hw/ppc/spapr_pci.c:116: addr = rtas_pci_cfgaddr(addr);
qemu-5.1+dfsg/hw/ppc/spapr_pci.c-117-
##############################################
qemu-5.1+dfsg/hw/ppc/spapr_pci.c-182- pci_dev = spapr_pci_find_dev(spapr, buid, addr);
qemu-5.1+dfsg/hw/ppc/spapr_pci.c:183: addr = rtas_pci_cfgaddr(addr);
qemu-5.1+dfsg/hw/ppc/spapr_pci.c-184-
##############################################
qemu-5.1+dfsg/hw/ppc/spapr_rtas.c-423-
qemu-5.1+dfsg/hw/ppc/spapr_rtas.c:424: rtas_addr = spapr_get_rtas_addr();
qemu-5.1+dfsg/hw/ppc/spapr_rtas.c-425- if (!rtas_addr) {
##############################################
qemu-5.1+dfsg/hw/ppc/spapr_rtas.c-575-
qemu-5.1+dfsg/hw/ppc/spapr_rtas.c:576:hwaddr spapr_get_rtas_addr(void)
qemu-5.1+dfsg/hw/ppc/spapr_rtas.c-577-{
##############################################
qemu-5.1+dfsg/hw/s390x/css.c-238-
qemu-5.1+dfsg/hw/s390x/css.c:239:static int post_load_ind_addr(void *opaque, int version_id)
qemu-5.1+dfsg/hw/s390x/css.c-240-{
##############################################
qemu-5.1+dfsg/hw/s390x/css.c-251-
qemu-5.1+dfsg/hw/s390x/css.c:252:static int pre_save_ind_addr(void *opaque)
qemu-5.1+dfsg/hw/s390x/css.c-253-{
##############################################
qemu-5.1+dfsg/hw/s390x/ipl.c-102-
qemu-5.1+dfsg/hw/s390x/ipl.c:103:static uint64_t bios_translate_addr(void *opaque, uint64_t srcaddr)
qemu-5.1+dfsg/hw/s390x/ipl.c-104-{
##############################################
qemu-5.1+dfsg/hw/s390x/virtio-ccw.c-99- VMSTATE_CCW_DEVICE(parent_obj, VirtioCcwDevice),
qemu-5.1+dfsg/hw/s390x/virtio-ccw.c:100: VMSTATE_PTR_TO_IND_ADDR(indicators, VirtioCcwDevice),
qemu-5.1+dfsg/hw/s390x/virtio-ccw.c:101: VMSTATE_PTR_TO_IND_ADDR(indicators2, VirtioCcwDevice),
qemu-5.1+dfsg/hw/s390x/virtio-ccw.c:102: VMSTATE_PTR_TO_IND_ADDR(summary_indicator, VirtioCcwDevice),
qemu-5.1+dfsg/hw/s390x/virtio-ccw.c-103- /*
##############################################
qemu-5.1+dfsg/hw/s390x/virtio-ccw.c-223- } else {
qemu-5.1+dfsg/hw/s390x/virtio-ccw.c:224: virtio_queue_set_addr(vdev, index, desc);
qemu-5.1+dfsg/hw/s390x/virtio-ccw.c-225- }
##############################################
qemu-5.1+dfsg/hw/scsi/megasas.c-221-
qemu-5.1+dfsg/hw/scsi/megasas.c:222:static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
qemu-5.1+dfsg/hw/scsi/megasas.c-223- union mfi_sgl *sgl)
##############################################
qemu-5.1+dfsg/hw/scsi/megasas.c-293- }
qemu-5.1+dfsg/hw/scsi/megasas.c:294: iov_pa = megasas_sgl_get_addr(cmd, sgl);
qemu-5.1+dfsg/hw/scsi/megasas.c-295- iov_size_p = megasas_sgl_get_len(cmd, sgl);
##############################################
qemu-5.1+dfsg/hw/scsi/megasas.c-431- */
qemu-5.1+dfsg/hw/scsi/megasas.c:432:static uint64_t megasas_get_sata_addr(uint16_t id)
qemu-5.1+dfsg/hw/scsi/megasas.c-433-{
##############################################
qemu-5.1+dfsg/hw/scsi/megasas.c-708- }
qemu-5.1+dfsg/hw/scsi/megasas.c:709: iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
qemu-5.1+dfsg/hw/scsi/megasas.c-710- iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
##############################################
qemu-5.1+dfsg/hw/scsi/megasas.c-773- info.device.port_addr[num_pd_disks] =
qemu-5.1+dfsg/hw/scsi/megasas.c:774: cpu_to_le64(megasas_get_sata_addr(pd_id));
qemu-5.1+dfsg/hw/scsi/megasas.c-775- }
##############################################
qemu-5.1+dfsg/hw/scsi/megasas.c-998- info.addr[num_pd_disks].sas_addr[0] =
qemu-5.1+dfsg/hw/scsi/megasas.c:999: cpu_to_le64(megasas_get_sata_addr(pd_id));
qemu-5.1+dfsg/hw/scsi/megasas.c-1000- num_pd_disks++;
##############################################
qemu-5.1+dfsg/hw/scsi/megasas.c-1098- info->path_info.sas_addr[0] =
qemu-5.1+dfsg/hw/scsi/megasas.c:1099: cpu_to_le64(megasas_get_sata_addr(pd_id));
qemu-5.1+dfsg/hw/scsi/megasas.c-1100- info->connected_port_bitmap = 0x1;
##############################################
qemu-5.1+dfsg/hw/sd/sd.c-818-
qemu-5.1+dfsg/hw/sd/sd.c:819:static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
qemu-5.1+dfsg/hw/sd/sd.c-820-{
##############################################
qemu-5.1+dfsg/hw/sd/sd.c-1251-
qemu-5.1+dfsg/hw/sd/sd.c:1252: if (sd_wp_addr(sd, sd->data_start)) {
qemu-5.1+dfsg/hw/sd/sd.c-1253- sd->card_status |= WP_VIOLATION;
##############################################
qemu-5.1+dfsg/hw/sd/sd.c-1281-
qemu-5.1+dfsg/hw/sd/sd.c:1282: if (sd_wp_addr(sd, sd->data_start)) {
qemu-5.1+dfsg/hw/sd/sd.c-1283- sd->card_status |= WP_VIOLATION;
##############################################
qemu-5.1+dfsg/hw/sd/sd.c-1850- }
qemu-5.1+dfsg/hw/sd/sd.c:1851: if (sd_wp_addr(sd, sd->data_start)) {
qemu-5.1+dfsg/hw/sd/sd.c-1852- sd->card_status |= WP_VIOLATION;
##############################################
qemu-5.1+dfsg/hw/sh4/r2d.c-263- pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
qemu-5.1+dfsg/hw/sh4/r2d.c:264: sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
qemu-5.1+dfsg/hw/sh4/r2d.c:265: sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
qemu-5.1+dfsg/hw/sh4/r2d.c-266- sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
##############################################
qemu-5.1+dfsg/hw/sh4/sh7750.c-651-#define MM_REGION_MASK 0x07000000
qemu-5.1+dfsg/hw/sh4/sh7750.c:652:#define MM_ICACHE_ADDR (0)
qemu-5.1+dfsg/hw/sh4/sh7750.c-653-#define MM_ICACHE_DATA (1)
qemu-5.1+dfsg/hw/sh4/sh7750.c:654:#define MM_ITLB_ADDR (2)
qemu-5.1+dfsg/hw/sh4/sh7750.c-655-#define MM_ITLB_DATA (3)
qemu-5.1+dfsg/hw/sh4/sh7750.c:656:#define MM_OCACHE_ADDR (4)
qemu-5.1+dfsg/hw/sh4/sh7750.c-657-#define MM_OCACHE_DATA (5)
qemu-5.1+dfsg/hw/sh4/sh7750.c:658:#define MM_UTLB_ADDR (6)
qemu-5.1+dfsg/hw/sh4/sh7750.c-659-#define MM_UTLB_DATA (7)
##############################################
qemu-5.1+dfsg/hw/sh4/sh7750.c-684- case MM_ITLB_ADDR:
qemu-5.1+dfsg/hw/sh4/sh7750.c:685: ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr);
qemu-5.1+dfsg/hw/sh4/sh7750.c-686- break;
##############################################
qemu-5.1+dfsg/hw/sh4/sh7750.c-694- case MM_UTLB_ADDR:
qemu-5.1+dfsg/hw/sh4/sh7750.c:695: ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr);
qemu-5.1+dfsg/hw/sh4/sh7750.c-696- break;
##############################################
qemu-5.1+dfsg/hw/sh4/sh7750.c-727- case MM_ITLB_ADDR:
qemu-5.1+dfsg/hw/sh4/sh7750.c:728: cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value);
qemu-5.1+dfsg/hw/sh4/sh7750.c-729- break;
##############################################
qemu-5.1+dfsg/hw/sh4/sh7750.c-738- case MM_UTLB_ADDR:
qemu-5.1+dfsg/hw/sh4/sh7750.c:739: cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value);
qemu-5.1+dfsg/hw/sh4/sh7750.c-740- break;
##############################################
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c-272-
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c:273:static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c-274- int is_write)
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c-275-{
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c:276: trace_sun4m_iommu_bad_addr(addr);
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c-277- s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
##############################################
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c-306- if (!(pte & IOPTE_VALID)) {
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c:307: iommu_bad_addr(is, page, is_write);
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c-308- return ret;
##############################################
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c-312- if (is_write && !(pte & IOPTE_WRITE)) {
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c:313: iommu_bad_addr(is, page, is_write);
qemu-5.1+dfsg/hw/sparc/sun4m_iommu.c-314- return ret;
##############################################
qemu-5.1+dfsg/hw/sparc/trace-events-16-sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva 0x%"PRIx64" => pa 0x%"PRIx64" iopte = 0x%x"
qemu-5.1+dfsg/hw/sparc/trace-events:17:sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64
qemu-5.1+dfsg/hw/sparc/trace-events-18-
##############################################
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-129-/* DMA Flash Side Address */
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c:130:#define R_DMA_FLASH_ADDR (0x84 / 4)
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-131-
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-132-/* DMA DRAM Side Address */
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c:133:#define R_DMA_DRAM_ADDR (0x88 / 4)
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-134-
##############################################
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-170- */
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c:171:#define DMA_DRAM_ADDR(s, val) ((s)->sdram_base | \
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-172- ((val) & (s)->ctrl->dma_dram_mask))
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c:173:#define DMA_FLASH_ADDR(s, val) ((s)->ctrl->flash_window_base | \
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-174- ((val) & (s)->ctrl->dma_flash_mask))
##############################################
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-666-
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c:667:static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-668- uint32_t addr)
##############################################
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-707- /* Flash access can not exceed CS segment */
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c:708: addr = aspeed_smc_check_segment_addr(fl, addr);
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-709-
##############################################
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-1285- } else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) {
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c:1286: s->regs[addr] = DMA_DRAM_ADDR(s, value);
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-1287- } else if (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) {
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c:1288: s->regs[addr] = DMA_FLASH_ADDR(s, value);
qemu-5.1+dfsg/hw/ssi/aspeed_smc.c-1289- } else if (s->ctrl->has_dma && addr == R_DMA_LEN) {
##############################################
qemu-5.1+dfsg/hw/timer/cadence_ttc.c-86-
qemu-5.1+dfsg/hw/timer/cadence_ttc.c:87:static CadenceTimerState *cadence_timer_from_addr(void *opaque,
qemu-5.1+dfsg/hw/timer/cadence_ttc.c-88- hwaddr offset)
##############################################
qemu-5.1+dfsg/hw/timer/cadence_ttc.c-236-{
qemu-5.1+dfsg/hw/timer/cadence_ttc.c:237: CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
qemu-5.1+dfsg/hw/timer/cadence_ttc.c-238- uint32_t value;
##############################################
qemu-5.1+dfsg/hw/timer/cadence_ttc.c-319-{
qemu-5.1+dfsg/hw/timer/cadence_ttc.c:320: CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
qemu-5.1+dfsg/hw/timer/cadence_ttc.c-321-
##############################################
qemu-5.1+dfsg/hw/timer/sh_timer.c-335- &s->iomem, 0, 0x1000);
qemu-5.1+dfsg/hw/timer/sh_timer.c:336: memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
qemu-5.1+dfsg/hw/timer/sh_timer.c-337-
##############################################
qemu-5.1+dfsg/hw/timer/sh_timer.c-339- &s->iomem, 0, 0x1000);
qemu-5.1+dfsg/hw/timer/sh_timer.c:340: memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
qemu-5.1+dfsg/hw/timer/sh_timer.c-341- /* ??? Save/restore. */
##############################################
qemu-5.1+dfsg/hw/timer/xilinx_timer.c-82-
qemu-5.1+dfsg/hw/timer/xilinx_timer.c:83:static inline unsigned int timer_from_addr(hwaddr addr)
qemu-5.1+dfsg/hw/timer/xilinx_timer.c-84-{
##############################################
qemu-5.1+dfsg/hw/timer/xilinx_timer.c-111- addr >>= 2;
qemu-5.1+dfsg/hw/timer/xilinx_timer.c:112: timer = timer_from_addr(addr);
qemu-5.1+dfsg/hw/timer/xilinx_timer.c-113- xt = &t->timers[timer];
##############################################
qemu-5.1+dfsg/hw/timer/xilinx_timer.c-162- addr >>= 2;
qemu-5.1+dfsg/hw/timer/xilinx_timer.c:163: timer = timer_from_addr(addr);
qemu-5.1+dfsg/hw/timer/xilinx_timer.c-164- xt = &t->timers[timer];
##############################################
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c-50-
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c:51:static uint8_t tpm_tis_locality_from_addr(hwaddr addr)
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c-52-{
##############################################
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c-294- int idx;
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c:295: uint8_t locty = tpm_tis_locality_from_addr(addr);
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c-296- hwaddr base = addr & ~0xfff;
##############################################
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c-334- uint32_t val = 0xffffffff;
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c:335: uint8_t locty = tpm_tis_locality_from_addr(addr);
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c-336- uint32_t avail;
##############################################
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c-454- uint8_t shift = (addr & 0x3) * 8;
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c:455: uint8_t locty = tpm_tis_locality_from_addr(addr);
qemu-5.1+dfsg/hw/tpm/tpm_tis_common.c-456- uint8_t active_locty, l;
##############################################
qemu-5.1+dfsg/hw/usb/desc.c-717- dev->addr = value;
qemu-5.1+dfsg/hw/usb/desc.c:718: trace_usb_set_addr(dev->addr);
qemu-5.1+dfsg/hw/usb/desc.c-719- ret = 0;
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-286-
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:287:static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-288-{
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-295-
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:296:static int ehci_get_fetch_addr(EHCIState *s, int async)
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-297-{
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1535-
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:1536: ehci_set_fetch_addr(ehci, async, entry);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1537- ehci_set_state(ehci, async, EST_FETCHENTRY);
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1562- int again = 0;
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:1563: uint32_t entry = ehci_get_fetch_addr(ehci, async);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1564-
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1608-
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:1609: entry = ehci_get_fetch_addr(ehci, async);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1610- q = ehci_find_queue_by_qh(ehci, entry, async);
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1699- assert(!async);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:1700: entry = ehci_get_fetch_addr(ehci, async);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1701-
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1713- sizeof(EHCIitd) >> 2);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:1714: ehci_set_fetch_addr(ehci, async, itd.next);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1715- ehci_set_state(ehci, async, EST_FETCHENTRY);
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1725- assert(!async);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:1726: entry = ehci_get_fetch_addr(ehci, async);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1727-
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1740-
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:1741: ehci_set_fetch_addr(ehci, async, sitd.next);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1742- ehci_set_state(ehci, async, EST_FETCHENTRY);
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1856-
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:1857: if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:1858: ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-1859- ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-2210- ehci->frindex / 8, list, entry);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c:2211: ehci_set_fetch_addr(ehci, async,entry);
qemu-5.1+dfsg/hw/usb/hcd-ehci.c-2212- ehci_set_state(ehci, async, EST_FETCHENTRY);
##############################################
qemu-5.1+dfsg/hw/usb/hcd-ohci.c-1976- DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
qemu-5.1+dfsg/hw/usb/hcd-ohci.c:1977: DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
qemu-5.1+dfsg/hw/usb/hcd-ohci.c-1978- DEFINE_PROP_END_OF_LIST(),
##############################################
qemu-5.1+dfsg/hw/usb/trace-events-236-usb_desc_msos(int addr, int index, int len, int ret) "dev %d msos, index 0x%x, len %d, ret %d"
qemu-5.1+dfsg/hw/usb/trace-events:237:usb_set_addr(int addr) "dev %d"
qemu-5.1+dfsg/hw/usb/trace-events-238-usb_set_config(int addr, int config, int ret) "dev %d, config %d, ret %d"
##############################################
qemu-5.1+dfsg/hw/vfio/common.c-409-/* Called with rcu_read_lock held. */
qemu-5.1+dfsg/hw/vfio/common.c:410:static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
qemu-5.1+dfsg/hw/vfio/common.c-411- bool *read_only)
##############################################
qemu-5.1+dfsg/hw/vfio/common.c-468- if ((iotlb->perm & IOMMU_RW) != IOMMU_NONE) {
qemu-5.1+dfsg/hw/vfio/common.c:469: if (!vfio_get_vaddr(iotlb, &vaddr, &read_only)) {
qemu-5.1+dfsg/hw/vfio/common.c-470- goto out;
##############################################
qemu-5.1+dfsg/hw/vfio/pci.c-3138-static Property vfio_pci_dev_properties[] = {
qemu-5.1+dfsg/hw/vfio/pci.c:3139: DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host),
qemu-5.1+dfsg/hw/vfio/pci.c-3140- DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev),
##############################################
qemu-5.1+dfsg/hw/vfio/spapr.c-32-
qemu-5.1+dfsg/hw/vfio/spapr.c:33:static void *vfio_prereg_gpa_to_vaddr(MemoryRegionSection *section, hwaddr gpa)
qemu-5.1+dfsg/hw/vfio/spapr.c-34-{
##############################################
qemu-5.1+dfsg/hw/vfio/spapr.c-75-
qemu-5.1+dfsg/hw/vfio/spapr.c:76: reg.vaddr = (uintptr_t) vfio_prereg_gpa_to_vaddr(section, gpa);
qemu-5.1+dfsg/hw/vfio/spapr.c-77- reg.size = end - gpa;
##############################################
qemu-5.1+dfsg/hw/vfio/spapr.c-131-
qemu-5.1+dfsg/hw/vfio/spapr.c:132: reg.vaddr = (uintptr_t) vfio_prereg_gpa_to_vaddr(section, gpa);
qemu-5.1+dfsg/hw/vfio/spapr.c-133- reg.size = end - gpa;
##############################################
qemu-5.1+dfsg/hw/virtio/trace-events-44-#
qemu-5.1+dfsg/hw/virtio/trace-events:45:virtio_balloon_bad_addr(uint64_t gpa) "0x%"PRIx64
qemu-5.1+dfsg/hw/virtio/trace-events-46-virtio_balloon_handle_output(const char *name, uint64_t gpa) "section name: %s gpa: 0x%"PRIx64
##############################################
qemu-5.1+dfsg/hw/virtio/vhost-backend.c-104-
qemu-5.1+dfsg/hw/virtio/vhost-backend.c:105:static int vhost_kernel_set_vring_addr(struct vhost_dev *dev,
qemu-5.1+dfsg/hw/virtio/vhost-backend.c-106- struct vhost_vring_addr *addr)
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-771-
qemu-5.1+dfsg/hw/virtio/vhost.c:772:static int vhost_virtqueue_set_addr(struct vhost_dev *dev,
qemu-5.1+dfsg/hw/virtio/vhost.c-773- struct vhost_virtqueue *vq,
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-780- if (dev->vhost_ops->vhost_vq_get_addr) {
qemu-5.1+dfsg/hw/virtio/vhost.c:781: r = dev->vhost_ops->vhost_vq_get_addr(dev, &addr, vq);
qemu-5.1+dfsg/hw/virtio/vhost.c-782- if (r < 0) {
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-793- addr.flags = enable_log ? (1 << VHOST_VRING_F_LOG) : 0;
qemu-5.1+dfsg/hw/virtio/vhost.c:794: r = dev->vhost_ops->vhost_set_vring_addr(dev, &addr);
qemu-5.1+dfsg/hw/virtio/vhost.c-795- if (r < 0) {
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-833- idx = dev->vhost_ops->vhost_get_vq_index(dev, dev->vq_index + i);
qemu-5.1+dfsg/hw/virtio/vhost.c:834: r = vhost_virtqueue_set_addr(dev, dev->vqs + i, idx,
qemu-5.1+dfsg/hw/virtio/vhost.c-835- enable_log);
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-843- idx = dev->vhost_ops->vhost_get_vq_index(dev, dev->vq_index + i);
qemu-5.1+dfsg/hw/virtio/vhost.c:844: vhost_virtqueue_set_addr(dev, dev->vqs + i, idx,
qemu-5.1+dfsg/hw/virtio/vhost.c-845- dev->log_enabled);
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-1033-
qemu-5.1+dfsg/hw/virtio/vhost.c:1034: a = virtio_queue_get_desc_addr(vdev, idx);
qemu-5.1+dfsg/hw/virtio/vhost.c-1035- if (a == 0) {
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-1070- vq->avail_size = s = l = virtio_queue_get_avail_size(vdev, idx);
qemu-5.1+dfsg/hw/virtio/vhost.c:1071: vq->avail_phys = a = virtio_queue_get_avail_addr(vdev, idx);
qemu-5.1+dfsg/hw/virtio/vhost.c-1072- vq->avail = vhost_memory_map(dev, a, &l, false);
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-1077- vq->used_size = s = l = virtio_queue_get_used_size(vdev, idx);
qemu-5.1+dfsg/hw/virtio/vhost.c:1078: vq->used_phys = a = virtio_queue_get_used_addr(vdev, idx);
qemu-5.1+dfsg/hw/virtio/vhost.c-1079- vq->used = vhost_memory_map(dev, a, &l, true);
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-1084-
qemu-5.1+dfsg/hw/virtio/vhost.c:1085: r = vhost_virtqueue_set_addr(dev, vq, vhost_vq_index, dev->log_enabled);
qemu-5.1+dfsg/hw/virtio/vhost.c-1086- if (r < 0) {
##############################################
qemu-5.1+dfsg/hw/virtio/vhost.c-1147-
qemu-5.1+dfsg/hw/virtio/vhost.c:1148: if (virtio_queue_get_desc_addr(vdev, idx) == 0) {
qemu-5.1+dfsg/hw/virtio/vhost.c-1149- /* Don't stop the virtqueue which might have not been started */
##############################################
qemu-5.1+dfsg/hw/virtio/vhost-user.c-1010-
qemu-5.1+dfsg/hw/virtio/vhost-user.c:1011:static int vhost_user_set_vring_addr(struct vhost_dev *dev,
qemu-5.1+dfsg/hw/virtio/vhost-user.c-1012- struct vhost_vring_addr *addr)
##############################################
qemu-5.1+dfsg/hw/virtio/vhost-vdpa.c-380-
qemu-5.1+dfsg/hw/virtio/vhost-vdpa.c:381:static int vhost_vdpa_set_vring_addr(struct vhost_dev *dev,
qemu-5.1+dfsg/hw/virtio/vhost-vdpa.c-382- struct vhost_vring_addr *addr)
##############################################
qemu-5.1+dfsg/hw/virtio/vhost-vdpa.c-427-
qemu-5.1+dfsg/hw/virtio/vhost-vdpa.c:428:static int vhost_vdpa_vq_get_addr(struct vhost_dev *dev,
qemu-5.1+dfsg/hw/virtio/vhost-vdpa.c-429- struct vhost_vring_addr *addr, struct vhost_virtqueue *vq)
##############################################
qemu-5.1+dfsg/hw/virtio/vhost-vsock-common.c-184-
qemu-5.1+dfsg/hw/virtio/vhost-vsock-common.c:185: if (virtio_queue_get_addr(vdev, 2)) {
qemu-5.1+dfsg/hw/virtio/vhost-vsock-common.c-186- /*
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c-107- subpages = rb_page_size / BALLOON_PAGE_SIZE;
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c:108: base_gpa = memory_region_get_ram_addr(mr) + mr_offset -
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c-109- (rb_offset - rb_aligned_offset);
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c-360- if (!rb) {
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c:361: trace_virtio_balloon_bad_addr(elem->in_addr[i]);
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c-362- continue;
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c-409- if (!section.mr) {
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c:410: trace_virtio_balloon_bad_addr(pa);
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c-411- continue;
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c-415- memory_region_is_romd(section.mr)) {
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c:416: trace_virtio_balloon_bad_addr(pa);
qemu-5.1+dfsg/hw/virtio/virtio-balloon.c-417- memory_region_unref(section.mr);
##############################################
qemu-5.1+dfsg/hw/virtio/virtio.c-2222-
qemu-5.1+dfsg/hw/virtio/virtio.c:2223:void virtio_queue_set_addr(VirtIODevice *vdev, int n, hwaddr addr)
qemu-5.1+dfsg/hw/virtio/virtio.c-2224-{
##############################################
qemu-5.1+dfsg/hw/virtio/virtio.c-2231-
qemu-5.1+dfsg/hw/virtio/virtio.c:2232:hwaddr virtio_queue_get_addr(VirtIODevice *vdev, int n)
qemu-5.1+dfsg/hw/virtio/virtio.c-2233-{
##############################################
qemu-5.1+dfsg/hw/virtio/virtio.c-3306-
qemu-5.1+dfsg/hw/virtio/virtio.c:3307:hwaddr virtio_queue_get_desc_addr(VirtIODevice *vdev, int n)
qemu-5.1+dfsg/hw/virtio/virtio.c-3308-{
##############################################
qemu-5.1+dfsg/hw/virtio/virtio.c-3313-{
qemu-5.1+dfsg/hw/virtio/virtio.c:3314: return virtio_queue_get_desc_addr(vdev, n) != 0;
qemu-5.1+dfsg/hw/virtio/virtio.c-3315-}
##############################################
qemu-5.1+dfsg/hw/virtio/virtio.c-3327-
qemu-5.1+dfsg/hw/virtio/virtio.c:3328:hwaddr virtio_queue_get_avail_addr(VirtIODevice *vdev, int n)
qemu-5.1+dfsg/hw/virtio/virtio.c-3329-{
##############################################
qemu-5.1+dfsg/hw/virtio/virtio.c-3332-
qemu-5.1+dfsg/hw/virtio/virtio.c:3333:hwaddr virtio_queue_get_used_addr(VirtIODevice *vdev, int n)
qemu-5.1+dfsg/hw/virtio/virtio.c-3334-{
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-mem.c-767-{
qemu-5.1+dfsg/hw/virtio/virtio-mem.c:768: void * const host = qemu_ram_get_host_addr(vmem->memdev->mr.ram_block);
qemu-5.1+dfsg/hw/virtio/virtio-mem.c-769- unsigned long first_zero_bit, last_zero_bit;
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-mem-pci.c-27-
qemu-5.1+dfsg/hw/virtio/virtio-mem-pci.c:28:static void virtio_mem_pci_set_addr(MemoryDeviceState *md, uint64_t addr,
qemu-5.1+dfsg/hw/virtio/virtio-mem-pci.c-29- Error **errp)
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-mem-pci.c-33-
qemu-5.1+dfsg/hw/virtio/virtio-mem-pci.c:34:static uint64_t virtio_mem_pci_get_addr(const MemoryDeviceState *md)
qemu-5.1+dfsg/hw/virtio/virtio-mem-pci.c-35-{
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-mmio.c-169- }
qemu-5.1+dfsg/hw/virtio/virtio-mmio.c:170: return virtio_queue_get_addr(vdev, vdev->queue_sel)
qemu-5.1+dfsg/hw/virtio/virtio-mmio.c-171- >> proxy->guest_page_shift;
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-mmio.c-339- } else {
qemu-5.1+dfsg/hw/virtio/virtio-mmio.c:340: virtio_queue_set_addr(vdev, vdev->queue_sel,
qemu-5.1+dfsg/hw/virtio/virtio-mmio.c-341- value << proxy->guest_page_shift);
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-pci.c-314- else
qemu-5.1+dfsg/hw/virtio/virtio-pci.c:315: virtio_queue_set_addr(vdev, vdev->queue_sel, pa);
qemu-5.1+dfsg/hw/virtio/virtio-pci.c-316- break;
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-pci.c-385- case VIRTIO_PCI_QUEUE_PFN:
qemu-5.1+dfsg/hw/virtio/virtio-pci.c:386: ret = virtio_queue_get_addr(vdev, vdev->queue_sel)
qemu-5.1+dfsg/hw/virtio/virtio-pci.c-387- >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-pmem-pci.c-27-
qemu-5.1+dfsg/hw/virtio/virtio-pmem-pci.c:28:static void virtio_pmem_pci_set_addr(MemoryDeviceState *md, uint64_t addr,
qemu-5.1+dfsg/hw/virtio/virtio-pmem-pci.c-29- Error **errp)
##############################################
qemu-5.1+dfsg/hw/virtio/virtio-pmem-pci.c-33-
qemu-5.1+dfsg/hw/virtio/virtio-pmem-pci.c:34:static uint64_t virtio_pmem_pci_get_addr(const MemoryDeviceState *md)
qemu-5.1+dfsg/hw/virtio/virtio-pmem-pci.c-35-{
##############################################
qemu-5.1+dfsg/hw/xen/xen_pt.c-950-static Property xen_pci_passthrough_properties[] = {
qemu-5.1+dfsg/hw/xen/xen_pt.c:951: DEFINE_PROP_PCI_HOST_DEVADDR("hostaddr", XenPCIPassthroughState, hostaddr),
qemu-5.1+dfsg/hw/xen/xen_pt.c-952- DEFINE_PROP_BOOL("permissive", XenPCIPassthroughState, permissive, false),
##############################################
qemu-5.1+dfsg/hw/xtensa/sim.c-41-
qemu-5.1+dfsg/hw/xtensa/sim.c:42:static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
qemu-5.1+dfsg/hw/xtensa/sim.c-43-{
##############################################
qemu-5.1+dfsg/hw/xtensa/xtfpga.c-189-
qemu-5.1+dfsg/hw/xtensa/xtfpga.c:190:static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
qemu-5.1+dfsg/hw/xtensa/xtfpga.c-191-{
##############################################
qemu-5.1+dfsg/include/exec/cpu-common.h-55-const char *qemu_ram_get_idstr(RAMBlock *rb);
qemu-5.1+dfsg/include/exec/cpu-common.h:56:void *qemu_ram_get_host_addr(RAMBlock *rb);
qemu-5.1+dfsg/include/exec/cpu-common.h-57-ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
##############################################
qemu-5.1+dfsg/include/exec/cpu_ldst.h-158-
qemu-5.1+dfsg/include/exec/cpu_ldst.h:159:static inline void set_helper_retaddr(uintptr_t ra)
qemu-5.1+dfsg/include/exec/cpu_ldst.h-160-{
##############################################
qemu-5.1+dfsg/include/exec/cpu_ldst.h-168-
qemu-5.1+dfsg/include/exec/cpu_ldst.h:169:static inline void clear_helper_retaddr(void)
qemu-5.1+dfsg/include/exec/cpu_ldst.h-170-{
##############################################
qemu-5.1+dfsg/include/exec/exec-all.h-504-#if defined(CONFIG_USER_ONLY)
qemu-5.1+dfsg/include/exec/exec-all.h:505:void tb_invalidate_phys_addr(target_ulong addr);
qemu-5.1+dfsg/include/exec/exec-all.h-506-void tb_invalidate_phys_range(target_ulong start, target_ulong end);
qemu-5.1+dfsg/include/exec/exec-all.h-507-#else
qemu-5.1+dfsg/include/exec/exec-all.h:508:void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
qemu-5.1+dfsg/include/exec/exec-all.h-509-#endif
##############################################
qemu-5.1+dfsg/include/exec/exec-all.h-522-# define GETPC() \
qemu-5.1+dfsg/include/exec/exec-all.h:523: ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
qemu-5.1+dfsg/include/exec/exec-all.h-524-#endif
##############################################
qemu-5.1+dfsg/include/exec/memory.h-33-#define MAX_PHYS_ADDR_SPACE_BITS 62
qemu-5.1+dfsg/include/exec/memory.h:34:#define MAX_PHYS_ADDR (((hwaddr)1 << MAX_PHYS_ADDR_SPACE_BITS) - 1)
qemu-5.1+dfsg/include/exec/memory.h-35-
##############################################
qemu-5.1+dfsg/include/exec/memory.h-1814- */
qemu-5.1+dfsg/include/exec/memory.h:1815:ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr);
qemu-5.1+dfsg/include/exec/memory.h-1816-
##############################################
qemu-5.1+dfsg/include/hw/core/cpu.h-191- bool probe, uintptr_t retaddr);
qemu-5.1+dfsg/include/hw/core/cpu.h:192: hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
qemu-5.1+dfsg/include/hw/core/cpu.h:193: hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
qemu-5.1+dfsg/include/hw/core/cpu.h-194- MemTxAttrs *attrs);
##############################################
qemu-5.1+dfsg/include/hw/core/cpu.h-218- void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
qemu-5.1+dfsg/include/hw/core/cpu.h:219: vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
qemu-5.1+dfsg/include/hw/core/cpu.h-220- void (*tcg_initialize)(void);
##############################################
qemu-5.1+dfsg/include/hw/loader-fit.h-31- const struct fit_loader_match *matches;
qemu-5.1+dfsg/include/hw/loader-fit.h:32: hwaddr (*addr_to_phys)(void *opaque, uint64_t addr);
qemu-5.1+dfsg/include/hw/loader-fit.h-33- const void *(*fdt_filter)(void *opaque, const void *fdt,
##############################################
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-dramc.h-32-/** Highest register address used by DRAMCOM module */
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-dramc.h:33:#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-dramc.h-34-
##############################################
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-dramc.h-39-/** Highest register address used by DRAMCTL module */
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-dramc.h:40:#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-dramc.h-41-
##############################################
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-dramc.h-46-/** Highest register address used by DRAMPHY module */
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-dramc.h:47:#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-dramc.h-48-
##############################################
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-sysctrl.h-31-/** Highest register address used by System Control device */
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-sysctrl.h:32:#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
qemu-5.1+dfsg/include/hw/misc/allwinner-h3-sysctrl.h-33-
##############################################
qemu-5.1+dfsg/include/hw/pci/pci.h-367-void pci_unregister_vga(PCIDevice *pci_dev);
qemu-5.1+dfsg/include/hw/pci/pci.h:368:pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
qemu-5.1+dfsg/include/hw/pci/pci.h-369-
##############################################
qemu-5.1+dfsg/include/hw/platform-bus.h-51- int n);
qemu-5.1+dfsg/include/hw/platform-bus.h:52:hwaddr platform_bus_get_mmio_addr(PlatformBusDevice *pbus, SysBusDevice *sbdev,
qemu-5.1+dfsg/include/hw/platform-bus.h-53- int n);
##############################################
qemu-5.1+dfsg/include/hw/ppc/ppc.h-105-#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
qemu-5.1+dfsg/include/hw/ppc/ppc.h:106:#define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08)
qemu-5.1+dfsg/include/hw/ppc/ppc.h-107-#define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09)
##############################################
qemu-5.1+dfsg/include/hw/ppc/spapr.h-938-void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
qemu-5.1+dfsg/include/hw/ppc/spapr.h:939:hwaddr spapr_get_rtas_addr(void);
qemu-5.1+dfsg/include/hw/ppc/spapr.h-940-#endif /* HW_SPAPR_H */
##############################################
qemu-5.1+dfsg/include/hw/ppc/xive_regs.h-239-
qemu-5.1+dfsg/include/hw/ppc/xive_regs.h:240:static inline uint64_t xive_end_qaddr(XiveEND *end)
qemu-5.1+dfsg/include/hw/ppc/xive_regs.h-241-{
##############################################
qemu-5.1+dfsg/include/hw/qdev-dma.h-12-
qemu-5.1+dfsg/include/hw/qdev-dma.h:13:#define DEFINE_PROP_DMAADDR(_n, _s, _f, _d) \
qemu-5.1+dfsg/include/hw/qdev-dma.h-14- DEFINE_PROP_UINT64(_n, _s, _f, _d)
##############################################
qemu-5.1+dfsg/include/hw/qdev-properties.h-185- DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *)
qemu-5.1+dfsg/include/hw/qdev-properties.h:186:#define DEFINE_PROP_MACADDR(_n, _s, _f) \
qemu-5.1+dfsg/include/hw/qdev-properties.h-187- DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
##############################################
qemu-5.1+dfsg/include/hw/qdev-properties.h-206- DEFINE_PROP_UNSIGNED(_n, _s, _f, 0, qdev_prop_blocksize, uint32_t)
qemu-5.1+dfsg/include/hw/qdev-properties.h:207:#define DEFINE_PROP_PCI_HOST_DEVADDR(_n, _s, _f) \
qemu-5.1+dfsg/include/hw/qdev-properties.h-208- DEFINE_PROP(_n, _s, _f, qdev_prop_pci_host_devaddr, PCIHostDeviceAddress)
##############################################
qemu-5.1+dfsg/include/hw/qdev-properties.h-259- BlockBackend *value);
qemu-5.1+dfsg/include/hw/qdev-properties.h:260:void qdev_prop_set_macaddr(DeviceState *dev, const char *name,
qemu-5.1+dfsg/include/hw/qdev-properties.h-261- const uint8_t *value);
##############################################
qemu-5.1+dfsg/include/hw/rtc/allwinner-rtc.h-31-/** Highest register address used by RTC device */
qemu-5.1+dfsg/include/hw/rtc/allwinner-rtc.h:32:#define AW_RTC_REGS_MAXADDR (0x200)
qemu-5.1+dfsg/include/hw/rtc/allwinner-rtc.h-33-
##############################################
qemu-5.1+dfsg/include/hw/s390x/css.h-186-
qemu-5.1+dfsg/include/hw/s390x/css.h:187:#define VMSTATE_PTR_TO_IND_ADDR(_f, _s) \
qemu-5.1+dfsg/include/hw/s390x/css.h-188- VMSTATE_STRUCT(_f, _s, 1, vmstate_ind_addr, IndAddr*)
##############################################
qemu-5.1+dfsg/include/hw/sh4/sh.h-7-
qemu-5.1+dfsg/include/hw/sh4/sh.h:8:#define A7ADDR(x) ((x) & 0x1fffffff)
qemu-5.1+dfsg/include/hw/sh4/sh.h:9:#define P4ADDR(x) ((x) | 0xe0000000)
qemu-5.1+dfsg/include/hw/sh4/sh.h-10-
##############################################
qemu-5.1+dfsg/include/hw/usb/dwc2-regs.h-455-#define DCFG_DEVADDR_LIMIT 0x7f
qemu-5.1+dfsg/include/hw/usb/dwc2-regs.h:456:#define DCFG_DEVADDR(_x) ((_x) << 4)
qemu-5.1+dfsg/include/hw/usb/dwc2-regs.h-457-#define DCFG_NZ_STS_OUT_HSHK BIT(2)
##############################################
qemu-5.1+dfsg/include/hw/virtio/virtio.h-254- uint32_t addr, uint32_t data);
qemu-5.1+dfsg/include/hw/virtio/virtio.h:255:void virtio_queue_set_addr(VirtIODevice *vdev, int n, hwaddr addr);
qemu-5.1+dfsg/include/hw/virtio/virtio.h:256:hwaddr virtio_queue_get_addr(VirtIODevice *vdev, int n);
qemu-5.1+dfsg/include/hw/virtio/virtio.h-257-void virtio_queue_set_num(VirtIODevice *vdev, int n, int num);
##############################################
qemu-5.1+dfsg/include/hw/virtio/virtio.h-296-
qemu-5.1+dfsg/include/hw/virtio/virtio.h:297:hwaddr virtio_queue_get_desc_addr(VirtIODevice *vdev, int n);
qemu-5.1+dfsg/include/hw/virtio/virtio.h-298-bool virtio_queue_enabled_legacy(VirtIODevice *vdev, int n);
qemu-5.1+dfsg/include/hw/virtio/virtio.h-299-bool virtio_queue_enabled(VirtIODevice *vdev, int n);
qemu-5.1+dfsg/include/hw/virtio/virtio.h:300:hwaddr virtio_queue_get_avail_addr(VirtIODevice *vdev, int n);
qemu-5.1+dfsg/include/hw/virtio/virtio.h:301:hwaddr virtio_queue_get_used_addr(VirtIODevice *vdev, int n);
qemu-5.1+dfsg/include/hw/virtio/virtio.h-302-hwaddr virtio_queue_get_desc_size(VirtIODevice *vdev, int n);
##############################################
qemu-5.1+dfsg/include/net/eth.h-260-
qemu-5.1+dfsg/include/net/eth.h:261:static inline int is_multicast_ether_addr(const uint8_t *addr)
qemu-5.1+dfsg/include/net/eth.h-262-{
##############################################
qemu-5.1+dfsg/include/net/eth.h-265-
qemu-5.1+dfsg/include/net/eth.h:266:static inline int is_broadcast_ether_addr(const uint8_t *addr)
qemu-5.1+dfsg/include/net/eth.h-267-{
##############################################
qemu-5.1+dfsg/include/net/eth.h-270-
qemu-5.1+dfsg/include/net/eth.h:271:static inline int is_unicast_ether_addr(const uint8_t *addr)
qemu-5.1+dfsg/include/net/eth.h-272-{
qemu-5.1+dfsg/include/net/eth.h:273: return !is_multicast_ether_addr(addr);
qemu-5.1+dfsg/include/net/eth.h-274-}
##############################################
qemu-5.1+dfsg/include/net/eth.h-284-{
qemu-5.1+dfsg/include/net/eth.h:285: if (is_broadcast_ether_addr(ehdr->h_dest)) {
qemu-5.1+dfsg/include/net/eth.h-286- return ETH_PKT_BCAST;
qemu-5.1+dfsg/include/net/eth.h:287: } else if (is_multicast_ether_addr(ehdr->h_dest)) {
qemu-5.1+dfsg/include/net/eth.h-288- return ETH_PKT_MCAST;
##############################################
qemu-5.1+dfsg/include/net/net.h-37-#define DEFINE_NIC_PROPERTIES(_state, _conf) \
qemu-5.1+dfsg/include/net/net.h:38: DEFINE_PROP_MACADDR("mac", _state, _conf.macaddr), \
qemu-5.1+dfsg/include/net/net.h-39- DEFINE_PROP_NETDEV("netdev", _state, _conf.peers)
##############################################
qemu-5.1+dfsg/include/net/net.h-223-
qemu-5.1+dfsg/include/net/net.h:224:#define vmstate_offset_macaddr(_state, _field) \
qemu-5.1+dfsg/include/net/net.h-225- vmstate_offset_array(_state, _field.a, uint8_t, \
##############################################
qemu-5.1+dfsg/include/net/net.h-227-
qemu-5.1+dfsg/include/net/net.h:228:#define VMSTATE_MACADDR(_field, _state) { \
qemu-5.1+dfsg/include/net/net.h-229- .name = (stringify(_field)), \
##############################################
qemu-5.1+dfsg/include/net/net.h-232- .flags = VMS_BUFFER, \
qemu-5.1+dfsg/include/net/net.h:233: .offset = vmstate_offset_macaddr(_state, _field), \
qemu-5.1+dfsg/include/net/net.h-234-}
##############################################
qemu-5.1+dfsg/include/qemu/atomic.h-18-/* Compiler barrier */
qemu-5.1+dfsg/include/qemu/atomic.h:19:#define barrier() ({ asm volatile("" ::: "memory"); (void)0; })
qemu-5.1+dfsg/include/qemu/atomic.h-20-
##############################################
qemu-5.1+dfsg/include/qemu/atomic.h-85-#elif defined(__alpha__)
qemu-5.1+dfsg/include/qemu/atomic.h:86:#define smp_read_barrier_depends() asm volatile("mb":::"memory")
qemu-5.1+dfsg/include/qemu/atomic.h-87-#else
##############################################
qemu-5.1+dfsg/include/qemu/atomic.h-247-#if defined __x86_64__
qemu-5.1+dfsg/include/qemu/atomic.h:248:#define smp_mb() ({ asm volatile("mfence" ::: "memory"); (void)0; })
qemu-5.1+dfsg/include/qemu/atomic.h-249-#else
qemu-5.1+dfsg/include/qemu/atomic.h:250:#define smp_mb() ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; })
qemu-5.1+dfsg/include/qemu/atomic.h-251-#endif
##############################################
qemu-5.1+dfsg/include/qemu/atomic.h-256-#ifdef __alpha__
qemu-5.1+dfsg/include/qemu/atomic.h:257:#define smp_read_barrier_depends() asm volatile("mb":::"memory")
qemu-5.1+dfsg/include/qemu/atomic.h-258-#endif
##############################################
qemu-5.1+dfsg/include/qemu/atomic.h-286- */
qemu-5.1+dfsg/include/qemu/atomic.h:287:#define smp_wmb() ({ asm volatile("eieio" ::: "memory"); (void)0; })
qemu-5.1+dfsg/include/qemu/atomic.h-288-#if defined(__powerpc64__)
qemu-5.1+dfsg/include/qemu/atomic.h:289:#define smp_mb_release() ({ asm volatile("lwsync" ::: "memory"); (void)0; })
qemu-5.1+dfsg/include/qemu/atomic.h:290:#define smp_mb_acquire() ({ asm volatile("lwsync" ::: "memory"); (void)0; })
qemu-5.1+dfsg/include/qemu/atomic.h-291-#else
qemu-5.1+dfsg/include/qemu/atomic.h:292:#define smp_mb_release() ({ asm volatile("sync" ::: "memory"); (void)0; })
qemu-5.1+dfsg/include/qemu/atomic.h:293:#define smp_mb_acquire() ({ asm volatile("sync" ::: "memory"); (void)0; })
qemu-5.1+dfsg/include/qemu/atomic.h-294-#endif
qemu-5.1+dfsg/include/qemu/atomic.h:295:#define smp_mb() ({ asm volatile("sync" ::: "memory"); (void)0; })
qemu-5.1+dfsg/include/qemu/atomic.h-296-
##############################################
qemu-5.1+dfsg/include/qemu/log.h-46-
qemu-5.1+dfsg/include/qemu/log.h:47:#define CPU_LOG_TB_OUT_ASM (1 << 0)
qemu-5.1+dfsg/include/qemu/log.h:48:#define CPU_LOG_TB_IN_ASM (1 << 1)
qemu-5.1+dfsg/include/qemu/log.h-49-#define CPU_LOG_TB_OP (1 << 2)
##############################################
qemu-5.1+dfsg/include/qemu/log.h-130- */
qemu-5.1+dfsg/include/qemu/log.h:131:#define qemu_log_mask_and_addr(MASK, ADDR, FMT, ...) \
qemu-5.1+dfsg/include/qemu/log.h-132- do { \
##############################################
qemu-5.1+dfsg/include/qemu/processor.h-12-#if defined(__i386__) || defined(__x86_64__)
qemu-5.1+dfsg/include/qemu/processor.h:13:# define cpu_relax() asm volatile("rep; nop" ::: "memory")
qemu-5.1+dfsg/include/qemu/processor.h-14-
qemu-5.1+dfsg/include/qemu/processor.h-15-#elif defined(__aarch64__)
qemu-5.1+dfsg/include/qemu/processor.h:16:# define cpu_relax() asm volatile("yield" ::: "memory")
qemu-5.1+dfsg/include/qemu/processor.h-17-
##############################################
qemu-5.1+dfsg/include/qemu/processor.h-19-/* set Hardware Multi-Threading (HMT) priority to low; then back to medium */
qemu-5.1+dfsg/include/qemu/processor.h:20:# define cpu_relax() asm volatile("or 1, 1, 1;" \
qemu-5.1+dfsg/include/qemu/processor.h-21- "or 2, 2, 2;" ::: "memory")
##############################################
qemu-5.1+dfsg/include/qemu/qemu-plugin.h-286-
qemu-5.1+dfsg/include/qemu/qemu-plugin.h:287:uint64_t qemu_plugin_tb_vaddr(const struct qemu_plugin_tb *tb);
qemu-5.1+dfsg/include/qemu/qemu-plugin.h-288-
##############################################
qemu-5.1+dfsg/include/qemu/qemu-plugin.h-295-
qemu-5.1+dfsg/include/qemu/qemu-plugin.h:296:uint64_t qemu_plugin_insn_vaddr(const struct qemu_plugin_insn *insn);
qemu-5.1+dfsg/include/qemu/qemu-plugin.h:297:void *qemu_plugin_insn_haddr(const struct qemu_plugin_insn *insn);
qemu-5.1+dfsg/include/qemu/qemu-plugin.h-298-
##############################################
qemu-5.1+dfsg/include/qemu/qemu-plugin.h-315-/*
qemu-5.1+dfsg/include/qemu/qemu-plugin.h:316: * qemu_plugin_get_hwaddr():
qemu-5.1+dfsg/include/qemu/qemu-plugin.h-317- * @vaddr: the virtual address of the memory operation
##############################################
qemu-5.1+dfsg/include/qemu/qemu-plugin.h-326- */
qemu-5.1+dfsg/include/qemu/qemu-plugin.h:327:struct qemu_plugin_hwaddr *qemu_plugin_get_hwaddr(qemu_plugin_meminfo_t info,
qemu-5.1+dfsg/include/qemu/qemu-plugin.h-328- uint64_t vaddr);
##############################################
qemu-5.1+dfsg/include/qemu/sockets.h-35-int inet_connect(const char *str, Error **errp);
qemu-5.1+dfsg/include/qemu/sockets.h:36:int inet_connect_saddr(InetSocketAddress *saddr, Error **errp);
qemu-5.1+dfsg/include/qemu/sockets.h-37-
##############################################
qemu-5.1+dfsg/include/qemu/timer.h-893- int64_t val;
qemu-5.1+dfsg/include/qemu/timer.h:894: asm volatile ("rdtsc" : "=A" (val));
qemu-5.1+dfsg/include/qemu/timer.h-895- return val;
##############################################
qemu-5.1+dfsg/include/qemu/timer.h-903- int64_t val;
qemu-5.1+dfsg/include/qemu/timer.h:904: asm volatile("rdtsc" : "=a" (low), "=d" (high));
qemu-5.1+dfsg/include/qemu/timer.h-905- val = high;
##############################################
qemu-5.1+dfsg/include/qemu/timer.h-915- int val;
qemu-5.1+dfsg/include/qemu/timer.h:916: asm volatile ("mfctl %%cr16, %0" : "=r"(val));
qemu-5.1+dfsg/include/qemu/timer.h-917- return val;
##############################################
qemu-5.1+dfsg/include/qemu/timer.h-924- int64_t val;
qemu-5.1+dfsg/include/qemu/timer.h:925: asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
qemu-5.1+dfsg/include/qemu/timer.h-926- return val;
##############################################
qemu-5.1+dfsg/include/qemu/timer.h-934- uint64_t rval;
qemu-5.1+dfsg/include/qemu/timer.h:935: asm volatile("rd %%tick,%0" : "=r"(rval));
qemu-5.1+dfsg/include/qemu/timer.h-936- return rval;
##############################################
qemu-5.1+dfsg/include/qemu/timer.h-946- } rval;
qemu-5.1+dfsg/include/qemu/timer.h:947: asm volatile("rd %%tick,%%g1; srlx %%g1,32,%0; mov %%g1,%1"
qemu-5.1+dfsg/include/qemu/timer.h-948- : "=r"(rval.i32.high), "=r"(rval.i32.low) : : "g1");
##############################################
qemu-5.1+dfsg/include/qemu/timer.h-989-
qemu-5.1+dfsg/include/qemu/timer.h:990: asm volatile("rpcc %0" : "=r"(cc));
qemu-5.1+dfsg/include/qemu/timer.h-991- cur = cc;
##############################################
qemu-5.1+dfsg/include/sysemu/xen-mapcache.h-13-
qemu-5.1+dfsg/include/sysemu/xen-mapcache.h:14:typedef hwaddr (*phys_offset_to_gaddr_t)(hwaddr phys_offset,
qemu-5.1+dfsg/include/sysemu/xen-mapcache.h-15- ram_addr_t size);
##############################################
qemu-5.1+dfsg/linux-headers/asm-powerpc/kvm.h-555-/* For SLB & DTL, address in high (first) half, length in low half */
qemu-5.1+dfsg/linux-headers/asm-powerpc/kvm.h:556:#define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82)
qemu-5.1+dfsg/linux-headers/asm-powerpc/kvm.h-557-#define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83)
##############################################
qemu-5.1+dfsg/linux-headers/linux/kvm.h-1411-/* store status for s390 */
qemu-5.1+dfsg/linux-headers/linux/kvm.h:1412:#define KVM_S390_STORE_STATUS_NOADDR (-1ul)
qemu-5.1+dfsg/linux-headers/linux/kvm.h-1413-#define KVM_S390_STORE_STATUS_PREFIXED (-2ul)
##############################################
qemu-5.1+dfsg/linux-user/alpha/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/alpha/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/alpha/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/arm/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/arm/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/arm/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/fd-trans.c-1288-
qemu-5.1+dfsg/linux-user/fd-trans.c:1289:static abi_long packet_target_to_host_sockaddr(void *host_addr,
qemu-5.1+dfsg/linux-user/fd-trans.c-1290- abi_ulong target_addr,
##############################################
qemu-5.1+dfsg/linux-user/fd-trans.h-46-
qemu-5.1+dfsg/linux-user/fd-trans.h:47:static inline TargetFdAddrFunc fd_trans_target_to_host_addr(int fd)
qemu-5.1+dfsg/linux-user/fd-trans.h-48-{
##############################################
qemu-5.1+dfsg/linux-user/flatload.c-635- continue;
qemu-5.1+dfsg/linux-user/flatload.c:636: addr = flat_get_relocate_addr(relval);
qemu-5.1+dfsg/linux-user/flatload.c-637- rp = calc_reloc(addr, libinfo, id, 1);
##############################################
qemu-5.1+dfsg/linux-user/hppa/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/hppa/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/hppa/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/i386/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/i386/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/i386/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/m68k/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/m68k/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/m68k/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/microblaze/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/microblaze/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/microblaze/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/mips64/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/mips64/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/mips64/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/mips/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/mips/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/mips/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/ppc/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/ppc/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/ppc/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/s390x/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/s390x/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/s390x/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/sh4/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/sh4/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/sh4/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/sparc64/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/sparc64/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/sparc64/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/sparc/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/sparc/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/sparc/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/strace.c-64-UNUSED static void print_buf(abi_long addr, abi_long len, int last);
qemu-5.1+dfsg/linux-user/strace.c:65:UNUSED static void print_raw_param(const char *, abi_long, int);
qemu-5.1+dfsg/linux-user/strace.c-66-UNUSED static void print_timeval(abi_ulong, int);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-69-UNUSED static void print_signal(abi_ulong, int);
qemu-5.1+dfsg/linux-user/strace.c:70:UNUSED static void print_sockaddr(abi_ulong, abi_long, int);
qemu-5.1+dfsg/linux-user/strace.c-71-UNUSED static void print_socket_domain(int domain);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-150- if (signal_name == NULL) {
qemu-5.1+dfsg/linux-user/strace.c:151: print_raw_param("%ld", arg, last);
qemu-5.1+dfsg/linux-user/strace.c-152- return;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-338-static void
qemu-5.1+dfsg/linux-user/strace.c:339:print_sockaddr(abi_ulong addr, abi_long addrlen, int last)
qemu-5.1+dfsg/linux-user/strace.c-340-{
##############################################
qemu-5.1+dfsg/linux-user/strace.c-365- ntohs(in->sin_port));
qemu-5.1+dfsg/linux-user/strace.c:366: qemu_log("sin_addr=inet_addr(\"%d.%d.%d.%d\")",
qemu-5.1+dfsg/linux-user/strace.c-367- c[0], c[1], c[2], c[3]);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-418- } else {
qemu-5.1+dfsg/linux-user/strace.c:419: print_raw_param("0x"TARGET_ABI_FMT_lx, addr, 0);
qemu-5.1+dfsg/linux-user/strace.c-420- }
##############################################
qemu-5.1+dfsg/linux-user/strace.c-743-static void
qemu-5.1+dfsg/linux-user/strace.c:744:print_syscall_ret_addr(const struct syscallname *name, abi_long ret,
qemu-5.1+dfsg/linux-user/strace.c-745- abi_long arg0, abi_long arg1, abi_long arg2,
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1427- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:1428: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-1429- print_pointer(arg1, 0);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1516- print_string(arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:1517: print_raw_param("%d", arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:1518: print_raw_param("%d", arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-1519- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1542- print_flags(clone_flags, flags, 0);
qemu-5.1+dfsg/linux-user/strace.c:1543: print_raw_param("child_stack=0x" TARGET_ABI_FMT_lx, newsp, 0);
qemu-5.1+dfsg/linux-user/strace.c:1544: print_raw_param("parent_tidptr=0x" TARGET_ABI_FMT_lx, parent_tidptr, 0);
qemu-5.1+dfsg/linux-user/strace.c:1545: print_raw_param("tls=0x" TARGET_ABI_FMT_lx, newtls, 0);
qemu-5.1+dfsg/linux-user/strace.c:1546: print_raw_param("child_tidptr=0x" TARGET_ABI_FMT_lx, child_tidptr, 1);
qemu-5.1+dfsg/linux-user/strace.c-1547-}
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1588- print_string(arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:1589: print_raw_param("0x" TARGET_ABI_FMT_lx, arg1, 1);
qemu-5.1+dfsg/linux-user/strace.c-1590- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1615- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:1616: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-1617- print_flags(falloc_flags, arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c-1618-#if TARGET_ABI_BITS == 32
qemu-5.1+dfsg/linux-user/strace.c:1619: print_raw_param("%" PRIu64, target_offset64(arg2, arg3), 0);
qemu-5.1+dfsg/linux-user/strace.c:1620: print_raw_param("%" PRIu64, target_offset64(arg4, arg5), 1);
qemu-5.1+dfsg/linux-user/strace.c-1621-#else
qemu-5.1+dfsg/linux-user/strace.c:1622: print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c:1623: print_raw_param(TARGET_ABI_FMT_ld, arg3, 1);
qemu-5.1+dfsg/linux-user/strace.c-1624-#endif
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1652- print_string(arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:1653: print_raw_param("%d", arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c:1654: print_raw_param("%d", arg3, 0);
qemu-5.1+dfsg/linux-user/strace.c-1655- print_flags(at_file_flags, arg4, 1);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1666- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:1667: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-1668- switch(arg1) {
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1670- qemu_log("F_DUPFD,");
qemu-5.1+dfsg/linux-user/strace.c:1671: print_raw_param(TARGET_ABI_FMT_ld, arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-1672- break;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1677- qemu_log("F_SETFD,");
qemu-5.1+dfsg/linux-user/strace.c:1678: print_raw_param(TARGET_ABI_FMT_ld, arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-1679- break;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1703- qemu_log("F_SETOWN,");
qemu-5.1+dfsg/linux-user/strace.c:1704: print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c-1705- break;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1710- qemu_log("F_SETSIG,");
qemu-5.1+dfsg/linux-user/strace.c:1711: print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c-1712- break;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1728- qemu_log("F_SETLEASE,");
qemu-5.1+dfsg/linux-user/strace.c:1729: print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c-1730- break;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1735- qemu_log("F_SETPIPE_SZ,");
qemu-5.1+dfsg/linux-user/strace.c:1736: print_raw_param(TARGET_ABI_FMT_ld, arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-1737- break;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1742- qemu_log("F_DUPFD_CLOEXEC,");
qemu-5.1+dfsg/linux-user/strace.c:1743: print_raw_param(TARGET_ABI_FMT_ld, arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-1744- break;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1746- qemu_log("F_NOTIFY,");
qemu-5.1+dfsg/linux-user/strace.c:1747: print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c-1748- break;
qemu-5.1+dfsg/linux-user/strace.c-1749- default:
qemu-5.1+dfsg/linux-user/strace.c:1750: print_raw_param(TARGET_ABI_FMT_ld, arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c-1751- print_pointer(arg2, 1);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1765- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:1766: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-1767- print_string(arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c-1768- print_pointer(arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c:1769: print_raw_param(TARGET_FMT_lu, arg3, 1);
qemu-5.1+dfsg/linux-user/strace.c-1770- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1780- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:1781: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-1782- print_pointer(arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:1783: print_raw_param(TARGET_FMT_lu, arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-1784- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1797- print_pointer(arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c:1798: print_raw_param(TARGET_FMT_lu, arg3, 1);
qemu-5.1+dfsg/linux-user/strace.c-1799- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1812- print_pointer(arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:1813: print_raw_param(TARGET_FMT_lu, arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-1814- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1825- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:1826: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-1827- print_string(arg1, 1);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1910- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:1911: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:1912: print_raw_param("%ld", arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:1913: print_raw_param("%ld", arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c-1914- print_pointer(arg3, 0);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1931- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:1932: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:1933: print_raw_param(TARGET_ABI_FMT_ld, arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c-1934- switch (arg2) {
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1949- default:
qemu-5.1+dfsg/linux-user/strace.c:1950: print_raw_param("%#x", arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-1951- }
##############################################
qemu-5.1+dfsg/linux-user/strace.c-1982-{
qemu-5.1+dfsg/linux-user/strace.c:1983: print_raw_param(TARGET_ABI_FMT_ld, sockfd, last);
qemu-5.1+dfsg/linux-user/strace.c-1984-}
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2012-
qemu-5.1+dfsg/linux-user/strace.c:2013:static void do_print_sockaddr(const char *name, abi_long arg1)
qemu-5.1+dfsg/linux-user/strace.c-2014-{
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2022- print_sockfd(sockfd, 0);
qemu-5.1+dfsg/linux-user/strace.c:2023: print_sockaddr(addr, addrlen, 0);
qemu-5.1+dfsg/linux-user/strace.c-2024- qemu_log(")");
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2035- print_sockfd(sockfd, 0);
qemu-5.1+dfsg/linux-user/strace.c:2036: print_raw_param(TARGET_ABI_FMT_ld, backlog, 1);
qemu-5.1+dfsg/linux-user/strace.c-2037- qemu_log(")");
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2055- qemu_log(",");
qemu-5.1+dfsg/linux-user/strace.c:2056: print_raw_param(TARGET_ABI_FMT_lx, tab, 1);
qemu-5.1+dfsg/linux-user/strace.c-2057- qemu_log(")");
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2071- print_buf(msg, len, 0);
qemu-5.1+dfsg/linux-user/strace.c:2072: print_raw_param(TARGET_ABI_FMT_ld, len, 0);
qemu-5.1+dfsg/linux-user/strace.c-2073- print_flags(msg_flags, flags, 1);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2076-
qemu-5.1+dfsg/linux-user/strace.c:2077:static void do_print_msgaddr(const char *name, abi_long arg1)
qemu-5.1+dfsg/linux-user/strace.c-2078-{
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2090- print_buf(msg, len, 0);
qemu-5.1+dfsg/linux-user/strace.c:2091: print_raw_param(TARGET_ABI_FMT_ld, len, 0);
qemu-5.1+dfsg/linux-user/strace.c-2092- print_flags(msg_flags, flags, 0);
qemu-5.1+dfsg/linux-user/strace.c:2093: print_sockaddr(addr, addrlen, 0);
qemu-5.1+dfsg/linux-user/strace.c-2094- qemu_log(")");
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2116- default:
qemu-5.1+dfsg/linux-user/strace.c:2117: print_raw_param(TARGET_ABI_FMT_ld, how, 1);
qemu-5.1+dfsg/linux-user/strace.c-2118- break;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2152- qemu_log("SOL_TCP,");
qemu-5.1+dfsg/linux-user/strace.c:2153: print_raw_param(TARGET_ABI_FMT_ld, optname, 0);
qemu-5.1+dfsg/linux-user/strace.c-2154- print_pointer(optval, 0);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2157- qemu_log("SOL_IP,");
qemu-5.1+dfsg/linux-user/strace.c:2158: print_raw_param(TARGET_ABI_FMT_ld, optname, 0);
qemu-5.1+dfsg/linux-user/strace.c-2159- print_pointer(optval, 0);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2162- qemu_log("SOL_RAW,");
qemu-5.1+dfsg/linux-user/strace.c:2163: print_raw_param(TARGET_ABI_FMT_ld, optname, 0);
qemu-5.1+dfsg/linux-user/strace.c-2164- print_pointer(optval, 0);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2261- default:
qemu-5.1+dfsg/linux-user/strace.c:2262: print_raw_param(TARGET_ABI_FMT_ld, optname, 0);
qemu-5.1+dfsg/linux-user/strace.c-2263- print_pointer(optval, 0);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2267- default:
qemu-5.1+dfsg/linux-user/strace.c:2268: print_raw_param(TARGET_ABI_FMT_ld, level, 0);
qemu-5.1+dfsg/linux-user/strace.c:2269: print_raw_param(TARGET_ABI_FMT_ld, optname, 0);
qemu-5.1+dfsg/linux-user/strace.c-2270- print_pointer(optval, 0);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2272- }
qemu-5.1+dfsg/linux-user/strace.c:2273: print_raw_param(TARGET_ABI_FMT_ld, optlen, 1);
qemu-5.1+dfsg/linux-user/strace.c-2274- qemu_log(")");
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2315- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:2316: print_raw_param(TARGET_ABI_FMT_ld, arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:2317: print_raw_param(TARGET_ABI_FMT_ld, arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:2318: print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c:2319: print_raw_param(TARGET_ABI_FMT_ld, arg3, 0);
qemu-5.1+dfsg/linux-user/strace.c:2320: print_raw_param(TARGET_ABI_FMT_ld, arg4, 0);
qemu-5.1+dfsg/linux-user/strace.c:2321: print_raw_param(TARGET_ABI_FMT_ld, arg5, 0);
qemu-5.1+dfsg/linux-user/strace.c-2322- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2333- print_sockfd(arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:2334: print_sockaddr(arg1, arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-2335- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2362- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:2363: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-2364- print_pointer(arg1, 1);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2452- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:2453: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-2454- print_signal(arg1, 0);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2477- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:2478: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:2479: print_raw_param("%d", arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c-2480- print_signal(arg2, 0);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2545- default: {
qemu-5.1+dfsg/linux-user/strace.c:2546: print_raw_param("%ld", arg, last);
qemu-5.1+dfsg/linux-user/strace.c-2547- return;
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2560- print_pointer(arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:2561: print_raw_param("%d", arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-2562- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2577- if (hasdev) {
qemu-5.1+dfsg/linux-user/strace.c:2578: print_raw_param("makedev(%d", major(arg2), 0);
qemu-5.1+dfsg/linux-user/strace.c:2579: print_raw_param("%d)", minor(arg2), 1);
qemu-5.1+dfsg/linux-user/strace.c-2580- }
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2597- if (hasdev) {
qemu-5.1+dfsg/linux-user/strace.c:2598: print_raw_param("makedev(%d", major(arg3), 0);
qemu-5.1+dfsg/linux-user/strace.c:2599: print_raw_param("%d)", minor(arg3), 1);
qemu-5.1+dfsg/linux-user/strace.c-2600- }
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2695- print_pointer(arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:2696: print_raw_param("%u", arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-2697- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2710- print_pointer(arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c:2711: print_raw_param("%u", arg3, 1);
qemu-5.1+dfsg/linux-user/strace.c-2712- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2912- print_pointer(arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:2913: print_raw_param("%d", arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c-2914- print_flags(mmap_prot_flags, arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c-2915- print_flags(mmap_flags, arg3, 0);
qemu-5.1+dfsg/linux-user/strace.c:2916: print_raw_param("%d", arg4, 0);
qemu-5.1+dfsg/linux-user/strace.c:2917: print_raw_param("%#x", arg5, 1);
qemu-5.1+dfsg/linux-user/strace.c-2918- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2930- print_pointer(arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:2931: print_raw_param("%d", arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c-2932- print_flags(mmap_prot_flags, arg2, 1);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2944- print_pointer(arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:2945: print_raw_param("%d", arg1, 1);
qemu-5.1+dfsg/linux-user/strace.c-2946- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-2998- print_futex_op(arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:2999: print_raw_param(",%d", arg2, 0);
qemu-5.1+dfsg/linux-user/strace.c-3000- print_pointer(arg3, 0); /* struct timespec */
qemu-5.1+dfsg/linux-user/strace.c-3001- print_pointer(arg4, 0);
qemu-5.1+dfsg/linux-user/strace.c:3002: print_raw_param("%d", arg4, 1);
qemu-5.1+dfsg/linux-user/strace.c-3003- print_syscall_epilogue(name);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-3013- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:3014: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-3015- print_signal(arg1, 1);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-3026- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:3027: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-3028- print_signal(arg1, 1);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-3039- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:3040: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c:3041: print_raw_param("%d", arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c-3042- print_signal(arg2, 1);
##############################################
qemu-5.1+dfsg/linux-user/strace.c-3069- print_syscall_prologue(name);
qemu-5.1+dfsg/linux-user/strace.c:3070: print_raw_param("%d", arg0, 0);
qemu-5.1+dfsg/linux-user/strace.c-3071-
##############################################
qemu-5.1+dfsg/linux-user/strace.c-3083- if (ie->target_cmd == 0) {
qemu-5.1+dfsg/linux-user/strace.c:3084: print_raw_param("%#x", arg1, 0);
qemu-5.1+dfsg/linux-user/strace.c:3085: print_raw_param("%#x", arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-3086- } else {
##############################################
qemu-5.1+dfsg/linux-user/strace.c-3099- case TYPE_INT:
qemu-5.1+dfsg/linux-user/strace.c:3100: print_raw_param("%d", arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-3101- break;
qemu-5.1+dfsg/linux-user/strace.c-3102- case TYPE_LONG:
qemu-5.1+dfsg/linux-user/strace.c:3103: print_raw_param(TARGET_ABI_FMT_ld, arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-3104- break;
qemu-5.1+dfsg/linux-user/strace.c-3105- case TYPE_ULONG:
qemu-5.1+dfsg/linux-user/strace.c:3106: print_raw_param(TARGET_ABI_FMT_lu, arg2, 1);
qemu-5.1+dfsg/linux-user/strace.c-3107- break;
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-1514-
qemu-5.1+dfsg/linux-user/syscall.c:1515:static inline abi_long target_to_host_sockaddr(int fd, struct sockaddr *addr,
qemu-5.1+dfsg/linux-user/syscall.c-1516- abi_ulong target_addr,
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-1522-
qemu-5.1+dfsg/linux-user/syscall.c:1523: if (fd_trans_target_to_host_addr(fd)) {
qemu-5.1+dfsg/linux-user/syscall.c:1524: return fd_trans_target_to_host_addr(fd)(addr, target_addr, len);
qemu-5.1+dfsg/linux-user/syscall.c-1525- }
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-1571-
qemu-5.1+dfsg/linux-user/syscall.c:1572:static inline abi_long host_to_target_sockaddr(abi_ulong target_addr,
qemu-5.1+dfsg/linux-user/syscall.c-1573- struct sockaddr *addr,
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-1849- __put_user(errh->ee.ee_data, &target_errh->ee.ee_data);
qemu-5.1+dfsg/linux-user/syscall.c:1850: host_to_target_sockaddr((unsigned long) &target_errh->offender,
qemu-5.1+dfsg/linux-user/syscall.c-1851- (void *) &errh->offender, sizeof(errh->offender));
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-1893- __put_user(errh->ee.ee_data, &target_errh->ee.ee_data);
qemu-5.1+dfsg/linux-user/syscall.c:1894: host_to_target_sockaddr((unsigned long) &target_errh->offender,
qemu-5.1+dfsg/linux-user/syscall.c-1895- (void *) &errh->offender, sizeof(errh->offender));
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-3041-
qemu-5.1+dfsg/linux-user/syscall.c:3042: ret = target_to_host_sockaddr(sockfd, addr, target_addr, addrlen);
qemu-5.1+dfsg/linux-user/syscall.c-3043- if (ret)
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-3061-
qemu-5.1+dfsg/linux-user/syscall.c:3062: ret = target_to_host_sockaddr(sockfd, addr, target_addr, addrlen);
qemu-5.1+dfsg/linux-user/syscall.c-3063- if (ret)
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-3081- msg.msg_name = alloca(msg.msg_namelen+1);
qemu-5.1+dfsg/linux-user/syscall.c:3082: ret = target_to_host_sockaddr(fd, msg.msg_name,
qemu-5.1+dfsg/linux-user/syscall.c-3083- tswapal(msgp->msg_name),
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-3157- if (msg.msg_name != NULL && msg.msg_name != (void *)-1) {
qemu-5.1+dfsg/linux-user/syscall.c:3158: ret = host_to_target_sockaddr(tswapal(msgp->msg_name),
qemu-5.1+dfsg/linux-user/syscall.c-3159- msg.msg_name, msg.msg_namelen);
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-3270- if (!is_error(ret)) {
qemu-5.1+dfsg/linux-user/syscall.c:3271: host_to_target_sockaddr(target_addr, addr, MIN(addrlen, ret_addrlen));
qemu-5.1+dfsg/linux-user/syscall.c-3272- if (put_user_u32(ret_addrlen, target_addrlen_addr)) {
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-3301- if (!is_error(ret)) {
qemu-5.1+dfsg/linux-user/syscall.c:3302: host_to_target_sockaddr(target_addr, addr, MIN(addrlen, ret_addrlen));
qemu-5.1+dfsg/linux-user/syscall.c-3303- if (put_user_u32(ret_addrlen, target_addrlen_addr)) {
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-3332- if (!is_error(ret)) {
qemu-5.1+dfsg/linux-user/syscall.c:3333: host_to_target_sockaddr(target_addr, addr, MIN(addrlen, ret_addrlen));
qemu-5.1+dfsg/linux-user/syscall.c-3334- if (put_user_u32(ret_addrlen, target_addrlen_addr)) {
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-3385- addr = alloca(addrlen+1);
qemu-5.1+dfsg/linux-user/syscall.c:3386: ret = target_to_host_sockaddr(fd, addr, target_addr, addrlen);
qemu-5.1+dfsg/linux-user/syscall.c-3387- if (ret) {
##############################################
qemu-5.1+dfsg/linux-user/syscall.c-3443- if (target_addr) {
qemu-5.1+dfsg/linux-user/syscall.c:3444: host_to_target_sockaddr(target_addr, addr,
qemu-5.1+dfsg/linux-user/syscall.c-3445- MIN(addrlen, ret_addrlen));
##############################################
qemu-5.1+dfsg/linux-user/target_flat.h-10-#define flat_old_ram_flag(flag) (flag)
qemu-5.1+dfsg/linux-user/target_flat.h:11:#define flat_get_relocate_addr(relval) (relval)
qemu-5.1+dfsg/linux-user/target_flat.h-12-#define flat_get_addr_from_rp(rp, relval, flags, persistent) (rp)
##############################################
qemu-5.1+dfsg/linux-user/x86_64/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/x86_64/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/x86_64/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/xtensa/syscallhdr.sh-5-out="$2"
qemu-5.1+dfsg/linux-user/xtensa/syscallhdr.sh:6:my_abis=`echo "($3)" | tr ',' '|'`
qemu-5.1+dfsg/linux-user/xtensa/syscallhdr.sh-7-prefix="$4"
##############################################
qemu-5.1+dfsg/linux-user/xtensa/target_flat.h-6-#define flat_old_ram_flag(flag) (flag)
qemu-5.1+dfsg/linux-user/xtensa/target_flat.h:7:#define flat_get_relocate_addr(relval) (relval)
qemu-5.1+dfsg/linux-user/xtensa/target_flat.h-8-#define flat_get_addr_from_rp(rp, relval, flags, persistent) (rp)
##############################################
qemu-5.1+dfsg/memory_ldst.inc.c-285- dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
qemu-5.1+dfsg/memory_ldst.inc.c:286: cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
qemu-5.1+dfsg/memory_ldst.inc.c-287- 4, dirty_log_mask);
##############################################
qemu-5.1+dfsg/migration/page_cache.c-121-
qemu-5.1+dfsg/migration/page_cache.c:122:static CacheItem *cache_get_by_addr(const PageCache *cache, uint64_t addr)
qemu-5.1+dfsg/migration/page_cache.c-123-{
##############################################
qemu-5.1+dfsg/migration/page_cache.c-135-{
qemu-5.1+dfsg/migration/page_cache.c:136: return cache_get_by_addr(cache, addr)->it_data;
qemu-5.1+dfsg/migration/page_cache.c-137-}
##############################################
qemu-5.1+dfsg/migration/page_cache.c-143-
qemu-5.1+dfsg/migration/page_cache.c:144: it = cache_get_by_addr(cache, addr);
qemu-5.1+dfsg/migration/page_cache.c-145-
##############################################
qemu-5.1+dfsg/migration/page_cache.c-160- /* actual update of entry */
qemu-5.1+dfsg/migration/page_cache.c:161: it = cache_get_by_addr(cache, addr);
qemu-5.1+dfsg/migration/page_cache.c-162-
##############################################
qemu-5.1+dfsg/migration/postcopy-ram.c-452- const char *block_name = qemu_ram_get_idstr(rb);
qemu-5.1+dfsg/migration/postcopy-ram.c:453: void *host_addr = qemu_ram_get_host_addr(rb);
qemu-5.1+dfsg/migration/postcopy-ram.c-454- ram_addr_t offset = qemu_ram_get_offset(rb);
##############################################
qemu-5.1+dfsg/migration/postcopy-ram.c-477- const char *block_name = qemu_ram_get_idstr(rb);
qemu-5.1+dfsg/migration/postcopy-ram.c:478: void *host_addr = qemu_ram_get_host_addr(rb);
qemu-5.1+dfsg/migration/postcopy-ram.c-479- ram_addr_t offset = qemu_ram_get_offset(rb);
##############################################
qemu-5.1+dfsg/migration/postcopy-ram.c-583- const char *block_name = qemu_ram_get_idstr(rb);
qemu-5.1+dfsg/migration/postcopy-ram.c:584: void *host_addr = qemu_ram_get_host_addr(rb);
qemu-5.1+dfsg/migration/postcopy-ram.c-585- ram_addr_t offset = qemu_ram_get_offset(rb);
##############################################
qemu-5.1+dfsg/migration/postcopy-ram.c-628-
qemu-5.1+dfsg/migration/postcopy-ram.c:629: reg_struct.range.start = (uintptr_t)qemu_ram_get_host_addr(rb);
qemu-5.1+dfsg/migration/postcopy-ram.c-630- reg_struct.range.len = qemu_ram_get_used_length(rb);
##############################################
qemu-5.1+dfsg/migration/rdma.c-631- const char *block_name = qemu_ram_get_idstr(rb);
qemu-5.1+dfsg/migration/rdma.c:632: void *host_addr = qemu_ram_get_host_addr(rb);
qemu-5.1+dfsg/migration/rdma.c-633- ram_addr_t block_offset = qemu_ram_get_offset(rb);
##############################################
qemu-5.1+dfsg/migration/rdma.c-976-
qemu-5.1+dfsg/migration/rdma.c:977: ret = rdma_resolve_addr(rdma->cm_id, NULL, e->ai_dst_addr,
qemu-5.1+dfsg/migration/rdma.c-978- RDMA_RESOLVE_TIMEOUT_MS);
##############################################
qemu-5.1+dfsg/migration/rdma.c-2583- trace_qemu_rdma_dest_init_trying(rdma->host, ip);
qemu-5.1+dfsg/migration/rdma.c:2584: ret = rdma_bind_addr(listen_id, e->ai_dst_addr);
qemu-5.1+dfsg/migration/rdma.c-2585- if (ret) {
##############################################
qemu-5.1+dfsg/net/eth.c-402-static bool
qemu-5.1+dfsg/net/eth.c:403:_eth_get_rss_ex_dst_addr(const struct iovec *pkt, int pkt_frags,
qemu-5.1+dfsg/net/eth.c-404- size_t rthdr_offset,
##############################################
qemu-5.1+dfsg/net/eth.c-431-static bool
qemu-5.1+dfsg/net/eth.c:432:_eth_get_rss_ex_src_addr(const struct iovec *pkt, int pkt_frags,
qemu-5.1+dfsg/net/eth.c-433- size_t dsthdr_offset,
##############################################
qemu-5.1+dfsg/net/eth.c-531- info->rss_ex_dst_valid =
qemu-5.1+dfsg/net/eth.c:532: _eth_get_rss_ex_dst_addr(pkt, pkt_frags,
qemu-5.1+dfsg/net/eth.c-533- ip6hdr_off + info->full_hdr_len,
##############################################
qemu-5.1+dfsg/net/eth.c-536- info->rss_ex_src_valid =
qemu-5.1+dfsg/net/eth.c:537: _eth_get_rss_ex_src_addr(pkt, pkt_frags,
qemu-5.1+dfsg/net/eth.c-538- ip6hdr_off + info->full_hdr_len,
##############################################
qemu-5.1+dfsg/net/net.c-916- if (nic->has_macaddr &&
qemu-5.1+dfsg/net/net.c:917: net_parse_macaddr(nd->macaddr.a, nic->macaddr) < 0) {
qemu-5.1+dfsg/net/net.c-918- error_setg(errp, "invalid syntax for ethernet address");
##############################################
qemu-5.1+dfsg/net/net.c-921- if (nic->has_macaddr &&
qemu-5.1+dfsg/net/net.c:922: is_multicast_ether_addr(nd->macaddr.a)) {
qemu-5.1+dfsg/net/net.c-923- error_setg(errp,
##############################################
qemu-5.1+dfsg/net/net.c-1460- if (mac) {
qemu-5.1+dfsg/net/net.c:1461: ret = net_parse_macaddr(ni->macaddr.a, mac);
qemu-5.1+dfsg/net/net.c-1462- g_free(mac);
##############################################
qemu-5.1+dfsg/net/net.c-1466- }
qemu-5.1+dfsg/net/net.c:1467: if (is_multicast_ether_addr(ni->macaddr.a)) {
qemu-5.1+dfsg/net/net.c-1468- error_setg(errp, "NIC cannot have multicast MAC address");
##############################################
qemu-5.1+dfsg/net/util.c-27-
qemu-5.1+dfsg/net/util.c:28:int net_parse_macaddr(uint8_t *macaddr, const char *p)
qemu-5.1+dfsg/net/util.c-29-{
##############################################
qemu-5.1+dfsg/net/util.h-83-
qemu-5.1+dfsg/net/util.h:84:int net_parse_macaddr(uint8_t *macaddr, const char *p);
qemu-5.1+dfsg/net/util.h-85-
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c-61-/*
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c:62: * The includes of C headers must be after the asm block to avoid compiler
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c-63- * errors.
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c-97-/* Return top of memory using BIOS function E801. */
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c:98:static uint32_t get_e801_addr(void)
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c-99-{
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c-133-
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c:134:/* Force the asm name without leading underscore, even on Win32. */
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c-135-extern void load_kernel(void) asm("load_kernel");
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c-172- */
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c:173: initrd_addr = (void *)((get_e801_addr() - initrd_size) & -4096);
qemu-5.1+dfsg/pc-bios/optionrom/linuxboot_dma.c-174- writel_es(0x218, (uint32_t)initrd_addr);
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/Makefile-23-# Attempt to work around compilers that lack -m16 (GCC <= 4.8, clang <= ??)
qemu-5.1+dfsg/pc-bios/optionrom/Makefile:24:# On GCC we add -fno-toplevel-reorder to keep the order of asm blocks with
qemu-5.1+dfsg/pc-bios/optionrom/Makefile-25-# respect to the rest of the code. clang does not have -fno-toplevel-reorder,
qemu-5.1+dfsg/pc-bios/optionrom/Makefile:26:# but it places all asm blocks at the beginning and we're relying on it for
qemu-5.1+dfsg/pc-bios/optionrom/Makefile-27-# the option ROM header. So just force clang not to use the integrated
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-39-{
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h:40: asm volatile("outb %0, %w1" : : "a"(value), "Nd"(port));
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-41-}
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-44-{
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h:45: asm volatile("outw %0, %w1" : : "a"(value), "Nd"(port));
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-46-}
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-49-{
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h:50: asm volatile("outl %0, %w1" : : "a"(value), "Nd"(port));
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-51-}
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-56-
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h:57: asm volatile("inb %w1, %0" : "=a"(value) : "Nd"(port));
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-58- return value;
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-64-
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h:65: asm volatile("inw %w1, %0" : "=a"(value) : "Nd"(port));
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-66- return value;
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-72-
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h:73: asm volatile("inl %w1, %0" : "=a"(value) : "Nd"(port));
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-74- return value;
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-78-{
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h:79: asm volatile("rep insb %%dx, %%es:(%%edi)"
qemu-5.1+dfsg/pc-bios/optionrom/optrom.h-80- : "+c"(len), "+D"(buf) : "d"(port) : "memory");
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/pvh_main.c-21-
qemu-5.1+dfsg/pc-bios/optionrom/pvh_main.c:22:asm (".code32"); /* this code will be executed in protected mode */
qemu-5.1+dfsg/pc-bios/optionrom/pvh_main.c-23-
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/pvh_main.c-68-
qemu-5.1+dfsg/pc-bios/optionrom/pvh_main.c:69:/* Force the asm name without leading underscore, even on Win32. */
qemu-5.1+dfsg/pc-bios/optionrom/pvh_main.c-70-extern void pvh_load_kernel(void) asm("pvh_load_kernel");
##############################################
qemu-5.1+dfsg/pc-bios/optionrom/pvh_main.c-131-
qemu-5.1+dfsg/pc-bios/optionrom/pvh_main.c:132: asm volatile("jmp *%1" : : "b"(&start_info), "c"(kernel_entry));
qemu-5.1+dfsg/pc-bios/optionrom/pvh_main.c-133-}
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-376-{
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:377: register struct subchannel_id reg1 asm ("1") = schid;
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-378- int ccode = -EIO;
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-379-
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:380: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-381- " stsch 0(%3)\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-392-{
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:393: register struct subchannel_id reg1 asm ("1") = schid;
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-394- int ccode;
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-395-
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:396: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-397- " msch 0(%2)\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-407-{
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:408: register struct subchannel_id reg1 asm ("1") = schid;
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-409- int ccode = -EIO;
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-410-
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:411: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-412- " msch 0(%2)\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-423-{
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:424: register struct subchannel_id reg1 asm ("1") = schid;
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-425- int ccode;
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-426-
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:427: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-428- " tsch 0(%3)\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-441-
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:442: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-443- " ssch 0(%2)\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-457-
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:458: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-459- " csch\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-471-
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:472: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-473- " tpi 0(%2)\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-486-
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h:487: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/cio.h-488- " .insn rre,0xb25f0000,%2,0\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/dasd-ipl.c-143-
qemu-5.1+dfsg/pc-bios/s390-ccw/dasd-ipl.c:144:static uint32_t read_ipl2_addr(void)
qemu-5.1+dfsg/pc-bios/s390-ccw/dasd-ipl.c-145-{
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/dasd-ipl.c-214- run_readipl(schid, cutype);
qemu-5.1+dfsg/pc-bios/s390-ccw/dasd-ipl.c:215: ipl2_addr = read_ipl2_addr();
qemu-5.1+dfsg/pc-bios/s390-ccw/dasd-ipl.c-216- check_ipl1();
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/helper.h-33-{
qemu-5.1+dfsg/pc-bios/s390-ccw/helper.h:34: asm volatile ("diag 0,0,0x44"
qemu-5.1+dfsg/pc-bios/s390-ccw/helper.h-35- : :
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/iplb.h-107-
qemu-5.1+dfsg/pc-bios/s390-ccw/iplb.h:108: asm volatile ("diag %0,%2,0x308\n"
qemu-5.1+dfsg/pc-bios/s390-ccw/iplb.h-109- : "+d" (addr), "+d" (rc)
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/jump2ipl.c-66- */
qemu-5.1+dfsg/pc-bios/s390-ccw/jump2ipl.c:67: asm volatile("lghi 1,1\n\t"
qemu-5.1+dfsg/pc-bios/s390-ccw/jump2ipl.c-68- "diag 1,1,0x308\n\t"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/menu.c-37-
qemu-5.1+dfsg/pc-bios/s390-ccw/menu.c:38: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/menu.c-39- "stctg 0,0,%0\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/menu.c-49-
qemu-5.1+dfsg/pc-bios/s390-ccw/menu.c:50: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/menu.c-51- "stctg 0,0,%0\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/menu.c-59-{
qemu-5.1+dfsg/pc-bios/s390-ccw/menu.c:60: asm volatile("sckc %0" : : "Q" (time));
qemu-5.1+dfsg/pc-bios/s390-ccw/menu.c-61-}
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/netmain.c-45-
qemu-5.1+dfsg/pc-bios/s390-ccw/netmain.c:46:#define KERNEL_ADDR ((void *)0L)
qemu-5.1+dfsg/pc-bios/s390-ccw/netmain.c-47-#define KERNEL_MAX_SIZE ((long)_start)
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/netmain.c-127-
qemu-5.1+dfsg/pc-bios/s390-ccw/netmain.c:128: asm volatile(" stck %0 " : : "Q"(seed) : "memory");
qemu-5.1+dfsg/pc-bios/s390-ccw/netmain.c-129- seed ^= (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/netmain.c-256- r1 = 2;
qemu-5.1+dfsg/pc-bios/s390-ccw/netmain.c:257: asm volatile(" stsi 0(%[addr])\n"
qemu-5.1+dfsg/pc-bios/s390-ccw/netmain.c-258- " ipm %[cc]\n"
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-arch.h-99-{
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-arch.h:100: asm volatile("spx %0" : : "m" (address) : "memory");
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-arch.h-101-}
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-arch.h-106-
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-arch.h:107: asm volatile("stpx %0" : "=m" (address));
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-arch.h-108- return address;
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-ccw.h-133-
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-ccw.h:134:static inline void debug_print_addr(const char *desc, void *p)
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-ccw.h-135-{
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-time.h-7-
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-time.h:8: asm volatile("stck %0" : "=Q" (r) : : "cc");
qemu-5.1+dfsg/pc-bios/s390-ccw/s390-time.h-9- return r;
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/sclp.c-34-
qemu-5.1+dfsg/pc-bios/s390-ccw/sclp.c:35: asm volatile(
qemu-5.1+dfsg/pc-bios/s390-ccw/sclp.c-36- " .insn rre,0xb2200000,%1,%2\n" /* servc %1,%2 */
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/virtio.c-56-
qemu-5.1+dfsg/pc-bios/s390-ccw/virtio.c:57: asm volatile ("diag 2,4,0x500"
qemu-5.1+dfsg/pc-bios/s390-ccw/virtio.c-58- : "=d" (retval)
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/virtio.c-112-
qemu-5.1+dfsg/pc-bios/s390-ccw/virtio.c:113: debug_print_addr("init p", p);
qemu-5.1+dfsg/pc-bios/s390-ccw/virtio.c-114- vr->id = info->index;
##############################################
qemu-5.1+dfsg/pc-bios/s390-ccw/virtio.c-131-
qemu-5.1+dfsg/pc-bios/s390-ccw/virtio.c:132: debug_print_addr("init vr", vr);
qemu-5.1+dfsg/pc-bios/s390-ccw/virtio.c-133-}
##############################################
qemu-5.1+dfsg/plugins/api.c-175-
qemu-5.1+dfsg/plugins/api.c:176:uint64_t qemu_plugin_tb_vaddr(const struct qemu_plugin_tb *tb)
qemu-5.1+dfsg/plugins/api.c-177-{
##############################################
qemu-5.1+dfsg/plugins/api.c-206-
qemu-5.1+dfsg/plugins/api.c:207:uint64_t qemu_plugin_insn_vaddr(const struct qemu_plugin_insn *insn)
qemu-5.1+dfsg/plugins/api.c-208-{
##############################################
qemu-5.1+dfsg/plugins/api.c-211-
qemu-5.1+dfsg/plugins/api.c:212:void *qemu_plugin_insn_haddr(const struct qemu_plugin_insn *insn)
qemu-5.1+dfsg/plugins/api.c-213-{
##############################################
qemu-5.1+dfsg/plugins/api.c-254-
qemu-5.1+dfsg/plugins/api.c:255:struct qemu_plugin_hwaddr *qemu_plugin_get_hwaddr(qemu_plugin_meminfo_t info,
qemu-5.1+dfsg/plugins/api.c-256- uint64_t vaddr)
##############################################
qemu-5.1+dfsg/plugins/api.c-270-#else
qemu-5.1+dfsg/plugins/api.c:271:struct qemu_plugin_hwaddr *qemu_plugin_get_hwaddr(qemu_plugin_meminfo_t info,
qemu-5.1+dfsg/plugins/api.c-272- uint64_t vaddr)
##############################################
qemu-5.1+dfsg/qemu-options.hx-2936- a model. Optionally, the MAC address can be changed to mac, the
qemu-5.1+dfsg/qemu-options.hx:2937: device address set to addr (PCI cards only), and a name can be
qemu-5.1+dfsg/qemu-options.hx-2938- assigned for use in monitor commands. Optionally, for PCI cards, you
##############################################
qemu-5.1+dfsg/roms/openbios/arch/amd64/context.c-142- __context = ctx;
qemu-5.1+dfsg/roms/openbios/arch/amd64/context.c:143: asm ("pushl %cs; call __switch_context");
qemu-5.1+dfsg/roms/openbios/arch/amd64/context.c-144- ret = __context;
##############################################
qemu-5.1+dfsg/roms/openbios/arch/amd64/multiboot.h-95-
qemu-5.1+dfsg/roms/openbios/arch/amd64/multiboot.h:96:#endif /* ! ASM */
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/briq/methods.c-144- /* This seems to be the correct thing to do - but I'm not sure */
qemu-5.1+dfsg/roms/openbios/arch/ppc/briq/methods.c:145: asm volatile("mfmsr %0" : "=r" (msr) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/briq/methods.c-146- msr &= ~(MSR_IR | MSR_DR);
qemu-5.1+dfsg/roms/openbios/arch/ppc/briq/methods.c:147: asm volatile("mtmsr %0" :: "r" (msr) );
qemu-5.1+dfsg/roms/openbios/arch/ppc/briq/methods.c-148-#endif
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/briq/methods.c-159-
qemu-5.1+dfsg/roms/openbios/arch/ppc/briq/methods.c:160: asm volatile("mftb %0" : "=r" (t) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/briq/methods.c-161- if( mticks )
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/Makefile-10-INCLUDES = -I../../kernel -I../../kernel/include \
qemu-5.1+dfsg/roms/openbios/arch/ppc/Makefile:11: -I../../include/molasm -I$(ODIR)/include
qemu-5.1+dfsg/roms/openbios/arch/ppc/Makefile-12-
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/Makefile.asm-2-#
qemu-5.1+dfsg/roms/openbios/arch/ppc/Makefile.asm:3:# Makefile.asm - assembly support
qemu-5.1+dfsg/roms/openbios/arch/ppc/Makefile.asm-4-#
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/Makefile.asm-12-#################################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/Makefile.asm:13:# Rules for asm targets
qemu-5.1+dfsg/roms/openbios/arch/ppc/Makefile.asm-14-#################################################
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/mol/methods.c-275- /* This seems to be the correct thing to do - but I'm not sure */
qemu-5.1+dfsg/roms/openbios/arch/ppc/mol/methods.c:276: asm volatile("mfmsr %0" : "=r" (msr) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/mol/methods.c-277- msr &= ~(MSR_IR | MSR_DR);
qemu-5.1+dfsg/roms/openbios/arch/ppc/mol/methods.c:278: asm volatile("mtmsr %0" :: "r" (msr) );
qemu-5.1+dfsg/roms/openbios/arch/ppc/mol/methods.c-279-#endif
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/mol/methods.c-292-
qemu-5.1+dfsg/roms/openbios/arch/ppc/mol/methods.c:293: asm volatile("mftb %0" : "=r" (t) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/mol/methods.c-294- if( mticks )
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-236-
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c:237: asm volatile( "tlbie %0" :: "r"(ea) );
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-238-}
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-246-
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c:247: asm volatile("mfdar %0" : "=r" (dar) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c:248: asm volatile("mfdsisr %0" : "=r" (dsisr) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-249-
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-262-
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c:263: asm volatile("mfsrr0 %0" : "=r" (nip) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c:264: asm volatile("mfsrr1 %0" : "=r" (srr1) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-265-
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-284-
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c:285: asm volatile("mtsdr1 %0" :: "r" (sdr1) );
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-286- for( i=0; i<16; i++ ) {
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-287- int j = i << 28;
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c:288: asm volatile("mtsrin %0,%1" :: "r" (sr_base + i), "r" (j) );
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-289- }
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c:290: asm volatile("mfmsr %0" : "=r" (msr) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-291- msr |= MSR_IR | MSR_DR;
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c:292: asm volatile("mtmsr %0" :: "r" (msr) );
qemu-5.1+dfsg/roms/openbios/arch/ppc/ofmem.c-293-}
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/osi_calls.h-63-#define _oc_tail \
qemu-5.1+dfsg/roms/openbios/arch/ppc/osi_calls.h:64: asm volatile ( "" : : : "memory" ); \
qemu-5.1+dfsg/roms/openbios/arch/ppc/osi_calls.h-65- _ret = __oc_r3; \
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/osi_calls.h-412-static inline _osi_call0_w2( int, OSI_Enet2GetHWAddr__, OSI_ENET2_GET_HWADDR, unsigned long *, retbuf );
qemu-5.1+dfsg/roms/openbios/arch/ppc/osi_calls.h:413:static inline int OSI_Enet2GetHWAddr( unsigned char *addr ) {
qemu-5.1+dfsg/roms/openbios/arch/ppc/osi_calls.h-414- int ret;
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/pearpc/methods.c-140- /* This seems to be the correct thing to do - but I'm not sure */
qemu-5.1+dfsg/roms/openbios/arch/ppc/pearpc/methods.c:141: asm volatile("mfmsr %0" : "=r" (msr) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/pearpc/methods.c-142- msr &= ~(MSR_IR | MSR_DR);
qemu-5.1+dfsg/roms/openbios/arch/ppc/pearpc/methods.c:143: asm volatile("mtmsr %0" :: "r" (msr) );
qemu-5.1+dfsg/roms/openbios/arch/ppc/pearpc/methods.c-144-#endif
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/pearpc/methods.c-155-
qemu-5.1+dfsg/roms/openbios/arch/ppc/pearpc/methods.c:156: asm volatile("mftb %0" : "=r" (t) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/pearpc/methods.c-157- if( mticks )
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/context.c-279-
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/context.c:280: asm __volatile__ ("mflr %%r9\n\t"
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/context.c-281- "stw %%r9, %0\n\t"
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c-247-static void
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c:248:push_physaddr(phys_addr_t value)
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c-249-{
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c-405- // Invalidate the cache lines
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c:406: asm ("icbi 0, %0" : : "r"(dsi));
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c:407: asm ("icbi 0, %0" : : "r"(isi));
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c-408-}
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c-1001-
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c:1002: push_physaddr(0);
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/init.c-1003- fword("encode-phys");
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/methods.c-121- /* This seems to be the correct thing to do - but I'm not sure */
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/methods.c:122: asm volatile("mfmsr %0" : "=r" (msr) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/methods.c-123- msr &= ~(MSR_IR | MSR_DR);
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/methods.c:124: asm volatile("mtmsr %0" :: "r" (msr) );
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/methods.c-125-#endif
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/methods.c-136-
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/methods.c:137: asm volatile(
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/methods.c-138- "1:\n"
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-149-
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:150:int ofmem_arch_encode_physaddr(ucell *p, phys_addr_t value)
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-151-{
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-181- transentry[i++] = t->size;
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:182: i += ofmem_arch_encode_physaddr(&transentry[i], t->phys);
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-183- transentry[i++] = t->mode;
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-201- if (ph == s_phandle_memory) {
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:202: i += ofmem_arch_encode_physaddr(availentry, start);
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-203- } else {
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-384-
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:385: asm volatile("tlbie %0" :: "r"(ea));
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-386-}
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-424-
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:425: asm volatile("tlbie %0" :: "r"(ea));
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-426-#endif
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-456-
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:457: asm volatile("mfdar %0" : "=r" (dar) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:458: asm volatile("mfdsisr %0" : "=r" (dsisr) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-459-
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-470-
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:471: asm volatile("mfsrr0 %0" : "=r" (nip) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:472: asm volatile("mfsrr1 %0" : "=r" (srr1) : );
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-473-
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-550- int j = i << 28;
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c:551: asm volatile("mtsrin %0,%1" :: "r" (sr_base + i), "r" (j));
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/ofmem.c-552- }
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/start.S-6- *
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/start.S:7: * Asm glue for ELF images
qemu-5.1+dfsg/roms/openbios/arch/ppc/qemu/start.S-8- *
##############################################
qemu-5.1+dfsg/roms/openbios/arch/ppc/start.S-6- *
qemu-5.1+dfsg/roms/openbios/arch/ppc/start.S:7: * Asm glue for ELF images run inside MOL
qemu-5.1+dfsg/roms/openbios/arch/ppc/start.S-8- *
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc32/context.c-115- __context = ctx;
qemu-5.1+dfsg/roms/openbios/arch/sparc32/context.c:116: asm __volatile__ ("\n\tcall __switch_context"
qemu-5.1+dfsg/roms/openbios/arch/sparc32/context.c-117- "\n\tnop" ::: "g1", "g2", "g3", "g4", "g5", "g6", "g7",
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c-290-/* ( -- addr ) */
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c:291:static void ignore_dfault_addr(void)
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c-292-{
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c-321- for (i = 0; i < c; i++) {
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c:322: ofmem_arch_encode_physaddr(&memreg[i * 3], simm_size * i); /* physical base */
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c-323- memreg[i * 3 + 2] = simm_size; /* size */
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c-337- virtreg = malloc(6 * sizeof(ucell));
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c:338: ofmem_arch_encode_physaddr(virtreg, 0);
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c-339- virtreg[2] = virtregsize;
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c:340: ofmem_arch_encode_physaddr(&virtreg[3], virtregsize);
qemu-5.1+dfsg/roms/openbios/arch/sparc32/lib.c-341- virtreg[5] = virtregsize;
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc32/multiboot.h-95-
qemu-5.1+dfsg/roms/openbios/arch/sparc32/multiboot.h:96:#endif /* ! ASM */
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc32/ofmem_sparc32.c-89-
qemu-5.1+dfsg/roms/openbios/arch/sparc32/ofmem_sparc32.c:90:int ofmem_arch_encode_physaddr(ucell *p, phys_addr_t value)
qemu-5.1+dfsg/roms/openbios/arch/sparc32/ofmem_sparc32.c-91-{
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc32/ofmem_sparc32.c-132-
qemu-5.1+dfsg/roms/openbios/arch/sparc32/ofmem_sparc32.c:133: i += ofmem_arch_encode_physaddr(availentry, start);
qemu-5.1+dfsg/roms/openbios/arch/sparc32/ofmem_sparc32.c-134- availentry[i] = size;
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc64/context.c-132- __context = ctx;
qemu-5.1+dfsg/roms/openbios/arch/sparc64/context.c:133: //asm ("pushl %cs; call __switch_context");
qemu-5.1+dfsg/roms/openbios/arch/sparc64/context.c:134: asm ("call __switch_context; nop");
qemu-5.1+dfsg/roms/openbios/arch/sparc64/context.c-135- ret = __context;
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc64/multiboot.h-95-
qemu-5.1+dfsg/roms/openbios/arch/sparc64/multiboot.h:96:#endif /* ! ASM */
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc64/ofmem_sparc64.c-120- if (ph == s_phandle_memory) {
qemu-5.1+dfsg/roms/openbios/arch/sparc64/ofmem_sparc64.c:121: i += ofmem_arch_encode_physaddr(availentry, start);
qemu-5.1+dfsg/roms/openbios/arch/sparc64/ofmem_sparc64.c-122- } else {
##############################################
qemu-5.1+dfsg/roms/openbios/arch/sparc64/ofmem_sparc64.c-199-
qemu-5.1+dfsg/roms/openbios/arch/sparc64/ofmem_sparc64.c:200:int ofmem_arch_encode_physaddr(ucell *p, phys_addr_t value)
qemu-5.1+dfsg/roms/openbios/arch/sparc64/ofmem_sparc64.c-201-{
##############################################
qemu-5.1+dfsg/roms/openbios/arch/x86/context.c-148- __context = ctx;
qemu-5.1+dfsg/roms/openbios/arch/x86/context.c:149: asm ("pushl %cs; call __switch_context");
qemu-5.1+dfsg/roms/openbios/arch/x86/context.c-150- ret = __context;
##############################################
qemu-5.1+dfsg/roms/openbios/arch/x86/multiboot.h-95-
qemu-5.1+dfsg/roms/openbios/arch/x86/multiboot.h:96:#endif /* ! ASM */
##############################################
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-136-{
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch:137: option=`echo $1 | tr a-z A-Z`
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-138- echo "<option name=\"$option\" type=\"boolean\" value=\"true\" />"
##############################################
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-146-
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch:147:SRCDIR=`dirname "$0"`/../..
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-148-BUILDDIR=`pwd`
##############################################
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-150-# make source path absolute
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch:151:SRCDIR=`cd "$SRCDIR"; pwd`
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-152-
##############################################
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-156-
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch:157:VERSION=`head $SRCDIR/VERSION`
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-158-
##############################################
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-175- echo "\"cross-\" prefix is no longer needed"
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch:176: target=`echo $target | sed s/cross-//g`
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-177- target_list="$target_list builtin-$target"
##############################################
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-187-for target in $target_list; do
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch:188: arch=`echo $target | sed s/.*-//g`
qemu-5.1+dfsg/roms/openbios/config/scripts/switch-arch-189- if ! test -f $SRCDIR/config/examples/${arch}_config.xml; then
##############################################
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-424- arch/amd64/.arch-ids/Makefile.id arch/amd64/Makefile
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch:425: arch/amd64/Makefile.asm arch/ia64/.arch-ids/Makefile.asm.id
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-426- arch/ia64/.arch-ids/Makefile.id arch/ia64/Makefile
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch:427: arch/ia64/Makefile.asm arch/ppc/mol/.arch-ids/video.c.id
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-428- arch/ppc/mol/video.c arch/x86/.arch-ids/Makefile.asm.id
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-429- arch/x86/.arch-ids/Makefile.id arch/x86/Makefile
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch:430: arch/x86/Makefile.asm autogen.sh config/.arch-ids/=id
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-431- config/.arch-ids/Makefile.defs.in.id
##############################################
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-952- arch/amd64/.arch-ids/sys_info.c.id arch/amd64/Kconfig
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch:953: arch/amd64/Makefile arch/amd64/Makefile.asm arch/amd64/boot.c
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-954- arch/amd64/builtin.c arch/amd64/console.c arch/amd64/context.c
##############################################
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-967- arch/ia64/.arch-ids/init.fs.id arch/ia64/Kconfig
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch:968: arch/ia64/Makefile arch/ia64/Makefile.asm arch/ia64/defconfig
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-969- arch/ia64/init.fs arch/ppc/.arch-ids/=id
##############################################
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-1091- arch/x86/.arch-ids/sys_info.c.id arch/x86/Kconfig
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch:1092: arch/x86/Makefile arch/x86/Makefile.asm arch/x86/boot.c
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-1093- arch/x86/boot.h arch/x86/builtin.c arch/x86/console.c
##############################################
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-1696- arch/ia64/defconfig arch/ia64/init.fs arch/ppc/Kconfig
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch:1697: arch/ppc/Makefile arch/ppc/Makefile.asm arch/ppc/briq/briq.c
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-1698- arch/ppc/briq/briq.fs arch/ppc/briq/briq.h
##############################################
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-1731- arch/unix/unix.c arch/x86/Kconfig arch/x86/Makefile
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch:1732: arch/x86/Makefile.asm arch/x86/boot.c arch/x86/boot.h
qemu-5.1+dfsg/roms/openbios/Documentation/ChangeLog.arch-1733- arch/x86/builtin.c arch/x86/console.c arch/x86/context.c
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-76-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:77:static inline int pci_encode_phys_addr(u32 *phys, int flags, int space_code,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-78- pci_addr dev, uint8_t reg, uint64_t addr)
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-105-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:106:static int host_encode_phys_addr(u32 *prop, ucell addr)
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-107-{
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-141-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:142:static unsigned long pci_bus_addr_to_host_addr(int space, uint32_t ba)
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-143-{
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-153-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:154:static inline void pci_decode_pci_addr(pci_addr addr, int *flags,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-155- int *space_code, uint32_t *mask)
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-374-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:375: pci_decode_pci_addr(ba, &flags, &space_code, &mask);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-376-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:377: phys = pci_bus_addr_to_host_addr(space_code,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-378- ba & ~mask);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-561-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:562: ncells += pci_encode_phys_addr(props + ncells, 0, range.type,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-563- 0, 0, range.parentaddr);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:564: ncells += host_encode_phys_addr(props + ncells, range.childaddr);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-565- ncells += pci_encode_size(props + ncells, range.len);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-658- /* Onboard NIC: slot 1, intno 0x21 */
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:659: ncells += pci_encode_phys_addr(props + ncells, 0, 0, PCI_ADDR(1, 1, 0), 0, 0);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-660- props[ncells++] = 0x1;
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-664- /* Onboard IDE: slot 3, intno 0x20 */
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:665: ncells += pci_encode_phys_addr(props + ncells, 0, 0, PCI_ADDR(1, 3, 0), 0, 0);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-666- props[ncells++] = 0x1;
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-774-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:775: addr = PCI_ADDR(
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-776- PCI_BUS(config->dev),
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-845- continue;
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:846: pci_decode_pci_addr(config->assigned[i],
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-847- &flags, &space_code, &mask);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-848-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:849: props[ncells++] = pci_bus_addr_to_host_addr(space_code,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-850- config->assigned[i] & ~mask);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-871- continue;
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:872: pci_decode_pci_addr(config->assigned[i],
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-873- &flags, &space_code, &mask);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-874-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:875: ncells += pci_encode_phys_addr(props + ncells,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-876- flags, space_code, config->dev,
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-919- /* first (addr, size) pair is the beginning of configuration address space */
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:920: ncells += pci_encode_phys_addr(props + ncells, 0, CONFIGURATION_SPACE,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-921- config->dev, 0, 0);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-929-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:930: pci_decode_pci_addr(config->regions[i],
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-931- &flags, &space_code, &mask);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-932-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:933: ncells += pci_encode_phys_addr(props + ncells,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-934- flags, space_code, config->dev,
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-971-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:972: pci_decode_pci_addr(config->assigned[i],
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-973- &flags, &space_code, &mask);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:974: ncells += pci_encode_phys_addr(props + ncells, flags, space_code,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-975- config->dev, 0x10 + i * 4,
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1016- if (config->assigned[6]) {
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1017: rom = pci_bus_addr_to_host_addr(MEMORY_SPACE_32,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1018- config->assigned[6] & ~0x0000000F);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1095-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1096: pci_decode_pci_addr(config->assigned[i],
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1097- &flags, &space_code, &mask);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1101-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1102: ncells += pci_encode_phys_addr(props + ncells,
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1103- flags, space_code, config->dev,
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1110- if (io_phys_base == 0x0 && space_code == IO_SPACE) {
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1111: io_phys_base = pci_bus_addr_to_host_addr(space_code, config->assigned[i] & ~mask);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1112- }
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1208-#ifdef CONFIG_DRIVER_USB
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1209: pci_addr addr = PCI_ADDR(
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1210- PCI_BUS(config->dev), PCI_DEV(config->dev), PCI_FN(config->dev));
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1239- uint16_t cmd;
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1240: pci_addr addr = PCI_ADDR(
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1241- PCI_BUS(config->dev), PCI_DEV(config->dev), PCI_FN(config->dev));
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1497- /* Ignore 64-bit BAR MSBs (always map in 32-bit space) */
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1498: pci_decode_pci_addr(config->assigned[reg],
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1499- &flags, &space_code, &mask);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1548-{
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1549: *ncells += pci_encode_phys_addr(props + *ncells, 0, 0, addr, 0, 0);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1550- props[(*ncells)++] = intno;
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1713-#endif
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1714: addr = PCI_ADDR(bus, devnum, fn);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1715- vid = pci_config_read16(addr, PCI_VENDOR_ID);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1763-
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1764: addr = PCI_ADDR(bus, devnum, fn);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1765- iface = pci_config_read8(addr, PCI_CLASS_PROG);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1813- /* Get encoded address for set-args */
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1814: pci_encode_phys_addr(props, 0, CONFIGURATION_SPACE, config.dev, 0, 0);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1815- PUSH(props[2]);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1898- ncells = 0;
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1899: ncells += pci_encode_phys_addr(props + ncells, 0, MEMORY_SPACE_32, 0, 0, mem_base);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1900- ncells += pci_encode_size(props + ncells, arch->mem_len - mem_base);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1901: ncells += pci_encode_phys_addr(props + ncells, 0, IO_SPACE, 0, 0, io_base);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1902- ncells += pci_encode_size(props + ncells, arch->io_len - io_base);
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1991-{
qemu-5.1+dfsg/roms/openbios/drivers/pci.c:1992: *ncells += pci_encode_phys_addr(props + *ncells, 0, 0, addr, 0, 0);
qemu-5.1+dfsg/roms/openbios/drivers/pci.c-1993-
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pci.fs-15-\ Get PCI physical address and size for configured BAR reg
qemu-5.1+dfsg/roms/openbios/drivers/pci.fs:16:: pci-bar>pci-addr ( bar-reg -- addr.lo addr.mid addr.hi size -1 | 0 )
qemu-5.1+dfsg/roms/openbios/drivers/pci.fs-17- " assigned-addresses" active-package get-package-property 0= if
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pmu.c-207- return *(volatile uint8_t *)(dev->base + reg);
qemu-5.1+dfsg/roms/openbios/drivers/pmu.c:208: asm volatile("eieio" : : : "memory");
qemu-5.1+dfsg/roms/openbios/drivers/pmu.c-209-}
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/pmu.c-213- *(volatile uint8_t *)(dev->base + reg) = val;
qemu-5.1+dfsg/roms/openbios/drivers/pmu.c:214: asm volatile("eieio" : : : "memory");
qemu-5.1+dfsg/roms/openbios/drivers/pmu.c-215-}
##############################################
qemu-5.1+dfsg/roms/openbios/drivers/sbus.fs-22-
qemu-5.1+dfsg/roms/openbios/drivers/sbus.fs:23:: sbus-unit>addr ( phys.lo phys.hi -- phys.lo phys.hi -1 | 0 )
qemu-5.1+dfsg/roms/openbios/drivers/sbus.fs-24- " ranges" my-self ihandle>phandle
##############################################
qemu-5.1+dfsg/roms/openbios/forth/device/display.fs-176-
qemu-5.1+dfsg/roms/openbios/forth/device/display.fs:177:: fb8-line2addr ( line -- addr )
qemu-5.1+dfsg/roms/openbios/forth/device/display.fs-178- window-top +
##############################################
qemu-5.1+dfsg/roms/openbios/forth/device/display.fs-183-
qemu-5.1+dfsg/roms/openbios/forth/device/display.fs:184:: fb8-curpos2addr ( col line -- addr )
qemu-5.1+dfsg/roms/openbios/forth/device/display.fs-185- char-height * fb8-line2addr
##############################################
qemu-5.1+dfsg/roms/openbios/forth/device/display.fs-270- over column# + line# fb8-curpos2addr
qemu-5.1+dfsg/roms/openbios/forth/device/display.fs:271: column# line# fb8-curpos2addr ( n numbytescopy destaddr srcaddr )
qemu-5.1+dfsg/roms/openbios/forth/device/display.fs-272- char-height 0 do
##############################################
qemu-5.1+dfsg/roms/openbios/forth/util/util.fs-112-\ Return the address of a named constant or value
qemu-5.1+dfsg/roms/openbios/forth/util/util.fs:113:: addr ( <word> -- addr )
qemu-5.1+dfsg/roms/openbios/forth/util/util.fs-114- parse-word $find if
##############################################
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.c-176-
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.c:177:unsigned int ext2_get_block_addr(ext2_VOLUME* volume, struct ext2_inode *inode,
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.c-178- unsigned int logical)
##############################################
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.c-247- if (shift) {
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.c:248: physical = ext2_get_block_addr(volume, inode, logical);
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.c-249- ext2_read_block(volume, physical);
##############################################
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.c-263- while (length) {
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.c:264: physical = ext2_get_block_addr(volume, inode, logical);
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.c-265- ext2_read_block(volume, physical);
##############################################
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.h-45- unsigned int ino, struct ext2_inode *inode);
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.h:46:extern unsigned int ext2_get_block_addr(ext2_VOLUME* volume,
qemu-5.1+dfsg/roms/openbios/fs/ext2/ext2_utils.h-47- struct ext2_inode *inode,
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/filesys.h-57-
qemu-5.1+dfsg/roms/openbios/fs/grubfs/filesys.h:58: asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
qemu-5.1+dfsg/roms/openbios/fs/grubfs/filesys.h-59- return 31 - lz;
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fs.h-127- * from first cylinder group data blocks. These blocks have to be
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fs.h:128: * read in from fs_csaddr (size fs_cssize) in addition to the
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fs.h-129- * super block.
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-185-static xfs_daddr_t
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c:186:agb2daddr (xfs_agnumber_t agno, xfs_agblock_t agbno)
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-187-{
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-191-static xfs_daddr_t
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c:192:fsb2daddr (xfs_fsblock_t fsbno)
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-193-{
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c:194: return agb2daddr ((xfs_agnumber_t)(fsbno >> xfs.agblklog),
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-195- (xfs_agblock_t)(fsbno & mask32lo(xfs.agblklog)));
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-222- offset = ino2offset (ino);
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c:223: daddr = agb2daddr (agno, agbno);
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-224-
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-247- for (;;) {
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c:248: xfs.daddr = fsb2daddr (le64(ptr0));
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-249- devread (xfs.daddr, 0,
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-252- xfs.nextents = le16(h.bb_numrecs);
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c:253: xfs.next = fsb2daddr (le64(h.bb_rightsib));
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-254- xfs.fpos = sizeof(xfs_btree_block_t);
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-280- xfs.nextents = le16(h.bb_numrecs);
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c:281: xfs.next = fsb2daddr (le64(h.bb_rightsib));
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-282- xfs.fpos = sizeof(xfs_btree_block_t);
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-310- if (isinxt (xfs.dablk, offset, xad->len)) {
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c:311: devread (fsb2daddr (xad->start + xfs.dablk - offset),
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-312- 0, 100, dirbuf);
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-527- disk_read_func = disk_read_hook;
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c:528: devread (fsb2daddr (xad->start),
qemu-5.1+dfsg/roms/openbios/fs/grubfs/fsys_xfs.c-529- filepos - (offset << xfs.blklog), toread, buf);
##############################################
qemu-5.1+dfsg/roms/openbios/fs/grubfs/ufs_fs.h-230- * from first cylinder group data blocks. These blocks have to be
qemu-5.1+dfsg/roms/openbios/fs/grubfs/ufs_fs.h:231: * read in from fs_csaddr (size fs_cssize) in addition to the
qemu-5.1+dfsg/roms/openbios/fs/grubfs/ufs_fs.h-232- * super block.
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/amd64/pci.h-15- * so register accesses can be made easy. */
qemu-5.1+dfsg/roms/openbios/include/arch/amd64/pci.h:16:#define PCI_ADDR(bus, dev, fn) \
qemu-5.1+dfsg/roms/openbios/include/arch/amd64/pci.h-17- ((pci_addr) (0x80000000u \
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h-109-#if !defined (N_TXTADDR)
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h:110:#define N_TXTADDR(x) (N_MAGIC(x) == QMAGIC ? PAGE_SIZE : 0)
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h-111-#endif
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h-145-
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h:146:#define _N_TXTENDADDR(x) (N_TXTADDR(x)+(x).a_text)
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h-147-
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h-148-#ifndef N_DATADDR
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h:149:#define N_DATADDR(x) \
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h:150: (N_MAGIC(x)==OMAGIC? (_N_TXTENDADDR(x)) \
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h:151: : (_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h-152-#endif
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h-155-#if !defined (N_BSSADDR)
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h:156:#define N_BSSADDR(x) (N_DATADDR(x) + (x).a_data)
qemu-5.1+dfsg/roms/openbios/include/arch/common/a.out.h-157-#endif
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/common/fw_cfg.h-46-#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
qemu-5.1+dfsg/roms/openbios/include/arch/common/fw_cfg.h:47:#define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08)
qemu-5.1+dfsg/roms/openbios/include/arch/common/fw_cfg.h-48-#define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09)
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/asmdefs.h:1:/* -*- asm -*-
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/asmdefs.h-2- *
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/pci.h-13-
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/pci.h:14:#define PCI_ADDR(bus, dev, fn) \
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/pci.h-15- ((pci_addr) (0x80000000u \
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-411-#define __stringify(x) __stringify_1(x)
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h:412:#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-413-
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-416- unsigned long msr;
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h:417: asm volatile("mfmsr %0" : "=r" (msr));
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-418- return msr;
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-423-#ifdef __powerpc64__
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h:424: asm volatile("mtmsrd %0" :: "r" (msr));
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-425-#else
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h:426: asm volatile("mtmsr %0" :: "r" (msr));
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-427-#endif
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-438- unsigned long sdr1;
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h:439: asm volatile("mfsdr1 %0" : "=r" (sdr1));
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-440- return sdr1;
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-444-{
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h:445: asm volatile("mtsdr1 %0" :: "r" (sdr1));
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-446-}
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-450- unsigned int pvr;
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h:451: asm volatile("mfspr %0, 0x11f" : "=r" (pvr) );
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-452- return pvr;
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-456-{
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h:457: asm volatile("slbia" ::: "memory");
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-458-}
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-461-{
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h:462: asm volatile("slbmte %0,%1 ; isync" :: "r" (rs), "r" (rb) : "memory");
qemu-5.1+dfsg/roms/openbios/include/arch/ppc/processor.h-463-}
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/a.out.h-30-/* Where does text segment go in memory after being loaded? */
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/a.out.h:31:#define N_TXTADDR(x) (((N_MAGIC(x) == ZMAGIC) && \
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/a.out.h-32- ((x).a_entry < SPARC_PGSIZE)) ? \
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/a.out.h-35-/* And same for the data segment.. */
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/a.out.h:36:#define N_DATADDR(x) (N_MAGIC(x)==OMAGIC ? \
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/a.out.h:37: (N_TXTADDR(x) + (x).a_text) \
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/a.out.h:38: : (_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/a.out.h-39-
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/pgtsrmmu.h-141-
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/pgtsrmmu.h:142:static __inline__ unsigned int srmmu_get_faddr(void)
qemu-5.1+dfsg/roms/openbios/include/arch/sparc32/pgtsrmmu.h-143-{
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/a.out.h-34-/* Where does text segment go in memory after being loaded? */
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/a.out.h:35:#define N_TXTADDR(x) (unsigned long)(((N_MAGIC(x) == ZMAGIC) && \
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/a.out.h-36- ((x).a_entry < SPARC_PGSIZE)) ? \
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/a.out.h-39-/* And same for the data segment.. */
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/a.out.h:40:#define N_DATADDR(x) (N_MAGIC(x)==OMAGIC ? \
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/a.out.h:41: (N_TXTADDR(x) + (x).a_text) \
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/a.out.h:42: : (unsigned long)(_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/a.out.h-43-
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/pci.h-13-
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/pci.h:14:#define PCI_ADDR(bus, dev, fn) \
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/pci.h-15- (((pci_addr) (uint32_t) (bus) << 16 \
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/pci.h-23-#define PCI_CONFIG(dev) (arch->cfg_addr \
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/pci.h:24: + (unsigned long)PCI_ADDR(PCI_BUS(dev), \
qemu-5.1+dfsg/roms/openbios/include/arch/sparc64/pci.h-25- PCI_DEV(dev), \
##############################################
qemu-5.1+dfsg/roms/openbios/include/arch/x86/pci.h-15- * so register accesses can be made easy. */
qemu-5.1+dfsg/roms/openbios/include/arch/x86/pci.h:16:#define PCI_ADDR(bus, dev, fn) \
qemu-5.1+dfsg/roms/openbios/include/arch/x86/pci.h-17- ((pci_addr) (0x80000000u \
##############################################
qemu-5.1+dfsg/roms/openbios/include/libopenbios/ofmem.h-69-extern int ofmem_arch_get_physaddr_cellsize(void);
qemu-5.1+dfsg/roms/openbios/include/libopenbios/ofmem.h:70:extern int ofmem_arch_encode_physaddr(ucell *p, phys_addr_t value);
qemu-5.1+dfsg/roms/openbios/include/libopenbios/ofmem.h-71-extern int ofmem_arch_get_available_entry_size(phandle_t ph);
##############################################
qemu-5.1+dfsg/roms/openbios/kernel/bootstrap.c-710-#ifdef CONFIG_DEBUG_INTERPRETER
qemu-5.1+dfsg/roms/openbios/kernel/bootstrap.c:711: printk("writing lit, addr(%s) to dict\n\n",
qemu-5.1+dfsg/roms/openbios/kernel/bootstrap.c-712- tib);
##############################################
qemu-5.1+dfsg/roms/openbios/libgcc/crtsavres.S-7- *
qemu-5.1+dfsg/roms/openbios/libgcc/crtsavres.S:8: * Based on gcc/config/rs6000/crtsavres.asm from gcc
qemu-5.1+dfsg/roms/openbios/libgcc/crtsavres.S-9- * 64 bit additions from reading the PPC elf64abi document.
##############################################
qemu-5.1+dfsg/roms/openbios/libopenbios/aout_load.c-109- if (N_MAGIC(ehdr) == NMAGIC) {
qemu-5.1+dfsg/roms/openbios/libopenbios/aout_load.c:110: size = addr_fixup(N_DATADDR(ehdr)) + addr_fixup(ehdr.a_data);
qemu-5.1+dfsg/roms/openbios/libopenbios/aout_load.c-111- } else {
##############################################
qemu-5.1+dfsg/roms/openbios/libopenbios/aout_load.c-118- fword("load-base");
qemu-5.1+dfsg/roms/openbios/libopenbios/aout_load.c:119: start = POP(); // N_TXTADDR(ehdr);
qemu-5.1+dfsg/roms/openbios/libopenbios/aout_load.c-120-
##############################################
qemu-5.1+dfsg/roms/openbios/libopenbios/aout_load.c-133- }
qemu-5.1+dfsg/roms/openbios/libopenbios/aout_load.c:134: if ((size_t)read_io(fd, (void *)(start + N_DATADDR(ehdr)), ehdr.a_data) != ehdr.a_data) {
qemu-5.1+dfsg/roms/openbios/libopenbios/aout_load.c-135- printf("Can't read program data segment (size 0x" FMT_aout_ehdr ")\n", ehdr.a_data);
##############################################
qemu-5.1+dfsg/roms/openbios/Makefile.target-56- $(call quiet-command,true, " GEN $(TARGET_DIR)$@")
qemu-5.1+dfsg/roms/openbios/Makefile.target:57: @DATE="$(shell echo `LC_ALL=C date --utc --date=@$(SOURCE_DATE_EPOCH) +'%b %e %Y %H:%M'`)" ; \
qemu-5.1+dfsg/roms/openbios/Makefile.target-58- ( echo ": builddate \" $$DATE\" ; " ; \
##############################################
qemu-5.1+dfsg/roms/openbios/Makefile.target-63- $(call quiet-command,true, " GEN $(TARGET_DIR)$@")
qemu-5.1+dfsg/roms/openbios/Makefile.target:64: @DATE="$(shell echo `LC_ALL=C date --utc --date=@$(SOURCE_DATE_EPOCH) +'%b %e %Y %H:%M'`)" ; \
qemu-5.1+dfsg/roms/openbios/Makefile.target-65- ( echo "#define OPENBIOS_BUILD_DATE \"$$DATE\"" ; \
##############################################
qemu-5.1+dfsg/roms/opensbi/firmware/payloads/test_main.c-17- register unsigned long a7 asm("a7") = (unsigned long)(__num); \
qemu-5.1+dfsg/roms/opensbi/firmware/payloads/test_main.c:18: asm volatile("ecall" \
qemu-5.1+dfsg/roms/opensbi/firmware/payloads/test_main.c-19- : "+r"(a0) \
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_barrier.h-39-/* CPU relax for busy loop */
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_barrier.h:40:#define cpu_relax() asm volatile ("" : : : "memory")
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_barrier.h-41-
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_fp.h-37- ulong tmp; \
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_fp.h:38: asm volatile( \
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_fp.h-39- "1: auipc %0, %%pcrel_hi(put_f32_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_fp.h-60- ulong tmp; \
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_fp.h:61: asm volatile( \
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_fp.h-62- "1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" \
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-17-{
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h:18: asm volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr));
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-19-}
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-22-{
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h:23: asm volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr));
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-24-}
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-27-{
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h:28: asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr));
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-29-}
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-33-{
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h:34: asm volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr));
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-35-}
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-41-
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h:42: asm volatile("lb %0, 0(%1)" : "=r"(val) : "r"(addr));
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-43- return val;
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-49-
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h:50: asm volatile("lh %0, 0(%1)" : "=r"(val) : "r"(addr));
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-51- return val;
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-57-
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h:58: asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr));
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-59- return val;
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-66-
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h:67: asm volatile("ld %0, 0(%1)" : "=r"(val) : "r"(addr));
qemu-5.1+dfsg/roms/opensbi/include/sbi/riscv_io.h-68- return val;
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/sbi_hart.h-19-extern void (*sbi_hart_unpriv_trap)(void);
qemu-5.1+dfsg/roms/opensbi/include/sbi/sbi_hart.h:20:static inline ulong sbi_hart_unpriv_trap_addr(void)
qemu-5.1+dfsg/roms/opensbi/include/sbi/sbi_hart.h-21-{
##############################################
qemu-5.1+dfsg/roms/opensbi/include/sbi/sbi_hart.h-26-void sbi_hart_pmp_dump(struct sbi_scratch *scratch);
qemu-5.1+dfsg/roms/opensbi/include/sbi/sbi_hart.h:27:int sbi_hart_pmp_check_addr(struct sbi_scratch *scratch, unsigned long daddr,
qemu-5.1+dfsg/roms/opensbi/include/sbi/sbi_hart.h-28- unsigned long attr);
##############################################
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_hart.c-167-
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_hart.c:168:int sbi_hart_pmp_check_addr(struct sbi_scratch *scratch, unsigned long addr,
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_hart.c-169- unsigned long attr)
##############################################
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_hsm.c-230-
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_hsm.c:231: rc = sbi_hart_pmp_check_addr(scratch, saddr, PMP_X);
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_hsm.c-232- if (rc)
##############################################
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-23- register ulong mstatus asm("a5"); \
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c:24: register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-25- type ret = 0; \
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-26- trap->cause = 0; \
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c:27: asm volatile( \
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-28- "add %[tinfo], %[taddr], zero\n" \
##############################################
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-53- register ulong mstatus asm("a5"); \
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c:54: register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-55- trap->cause = 0; \
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c:56: asm volatile( \
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-57- "add %[tinfo], %[taddr], zero\n" \
##############################################
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-122- register ulong mstatus asm("a5");
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c:123: register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr();
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-124- ulong insn = 0;
##############################################
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-127-
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c:128: asm volatile(
qemu-5.1+dfsg/roms/opensbi/lib/sbi/sbi_unpriv.c-129- "add %[tinfo], %[taddr], zero\n"
##############################################
qemu-5.1+dfsg/roms/opensbi/Makefile-73-# Find library version
qemu-5.1+dfsg/roms/opensbi/Makefile:74:OPENSBI_VERSION_MAJOR=`grep "define OPENSBI_VERSION_MAJOR" $(include_dir)/sbi/sbi_version.h | sed 's/.*MAJOR.*\([0-9][0-9]*\)/\1/'`
qemu-5.1+dfsg/roms/opensbi/Makefile:75:OPENSBI_VERSION_MINOR=`grep "define OPENSBI_VERSION_MINOR" $(include_dir)/sbi/sbi_version.h | sed 's/.*MINOR.*\([0-9][0-9]*\)/\1/'`
qemu-5.1+dfsg/roms/opensbi/Makefile-76-OPENSBI_VERSION_GIT=$(shell if [ -d $(src_dir)/.git ]; then git describe 2> /dev/null; fi)
##############################################
qemu-5.1+dfsg/roms/opensbi/Makefile-95-# Guess the compillers xlen
qemu-5.1+dfsg/roms/opensbi/Makefile:96:OPENSBI_CC_XLEN := $(shell TMP=`$(CC) -dumpmachine | sed 's/riscv\([0-9][0-9]\).*/\1/'`; echo $${TMP})
qemu-5.1+dfsg/roms/opensbi/Makefile-97-
##############################################
qemu-5.1+dfsg/roms/opensbi/Makefile-235-endef
qemu-5.1+dfsg/roms/opensbi/Makefile:236:merge_objs = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-237- echo " MERGE $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile-238- $(LD) $(MERGEFLAGS) $(2) -o $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:239:merge_deps = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-240- echo " MERGE-DEP $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile-241- cat $(2) > $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:242:copy_file = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-243- echo " COPY $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile-244- cp -f $(2) $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:245:inst_file = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-246- echo " INSTALL $(subst $(install_root_dir)/,,$(1))"; \
##############################################
qemu-5.1+dfsg/roms/opensbi/Makefile-250- for file in $(4) ; do \
qemu-5.1+dfsg/roms/opensbi/Makefile:251: rel_file=`echo $$file | sed -e 's@$(2)/$(subst $(install_firmware_path),platform,$(3))@@'`; \
qemu-5.1+dfsg/roms/opensbi/Makefile:252: dest_file=$(1)"/"$(3)"/"`echo $$rel_file`; \
qemu-5.1+dfsg/roms/opensbi/Makefile:253: dest_dir=`dirname $$dest_file`; \
qemu-5.1+dfsg/roms/opensbi/Makefile:254: echo " INSTALL "$(3)"/"`echo $$rel_file`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-255- mkdir -p $$dest_dir; \
##############################################
qemu-5.1+dfsg/roms/opensbi/Makefile-261- cp -rf $(2) $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:262:compile_cpp = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-263- echo " CPP $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile-264- $(CPP) $(CPPFLAGS) -x c $(2) | grep -v "\#" > $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:265:compile_cc_dep = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-266- echo " CC-DEP $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile:267: printf %s `dirname $(1)`/ > $(1) && \
qemu-5.1+dfsg/roms/opensbi/Makefile-268- $(CC) $(CFLAGS) $(call dynamic_flags,$(1),$(2)) \
qemu-5.1+dfsg/roms/opensbi/Makefile-269- -MM $(2) >> $(1) || rm -f $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:270:compile_cc = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-271- echo " CC $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile-272- $(CC) $(CFLAGS) $(call dynamic_flags,$(1),$(2)) -c $(2) -o $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:273:compile_as_dep = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-274- echo " AS-DEP $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile:275: printf %s `dirname $(1)`/ > $(1) && \
qemu-5.1+dfsg/roms/opensbi/Makefile-276- $(AS) $(ASFLAGS) $(call dynamic_flags,$(1),$(2)) \
qemu-5.1+dfsg/roms/opensbi/Makefile-277- -MM $(2) >> $(1) || rm -f $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:278:compile_as = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-279- echo " AS $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile-280- $(AS) $(ASFLAGS) $(call dynamic_flags,$(1),$(2)) -c $(2) -o $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:281:compile_elf = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-282- echo " ELF $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile-283- $(CC) $(CFLAGS) $(3) $(ELFFLAGS) -Wl,-T$(2) -o $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:284:compile_ar = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-285- echo " AR $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile-286- $(AR) $(ARFLAGS) $(1) $(2)
qemu-5.1+dfsg/roms/opensbi/Makefile:287:compile_objcopy = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-288- echo " OBJCOPY $(subst $(build_dir)/,,$(1))"; \
qemu-5.1+dfsg/roms/opensbi/Makefile-289- $(OBJCOPY) -S -O binary $(2) $(1)
qemu-5.1+dfsg/roms/opensbi/Makefile:290:compile_dts = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
qemu-5.1+dfsg/roms/opensbi/Makefile-291- echo " DTC $(subst $(build_dir)/,,$(1))"; \
##############################################
qemu-5.1+dfsg/roms/opensbi/platform/andes/ae350/platform.h-25-#define AE350_UART_ADDR_OFFSET 0x20
qemu-5.1+dfsg/roms/opensbi/platform/andes/ae350/platform.h:26:#define AE350_UART_ADDR (0xf0300000 + AE350_UART_ADDR_OFFSET)
qemu-5.1+dfsg/roms/opensbi/platform/andes/ae350/platform.h-27-#define AE350_UART_FREQUENCY 19660800
##############################################
qemu-5.1+dfsg/roms/opensbi/platform/thead/c910/platform.c-104-{
qemu-5.1+dfsg/roms/opensbi/platform/thead/c910/platform.c:105: asm volatile ("ebreak");
qemu-5.1+dfsg/roms/opensbi/platform/thead/c910/platform.c-106- return 0;
##############################################
qemu-5.1+dfsg/roms/qboot/code16.c-10-{
qemu-5.1+dfsg/roms/qboot/code16.c:11: asm volatile("movw %0,%%fs" : : "rm" (seg));
qemu-5.1+dfsg/roms/qboot/code16.c-12-}
##############################################
qemu-5.1+dfsg/roms/qboot/code16.c-17-
qemu-5.1+dfsg/roms/qboot/code16.c:18: asm volatile("addr32 movb %%fs:%1,%0" : "=q" (v) : "m" (*(uint8_t *)addr));
qemu-5.1+dfsg/roms/qboot/code16.c-19-
##############################################
qemu-5.1+dfsg/roms/qboot/code16.c-26-
qemu-5.1+dfsg/roms/qboot/code16.c:27: asm volatile("addr32 movl %%fs:%1,%0" : "=r" (v) : "m" (*(uint32_t *)addr));
qemu-5.1+dfsg/roms/qboot/code16.c-28-
##############################################
qemu-5.1+dfsg/roms/qboot/code16.c-36-
qemu-5.1+dfsg/roms/qboot/code16.c:37: asm volatile("addr32 movw %%cs:%1,%0" : "=r" (v) : "m" (*(uint32_t *)addr));
qemu-5.1+dfsg/roms/qboot/code16.c-38-
##############################################
qemu-5.1+dfsg/roms/qboot/fw_cfg.c-186- kernel_entry = (void *) fw_cfg_readl_le();
qemu-5.1+dfsg/roms/qboot/fw_cfg.c:187: asm volatile("jmp *%2" : : "a" (0x2badb002), "b"(mb), "c"(kernel_entry));
qemu-5.1+dfsg/roms/qboot/fw_cfg.c-188- panic();
##############################################
qemu-5.1+dfsg/roms/qboot/fw_cfg.c-262-#endif
qemu-5.1+dfsg/roms/qboot/fw_cfg.c:263: asm volatile("jmp *%2" : : "a" (0x2badb002),
qemu-5.1+dfsg/roms/qboot/fw_cfg.c-264- "b"(&start_info), "c"(kernel_entry));
##############################################
qemu-5.1+dfsg/roms/qboot/include/ioport.h-5-{
qemu-5.1+dfsg/roms/qboot/include/ioport.h:6: asm volatile("rep outsb %%ds:(%0), %3" : "=S" (buf), "=c" (len) : "m"(buf), "Nd"(port), "0" (buf), "1" (len));
qemu-5.1+dfsg/roms/qboot/include/ioport.h-7-}
##############################################
qemu-5.1+dfsg/roms/qboot/include/ioport.h-10-{
qemu-5.1+dfsg/roms/qboot/include/ioport.h:11: asm volatile("rep insb %3, %%es:(%0)" : "=D" (buf), "=c" (len), "=m"(buf) : "Nd"(port), "0" (buf), "1" (len));
qemu-5.1+dfsg/roms/qboot/include/ioport.h-12-}
##############################################
qemu-5.1+dfsg/roms/qboot/include/ioport.h-16- unsigned char val;
qemu-5.1+dfsg/roms/qboot/include/ioport.h:17: asm volatile("inb %1, %0" : "=a"(val) : "Nd"(port));
qemu-5.1+dfsg/roms/qboot/include/ioport.h-18- return val;
##############################################
qemu-5.1+dfsg/roms/qboot/include/ioport.h-23- unsigned short val;
qemu-5.1+dfsg/roms/qboot/include/ioport.h:24: asm volatile("inw %1, %0" : "=a"(val) : "Nd"(port));
qemu-5.1+dfsg/roms/qboot/include/ioport.h-25- return val;
##############################################
qemu-5.1+dfsg/roms/qboot/include/ioport.h-30- unsigned val;
qemu-5.1+dfsg/roms/qboot/include/ioport.h:31: asm volatile("inl %1, %0" : "=a"(val) : "Nd"(port));
qemu-5.1+dfsg/roms/qboot/include/ioport.h-32- return val;
##############################################
qemu-5.1+dfsg/roms/qboot/include/ioport.h-36-{
qemu-5.1+dfsg/roms/qboot/include/ioport.h:37: asm volatile("outb %0, %1" : : "a"(val), "Nd"(port));
qemu-5.1+dfsg/roms/qboot/include/ioport.h-38-}
##############################################
qemu-5.1+dfsg/roms/qboot/include/ioport.h-41-{
qemu-5.1+dfsg/roms/qboot/include/ioport.h:42: asm volatile("outw %0, %1" : : "a"(val), "Nd"(port));
qemu-5.1+dfsg/roms/qboot/include/ioport.h-43-}
##############################################
qemu-5.1+dfsg/roms/qboot/include/ioport.h-46-{
qemu-5.1+dfsg/roms/qboot/include/ioport.h:47: asm volatile("outl %0, %1" : : "a"(val), "Nd"(port));
qemu-5.1+dfsg/roms/qboot/include/ioport.h-48-}
##############################################
qemu-5.1+dfsg/roms/qboot/include/bios.h-85-{
qemu-5.1+dfsg/roms/qboot/include/bios.h:86: asm volatile("cli; hlt");
qemu-5.1+dfsg/roms/qboot/include/bios.h-87- for(;;);
##############################################
qemu-5.1+dfsg/roms/qboot/linuxboot.c-101-#endif
qemu-5.1+dfsg/roms/qboot/linuxboot.c:102: asm volatile(
qemu-5.1+dfsg/roms/qboot/linuxboot.c-103- "ljmp $0x18, $pm16_boot_linux - 0xf0000"
##############################################
qemu-5.1+dfsg/roms/qboot/tables.c-43-
qemu-5.1+dfsg/roms/qboot/tables.c:44:static inline void *id_to_addr(int fw_cfg_id)
qemu-5.1+dfsg/roms/qboot/tables.c-45-{
##############################################
qemu-5.1+dfsg/roms/qboot/tables.c-48-
qemu-5.1+dfsg/roms/qboot/tables.c:49:static inline void set_file_addr(int fw_cfg_id, void *p)
qemu-5.1+dfsg/roms/qboot/tables.c-50-{
##############################################
qemu-5.1+dfsg/roms/qboot/tables.c-70-
qemu-5.1+dfsg/roms/qboot/tables.c:71: set_file_addr(id, p);
qemu-5.1+dfsg/roms/qboot/tables.c-72- fw_cfg_read_file(id, p, n);
##############################################
qemu-5.1+dfsg/roms/qboot/tables.c-76- if (!memcmp(p, "RSD PTR ", 8)) {
qemu-5.1+dfsg/roms/qboot/tables.c:77: start_info.rsdp_paddr = (uintptr_t)id_to_addr(id);
qemu-5.1+dfsg/roms/qboot/tables.c-78- }
##############################################
qemu-5.1+dfsg/roms/qboot/tables.c-91- id = fw_cfg_file_id(src);
qemu-5.1+dfsg/roms/qboot/tables.c:92: p = id_to_addr(id);
qemu-5.1+dfsg/roms/qboot/tables.c-93- if (!p)
##############################################
qemu-5.1+dfsg/roms/qboot/tables.c-96- id = fw_cfg_file_id(dest);
qemu-5.1+dfsg/roms/qboot/tables.c:97: q = id_to_addr(id);
qemu-5.1+dfsg/roms/qboot/tables.c-98- if (!q)
##############################################
qemu-5.1+dfsg/roms/qboot/tables.c-123- id = fw_cfg_file_id(file);
qemu-5.1+dfsg/roms/qboot/tables.c:124: p = id_to_addr(id);
qemu-5.1+dfsg/roms/qboot/tables.c-125- if (!p)
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/core-typhoon.h-25-#define PIO_PHYS_ADDR 0x80000000000
qemu-5.1+dfsg/roms/qemu-palcode/core-typhoon.h:26:#define PIO_KSEG_ADDR (0xfffffc0000000000 + 0x10000000000)
qemu-5.1+dfsg/roms/qemu-palcode/core-typhoon.h-27-
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/osf.h-77-** <6:5> 2 GH Granularity Hint
qemu-5.1+dfsg/roms/qemu-palcode/osf.h:78:** <4> 1 ASM Address Space Match
qemu-5.1+dfsg/roms/qemu-palcode/osf.h-79-** <3> 1 FOE Fault On Execute
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/osf.h-98-#define PTE_M_GH (3<<PTE_V_GH)
qemu-5.1+dfsg/roms/qemu-palcode/osf.h:99:#define PTE_V_ASM 4
qemu-5.1+dfsg/roms/qemu-palcode/osf.h:100:#define PTE_M_ASM (1<<PTE_V_ASM)
qemu-5.1+dfsg/roms/qemu-palcode/osf.h-101-#define PTE_V_FOE 3
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/osf.h-347-#define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */
qemu-5.1+dfsg/roms/qemu-palcode/osf.h:348:#define _PAGE_ASM 0x0010
qemu-5.1+dfsg/roms/qemu-palcode/osf.h-349-#define _PAGE_KRE 0x0100 /* xxx - see below on the "accessed" bit */
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-38-
qemu-5.1+dfsg/roms/qemu-palcode/protos.h:39: asm volatile ("call_pal 0x34"
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-40- : "+r"(a0), "+r"(a1)
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-48-
qemu-5.1+dfsg/roms/qemu-palcode/protos.h:49: asm volatile ("call_pal 0x35"
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-50- : "=r"(v0), "+r"(a0)
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-59-
qemu-5.1+dfsg/roms/qemu-palcode/protos.h:60: asm volatile ("call_pal 0x36"
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-61- : "=r"(v0) : : "$1", "$22", "$23", "$24", "$25");
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-67-{
qemu-5.1+dfsg/roms/qemu-palcode/protos.h:68: asm volatile ("mov $29, $16\n\tcall_pal 0x37"
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-69- : : : "$16", "$1", "$22", "$23", "$24", "$25");
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-76-
qemu-5.1+dfsg/roms/qemu-palcode/protos.h:77: asm volatile ("call_pal 0x3e"
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-78- : "=r"(v0), "+r"(a0)
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-93-
qemu-5.1+dfsg/roms/qemu-palcode/protos.h:94: asm volatile ("call_pal 9"
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-95- : "=r"(v0), "+r"(a0), "+r"(a1) :
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-107-
qemu-5.1+dfsg/roms/qemu-palcode/protos.h:108: asm volatile ("call_pal 9"
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-109- : "=r"(v0), "+r"(a0), "+r"(a1), "+r"(a2) :
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-139-
qemu-5.1+dfsg/roms/qemu-palcode/protos.h:140: asm volatile ("call_pal 9"
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-141- : "+r"(a0), "+r"(a1)
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-149-
qemu-5.1+dfsg/roms/qemu-palcode/protos.h:150: asm volatile ("call_pal 9"
qemu-5.1+dfsg/roms/qemu-palcode/protos.h-151- : "+r"(a0), "+r"(a1)
##############################################
qemu-5.1+dfsg/roms/qemu-palcode/util.c-27- register long v0 __asm__("0");
qemu-5.1+dfsg/roms/qemu-palcode/util.c:28: asm volatile ("call_pal 3" : "=r"(v0) : "r"(a0));
qemu-5.1+dfsg/roms/qemu-palcode/util.c-29- return v0;
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/docs/Build_overview.md-61-
qemu-5.1+dfsg/roms/seabios-hppa/docs/Build_overview.md:62:`make EXTRAVERSION="-${RPM_PACKAGE_RELEASE}"`
qemu-5.1+dfsg/roms/seabios-hppa/docs/Build_overview.md-63-
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/Makefile-51-# Default compiler flags
qemu-5.1+dfsg/roms/seabios-hppa/Makefile:52:cc-option=$(shell if test -z "`$(1) $(2) -S -o /dev/null -xc /dev/null 2>&1`" \
qemu-5.1+dfsg/roms/seabios-hppa/Makefile-53- ; then echo "$(2)"; else echo "$(3)"; fi ;)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/Makefile-256-
qemu-5.1+dfsg/roms/seabios-hppa/Makefile:257:iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \
qemu-5.1+dfsg/roms/seabios-hppa/Makefile-258- ; then echo "$(2)"; else echo "$(3)"; fi ;)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/scripts/checkstack.py-108-re_func = re.compile(r'^(?P<funcaddr>' + hex_s + r') <(?P<func>.*)>:$')
qemu-5.1+dfsg/roms/seabios-hppa/scripts/checkstack.py:109:re_asm = re.compile(
qemu-5.1+dfsg/roms/seabios-hppa/scripts/checkstack.py-110- r'^[ ]*(?P<insnaddr>' + hex_s
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/scripts/kconfig/streamline_config.pl-109- if (defined($conf->{"test"})) {
qemu-5.1+dfsg/roms/seabios-hppa/scripts/kconfig/streamline_config.pl:110: `$conf->{"test"} $conf->{"file"} 2>/dev/null`;
qemu-5.1+dfsg/roms/seabios-hppa/scripts/kconfig/streamline_config.pl-111- next if ($?);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/scripts/kconfig/streamline_config.pl-139-
qemu-5.1+dfsg/roms/seabios-hppa/scripts/kconfig/streamline_config.pl:140:my @makefiles = `find $ksource -name Makefile 2>/dev/null`;
qemu-5.1+dfsg/roms/seabios-hppa/scripts/kconfig/streamline_config.pl-141-chomp @makefiles;
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/scripts/test-build.sh-39-if [ $? -ne 0 ]; then
qemu-5.1+dfsg/roms/seabios-hppa/scripts/test-build.sh:40: echo "The version of LD on this system ($LD) does not properly handle" >&2
qemu-5.1+dfsg/roms/seabios-hppa/scripts/test-build.sh-41- echo "alignments. As a result, this project can not be built." >&2
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-87-static void
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c:88:pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64)
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-89-{
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-224- /* IDE: we map it as in ISA mode */
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c:225: pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c:226: pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE, 0);
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c:227: pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE, 0);
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c:228: pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE, 0);
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-229-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-241- /* PIC, IBM, MPIC & MPIC2 */
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c:242: pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-243-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-247- /* macio bridge */
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c:248: pci_set_io_region_addr(pci, 0, 0x80800000, 0);
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-249-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-1105-
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c:1106: pci_set_io_region_addr(entry->dev, entry->bar, addr, entry->is64);
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/pciinit.c-1107- return;
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/shadow.c-207-#if CONFIG_X86
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/shadow.c:208: asm volatile("int3");
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/shadow.c-209-#endif
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/smp.c-152- while (expected_cpus_count != CountCPUs)
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/smp.c:153: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/smp.c-154- // Release lock and allow other processors to use the stack.
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-14- long __res; \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h:15: asm volatile ( \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-16- "call *%%eax" \
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-26- long __res, __ign1; \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h:27: asm volatile ( \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-28- "call *%%eax" \
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-38- long __res, __ign1, __ign2; \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h:39: asm volatile ( \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-40- "call *%%eax" \
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-50- long __res, __ign1, __ign2, __ign3; \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h:51: asm volatile ( \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-52- "call *%%eax" \
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-64- long __res, __ign1, __ign2, __ign3, __ign4; \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h:65: asm volatile ( \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-66- "call *%%eax" \
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-78- long __res, __ign1, __ign2, __ign3, __ign4, __ign5; \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h:79: asm volatile ( \
qemu-5.1+dfsg/roms/seabios-hppa/src/fw/xen.h-80- "call *%%eax" \
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/gen-defs.h-7-#define DEFINE(sym, val) \
qemu-5.1+dfsg/roms/seabios-hppa/src/gen-defs.h:8: asm volatile("\n->" #sym " %0 " #val : : "i" (val))
qemu-5.1+dfsg/roms/seabios-hppa/src/gen-defs.h-9-
qemu-5.1+dfsg/roms/seabios-hppa/src/gen-defs.h-10-#define BLANK() \
qemu-5.1+dfsg/roms/seabios-hppa/src/gen-defs.h:11: asm volatile("\n->" : : )
qemu-5.1+dfsg/roms/seabios-hppa/src/gen-defs.h-12-
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/gen-defs.h-16-#define COMMENT(x) \
qemu-5.1+dfsg/roms/seabios-hppa/src/gen-defs.h:17: asm volatile("\n->#" x)
qemu-5.1+dfsg/roms/seabios-hppa/src/gen-defs.h-18-
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/hw/sdcard.c-67-#define SC_ALL_SEND_CID ((2<<8) | SCB_R136)
qemu-5.1+dfsg/roms/seabios-hppa/src/hw/sdcard.c:68:#define SC_SEND_RELATIVE_ADDR ((3<<8) | SCB_R48)
qemu-5.1+dfsg/roms/seabios-hppa/src/hw/sdcard.c-69-#define SC_SELECT_DESELECT_CARD ((7<<8) | SCB_R48b)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/mouse.c-295-
qemu-5.1+dfsg/roms/seabios-hppa/src/mouse.c:296: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/mouse.c-297- "pushl %%ebp\n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-31-
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:32:#define BOOTADDR(x) (x)
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-33-
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-123-#define CR_IVA 14
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:124: load32 BOOTADDR(smp_ivt),%r1
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-125- mtctl %r1, CR_IVA
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-143- /* on 64bit: Address of PDCE_PROC for each non-monarch processor in GR26. */
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:144: load32 BOOTADDR(pdc_entry), %r26
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-145-
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-154- /* Initialize stack pointer */
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:155: load32 BOOTADDR(parisc_stack),%r1
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-156- ldo FRAME_SIZE(%r1),%sp
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-164-
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:165: load32 BOOTADDR(_bss),%r3
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:166: load32 BOOTADDR(_ebss),%r4
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-167-$bss_loop:
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-171- /* Save boot args */
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:172: load32 BOOTADDR(boot_args),%r1
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-173- stw,ma %r26,4(%r1)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-180-
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:181: load32 BOOTADDR(start_parisc_firmware),%r3
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-182- bv 0(%r3)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-192- .align 32
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:193: load32 BOOTADDR($smp_exit_loop),%r1
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-194- bv 0(%r1)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-312- .import vga_post
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S:313: load32 BOOTADDR(vga_post), %r1
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/head.S-314- bv,n %r0(%r1)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-34- unsigned long flags;
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:35: asm volatile("ssm 0, %0" : "=r" (flags) : : "memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-36- return flags;
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-40-{
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:41: asm volatile("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-42-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-45-{
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:46: asm volatile("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-47-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-51- unsigned long flags;
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:52: asm volatile("rsm %1,%0" : "=r" (flags) : "i" (PSW_I) : "memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-53- return flags;
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-57-{
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:58: asm volatile("mtsm %0" : : "r" (flags) : "memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-59-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-84-{
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:85: asm volatile("nop": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-86-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-89-{
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:90: asm volatile("nop");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-91-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-96-{
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:97: asm volatile("sync": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-98-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-212-
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:213:#define pci_ioport_addr(port) ((port >= 0x1000) && (port < FIRMWARE_START))
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-214-
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-215-static inline void outl(u32 value, portaddr_t port) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:216: if (!pci_ioport_addr(port)) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-217- *(volatile u32 *)(port) = be32_to_cpu(value);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-226-static inline void outw(u16 value, portaddr_t port) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:227: if (!pci_ioport_addr(port)) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-228- *(volatile u16 *)(port) = be16_to_cpu(value);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-237-static inline void outb(u8 value, portaddr_t port) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:238: if (!pci_ioport_addr(port)) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-239- *(volatile u8 *)(port) = value;
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-248-static inline u8 inb(portaddr_t port) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:249: if (!pci_ioport_addr(port)) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-250- return *(volatile u8 *)(port);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-259-static inline u16 inw(portaddr_t port) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:260: if (!pci_ioport_addr(port)) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-261- return *(volatile u16 *)(port);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-269-static inline u32 inl(portaddr_t port) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:270: if (!pci_ioport_addr(port)) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-271- return *(volatile u32 *)(port);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-285- while (count--)
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:286: if (pci_ioport_addr(port))
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-287- *data++ = be16_to_cpu(inw(port));
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-292- while (count--)
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:293: if (pci_ioport_addr(port))
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-294- *data++ = be32_to_cpu(inl(port));
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-304- while (count--) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:305: if (pci_ioport_addr(port))
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-306- outw(cpu_to_be16(*data), port);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-313- while (count--) {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h:314: if (pci_ioport_addr(port))
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/hppa.h-315- outl(cpu_to_be32(*data), port);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c-142- printf("SeaBIOS wants SYSTEM HALT.\n\n");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c:143: asm volatile("\t.word 0xfffdead0": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c-144- while (1);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c-153- PAGE0->imm_soft_boot = 1;
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c:154: asm volatile("\t.word 0xfffdead1": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c-155- while (1);
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c-168- {
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c:169: asm volatile("fdc 0(%0)" : : "r" (start));
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c:170: asm volatile("fic 0(%%sr0,%0)" : : "r" (start));
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c-171- start += 16;
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c-172- } while (start < end);
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c:173: asm volatile("fdc 0(%0)" : : "r" (end));
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c-174-
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c:175: asm ("sync");
qemu-5.1+dfsg/roms/seabios-hppa/src/parisc/parisc.c-176-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-44- // resume execution by jump via 40h:0067h
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c:45: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-46- "movw %w1, %%ds\n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-53- // resume execution via IRET via 40h:0067h
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c:54: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-55- "movw %w1, %%ds\n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-63- // resume execution via RETF via 40h:0067h
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c:64: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-65- "movw %w1, %%ds\n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-76- // Not a 16bit resume - do remaining checks in 32bit mode
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c:77: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-78- "movw %w1, %%ss\n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-140- // Try triple fault
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c:141: asm volatile("int3");
qemu-5.1+dfsg/roms/seabios-hppa/src/resume.c-142-
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-61-static u16
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c:62:getComAddr(struct bregs *regs)
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-63-{
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-77-{
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c:78: u16 addr = getComAddr(regs);
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-79- if (!addr)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-99-{
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c:100: u16 addr = getComAddr(regs);
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-101- if (!addr)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-126-{
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c:127: u16 addr = getComAddr(regs);
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-128- if (!addr)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-152-{
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c:153: u16 addr = getComAddr(regs);
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-154- if (!addr)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-222-static u16
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c:223:getLptAddr(struct bregs *regs)
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-224-{
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-238-{
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c:239: u16 addr = getLptAddr(regs);
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-240- if (!addr)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-272-{
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c:273: u16 addr = getLptAddr(regs);
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-274- if (!addr)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-289-{
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c:290: u16 addr = getLptAddr(regs);
qemu-5.1+dfsg/roms/seabios-hppa/src/serial.c-291- if (!addr)
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-154- u32 bkup_esp;
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:155: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-156- // Backup esp / set esp to flat stack location
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-202- u32 stackoffset = Call16Data.ss << 4;
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:203: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-204- // Restore esp
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-249- u32 bkup_ss, bkup_esp;
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:250: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-251- // Backup ss/esp / set esp to flat stack location
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-294- u32 stackseg = Call16Data.ss;
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:295: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-296- // Transition to 16bit mode
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-344- u32 bkup_ss, bkup_esp;
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:345: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-346- // Backup current %ss/%esp values.
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-379- u32 bkup_stack_pos, temp;
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:380: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-381- // Backup stack_pos and current %ss/%esp
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-417- ASSERT16();
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:418: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-419- "calll __farcall16\n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-527- return;
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:528: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-529- " pushl $1f\n" // store return pc
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-567- hlist_add_after(&thread->node, &cur->node);
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:568: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-569- // Start thread
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-613- clock_poll_irq();
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:614: asm volatile("sti ; nop ; rep ; nop ; cli ; cld" : : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-615-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-640- }
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c:641: asm volatile("sti ; hlt ; cli ; cld": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/stacks.c-642-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/system.c-110- u16 count = regs->cx, si = 0, di = 0;
qemu-5.1+dfsg/roms/seabios-hppa/src/system.c:111: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/system.c-112- // Load new descriptor tables
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/system.c-202-
qemu-5.1+dfsg/roms/seabios-hppa/src/system.c:203: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/src/system.c-204- // Load new descriptor tables
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:1:// Basic x86 asm functions.
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-2-#ifndef __X86_H
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-28-{
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:29: asm volatile("cli": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-30-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-33-{
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:34: asm volatile("sti": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-35-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-39- u32 flags;
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:40: asm volatile("pushfl ; popl %0" : "=rm" (flags));
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-41- return flags;
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-45-{
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:46: asm volatile("pushl %0 ; popfl" : : "g" (flags) : "memory", "cc");
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-47-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-50-{
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:51: asm volatile("rep ; nop": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-52-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-55-{
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:56: asm volatile("nop");
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-57-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-60-{
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:61: asm volatile("hlt": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-62-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-65-{
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:66: asm volatile("wbinvd": : :"memory");
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-67-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-100- u64 ret;
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:101: asm ("rdmsr" : "=A"(ret) : "c"(index));
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-102- return ret;
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-106-{
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:107: asm volatile ("wrmsr" : : "c"(index), "A"(val));
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-108-}
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-112- u64 val;
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:113: asm volatile("rdtsc" : "=A" (val));
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-114- return val;
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-139- u32 res;
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:140: asm volatile("roll %%cl, %%eax"
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-141- : "=a" (res) : "a" (val), "c" (rol));
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-170-static inline void insb(u16 port, u8 *data, u32 count) {
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:171: asm volatile("rep insb (%%dx), %%es:(%%edi)"
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-172- : "+c"(count), "+D"(data) : "d"(port) : "memory");
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-174-static inline void insw(u16 port, u16 *data, u32 count) {
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:175: asm volatile("rep insw (%%dx), %%es:(%%edi)"
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-176- : "+c"(count), "+D"(data) : "d"(port) : "memory");
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-178-static inline void insl(u16 port, u32 *data, u32 count) {
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:179: asm volatile("rep insl (%%dx), %%es:(%%edi)"
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-180- : "+c"(count), "+D"(data) : "d"(port) : "memory");
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-183-static inline void outsb(u16 port, u8 *data, u32 count) {
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:184: asm volatile("rep outsb %%es:(%%esi), (%%dx)"
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-185- : "+c"(count), "+S"(data) : "d"(port) : "memory");
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-187-static inline void outsw(u16 port, u16 *data, u32 count) {
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:188: asm volatile("rep outsw %%es:(%%esi), (%%dx)"
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-189- : "+c"(count), "+S"(data) : "d"(port) : "memory");
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-191-static inline void outsl(u16 port, u32 *data, u32 count) {
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h:192: asm volatile("rep outsl %%es:(%%esi), (%%dx)"
qemu-5.1+dfsg/roms/seabios-hppa/src/x86.h-193- : "+c"(count), "+S"(data) : "d"(port) : "memory");
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c-26- union u64_u32_u val;
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c:27: asm __volatile__ (
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c-28- "movw $0x0AC1C, %%dx \n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c-51-
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c:52: asm __volatile__ (
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c-53- "push %%eax \n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c-68- u32 val;
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c:69: asm __volatile__ (
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c-70- "movw $0x0AC1C, %%dx \n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c-84-{
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c:85: asm __volatile__ (
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/geodevga.c-86- "movw $0x0AC1C, %%dx \n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/vgafb.c-213- SET_SEG(ES, GET_SEG(SS));
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/vgafb.c:214: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/vgafb.c-215- "stc\n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/vgainit.c-64- size >>= 4;
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/vgainit.c:65: asm volatile(
qemu-5.1+dfsg/roms/seabios-hppa/vgasrc/vgainit.c-66- "pushl %0\n"
##############################################
qemu-5.1+dfsg/roms/seabios-hppa/Makefile.parisc-62-# Default compiler flags
qemu-5.1+dfsg/roms/seabios-hppa/Makefile.parisc:63:cc-option=$(shell if test -z "`$(1) $(2) -S -o /dev/null -xc /dev/null 2>&1`" \
qemu-5.1+dfsg/roms/seabios-hppa/Makefile.parisc-64- ; then echo "$(2)"; else echo "$(3)"; fi ;)
##############################################
qemu-5.1+dfsg/roms/skiboot/asm/asm-offsets.c-25-#define DEFINE(sym, val) \
qemu-5.1+dfsg/roms/skiboot/asm/asm-offsets.c:26: asm volatile("\n#define " #sym " %0 /* " #val " */" : : "i" (val))
qemu-5.1+dfsg/roms/skiboot/asm/asm-offsets.c-27-
##############################################
qemu-5.1+dfsg/roms/skiboot/asm/Makefile.inc-2-
qemu-5.1+dfsg/roms/skiboot/asm/Makefile.inc:3:SUBDIRS += asm
qemu-5.1+dfsg/roms/skiboot/asm/Makefile.inc-4-ASM_OBJS = head.o misc.o kernel-wrapper.o cvc_entry.o
##############################################
qemu-5.1+dfsg/roms/skiboot/ccan/Makefile.check-21- $(eval LCOV_DIRS += -d $(dir $<) )
qemu-5.1+dfsg/roms/skiboot/ccan/Makefile.check:22: $(call Q, TEST-COVERAGE , (cd $(dir $<); GCOV_PREFIX_STRIP=`(c=0; while [ "\`pwd\`" != '/' ]; do cd ..; c=\`expr 1 + $$c\`; done; echo $$c)` ./$(notdir $<) ), $< )
qemu-5.1+dfsg/roms/skiboot/ccan/Makefile.check-23-
##############################################
qemu-5.1+dfsg/roms/skiboot/core/console.c-78-
qemu-5.1+dfsg/roms/skiboot/core/console.c:79: con = dt_new_addr(consoles, "serial", index);
qemu-5.1+dfsg/roms/skiboot/core/console.c-80- assert(con);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/cpu.c-36-/* The cpu_threads array is static and indexed by PIR in
qemu-5.1+dfsg/roms/skiboot/core/cpu.c:37: * order to speed up lookup from asm entry points
qemu-5.1+dfsg/roms/skiboot/core/cpu.c-38- */
##############################################
qemu-5.1+dfsg/roms/skiboot/core/cpu.c-97- smt_lowest();
qemu-5.1+dfsg/roms/skiboot/core/cpu.c:98: asm volatile("nop; nop; nop; nop;\n"
qemu-5.1+dfsg/roms/skiboot/core/cpu.c-99- "nop; nop; nop; nop;\n"
##############################################
qemu-5.1+dfsg/roms/skiboot/core/device.c-164- */
qemu-5.1+dfsg/roms/skiboot/core/device.c:165:struct dt_node *__dt_find_by_name_addr(struct dt_node *parent, const char *name,
qemu-5.1+dfsg/roms/skiboot/core/device.c-166- const char *addr)
##############################################
qemu-5.1+dfsg/roms/skiboot/core/device.c-190- dt_for_each_child(parent, node) {
qemu-5.1+dfsg/roms/skiboot/core/device.c:191: struct dt_node *ret = __dt_find_by_name_addr(node, name, addr);
qemu-5.1+dfsg/roms/skiboot/core/device.c-192-
##############################################
qemu-5.1+dfsg/roms/skiboot/core/device.c-199-
qemu-5.1+dfsg/roms/skiboot/core/device.c:200:struct dt_node *dt_find_by_name_addr(struct dt_node *parent, const char *name,
qemu-5.1+dfsg/roms/skiboot/core/device.c-201- uint64_t addr)
##############################################
qemu-5.1+dfsg/roms/skiboot/core/device.c-205-
qemu-5.1+dfsg/roms/skiboot/core/device.c:206: return __dt_find_by_name_addr(parent, name, addr_str);
qemu-5.1+dfsg/roms/skiboot/core/device.c-207-}
qemu-5.1+dfsg/roms/skiboot/core/device.c-208-
qemu-5.1+dfsg/roms/skiboot/core/device.c:209:struct dt_node *dt_new_addr(struct dt_node *parent, const char *name,
qemu-5.1+dfsg/roms/skiboot/core/device.c-210- uint64_t addr)
##############################################
qemu-5.1+dfsg/roms/skiboot/core/device.c-230-
qemu-5.1+dfsg/roms/skiboot/core/device.c:231:struct dt_node *dt_new_2addr(struct dt_node *parent, const char *name,
qemu-5.1+dfsg/roms/skiboot/core/device.c-232- uint64_t addr0, uint64_t addr1)
##############################################
qemu-5.1+dfsg/roms/skiboot/core/fast-reboot.c-233-
qemu-5.1+dfsg/roms/skiboot/core/fast-reboot.c:234: asm volatile("ba 0x100\n\t" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/core/fast-reboot.c-235- for (;;)
##############################################
qemu-5.1+dfsg/roms/skiboot/core/fast-reboot.c-327-
qemu-5.1+dfsg/roms/skiboot/core/fast-reboot.c:328:/* Entry from asm after a fast reset */
qemu-5.1+dfsg/roms/skiboot/core/fast-reboot.c-329-void __noreturn fast_reboot_entry(void);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/flash.c-232-
qemu-5.1+dfsg/roms/skiboot/core/flash.c:233: flash_node = dt_new_addr(opal_node, "flash", id);
qemu-5.1+dfsg/roms/skiboot/core/flash.c-234- dt_add_property_strings(flash_node, "compatible", "ibm,opal-flash");
##############################################
qemu-5.1+dfsg/roms/skiboot/core/flash.c-278-
qemu-5.1+dfsg/roms/skiboot/core/flash.c:279: partition_node = dt_new_addr(partition_container_node, "partition", ffs_part_start);
qemu-5.1+dfsg/roms/skiboot/core/flash.c-280- dt_add_property_strings(partition_node, "label", name);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/flash.c-290-
qemu-5.1+dfsg/roms/skiboot/core/flash.c:291: partition_node = dt_new_addr(partition_container_node, "partition", 0);
qemu-5.1+dfsg/roms/skiboot/core/flash.c-292- dt_add_property_strings(partition_node, "label", "PNOR");
##############################################
qemu-5.1+dfsg/roms/skiboot/core/interrupts.c-168-{
qemu-5.1+dfsg/roms/skiboot/core/interrupts.c:169: struct dt_node *ics = dt_new_addr(dt_root, "interrupt-controller", 0);
qemu-5.1+dfsg/roms/skiboot/core/interrupts.c-170- bool has_xive;
##############################################
qemu-5.1+dfsg/roms/skiboot/core/mem_region.c-1437-
qemu-5.1+dfsg/roms/skiboot/core/mem_region.c:1438: region->node = dt_new_addr(parent, name, region->start);
qemu-5.1+dfsg/roms/skiboot/core/mem_region.c-1439- assert(region->node);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-164-
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:165: addr1 = dt_new_addr(addrs, "addr", 0x1337);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-166- assert(!list_top(&addr1->properties, struct dt_property, list));
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-168- assert(dt_find_by_name(root, "addr@1337") == addr1);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:169: assert(dt_find_by_name_addr(root, "addr", 0x1337) == addr1);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-170- assert(dt_find_by_path(root, "/addrs/addr@1337") == addr1);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:171: assert(dt_new_addr(addrs, "addr", 0x1337) == NULL);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-172-
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:173: addr2 = dt_new_2addr(addrs, "2addr", 0xdead, 0xbeef);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-174- assert(!list_top(&addr2->properties, struct dt_property, list));
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-177- assert(dt_find_by_path(root, "/addrs/2addr@dead,beef") == addr2);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:178: assert(dt_new_2addr(addrs, "2addr", 0xdead, 0xbeef) == NULL);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-179-
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-420-
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:421: c1 = dt_new_addr(root, "some-32bit-bus", 0x80000000);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-422- dt_add_property_cells(c1, "#address-cells", 1);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-425-
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:426: gc1 = dt_new_addr(c1, "test", 0x0500);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-427- dt_add_property_cells(gc1, "reg", 0x0500, 0x10);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-432-
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:433: gc2 = dt_new_addr(c1, "another-32bit-bus", 0x40000000);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-434- dt_add_property_cells(gc2, "#address-cells", 1);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-438-
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:439: ggc1 = dt_new_addr(gc2, "test", 0x50);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-440- dt_add_property_cells(ggc1, "reg", 0x50, 0x10);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-443- /* test multiple ranges work */
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:444: ggc2 = dt_new_addr(gc2, "test", 0x150);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-445- dt_add_property_cells(ggc2, "reg", 0x150, 0x10);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-449-
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:450: c2 = dt_new_addr(root, "some-64bit-bus", 0xe00000000);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-451- dt_add_property_cells(c2, "#address-cells", 2);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-454-
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c:455: gc2 = dt_new_addr(c2, "test", 0x100000000ul);
qemu-5.1+dfsg/roms/skiboot/core/test/run-device.c-456- dt_add_property_u64s(gc2, "reg", 0x100000000ul, 0x10ul);
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-trace.c-39-{
qemu-5.1+dfsg/roms/skiboot/core/test/run-trace.c:40: asm volatile("mfence" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/core/test/run-trace.c-41-}
##############################################
qemu-5.1+dfsg/roms/skiboot/core/test/run-trace.c-45-{
qemu-5.1+dfsg/roms/skiboot/core/test/run-trace.c:46: asm volatile("lwsync" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/core/test/run-trace.c-47-}
##############################################
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-5.10-rc1.rst-845- cmpxchg will be used in a subsequent change, and this reduces the
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-5.10-rc1.rst:846: amount of asm code.
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-5.10-rc1.rst-847-- direct-controls: add xscom error handling for p8
##############################################
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-5.10.rst-1156- cmpxchg will be used in a subsequent change, and this reduces the
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-5.10.rst:1157: amount of asm code.
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-5.10.rst-1158-- direct-controls: add xscom error handling for p8
##############################################
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-6.3-rc3.rst-132- std r0,PPC_STK_LROFF(r1)
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-6.3-rc3.rst:133: LOAD_REG_ADDR(r11, opal_return)
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-6.3-rc3.rst-134- mtlr r11
##############################################
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-6.3.rst-426- std r0,PPC_STK_LROFF(r1)
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-6.3.rst:427: LOAD_REG_ADDR(r11, opal_return)
qemu-5.1+dfsg/roms/skiboot/doc/release-notes/skiboot-6.3.rst-428- mtlr r11
##############################################
qemu-5.1+dfsg/roms/skiboot/external/boot-tests/boot_test.sh-246- firmware_supplied=1;
qemu-5.1+dfsg/roms/skiboot/external/boot-tests/boot_test.sh:247: arbitrary_lid[0]=`echo "$OPTARG" | cut -s -f1 -d:`;
qemu-5.1+dfsg/roms/skiboot/external/boot-tests/boot_test.sh:248: arbitrary_lid[1]=`echo "$OPTARG" | cut -s -f2 -d:`;
qemu-5.1+dfsg/roms/skiboot/external/boot-tests/boot_test.sh-249- if [ -z "${arbitrary_lid[0]}" -o -z "${arbitrary_lid[1]}" ] ; then
##############################################
qemu-5.1+dfsg/roms/skiboot/external/boot-tests/fsp_support.sh-125- while [ \( "$state" != "runtime" \) -a \( "$i" -lt "$BOOT_TIMEOUT" \) ] ; do
qemu-5.1+dfsg/roms/skiboot/external/boot-tests/fsp_support.sh:126: msg "Waiting $BOOT_SLEEP_PERIOD more seconds (istep: `grep iStep $ISTEP_LOG|tail -n 1`)";
qemu-5.1+dfsg/roms/skiboot/external/boot-tests/fsp_support.sh-127- sleep "$BOOT_SLEEP_PERIOD";
##############################################
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-31-{
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h:32: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-33- return *(volatile uint8_t *)addr;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-37-{
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h:38: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-39- return *(volatile uint16_t *)addr;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-43-{
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h:44: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-45- return *(volatile uint32_t *)addr;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-49-{
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h:50: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-51- *(volatile uint8_t *)addr = val;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-55-{
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h:56: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-57- *(volatile uint16_t *)addr = val;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-61-{
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h:62: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/external/common/arch_flash_arm_io.h-63- *(volatile uint32_t *)addr = val;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/gard/gard.c-154- /* grab the chip type from the PVR SPR */
qemu-5.1+dfsg/roms/skiboot/external/gard/gard.c:155: asm ("mfspr %0,0x11f" : "=r" (pvr));
qemu-5.1+dfsg/roms/skiboot/external/gard/gard.c-156-
##############################################
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-49- register unsigned long a2 asm("r5") = arg2;
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c:50: asm volatile (".long 0x000eaeb0":"=r" (c):"r"(c), "r"(a1), "r"(a2));
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-51- return (c);
##############################################
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-60- register unsigned long a3 asm("r6") = arg3;
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c:61: asm volatile (".long 0x000eaeb0":"=r" (c):"r"(c), "r"(a1), "r"(a2),
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-62- "r"(a3));
##############################################
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-73- register unsigned long a4 asm("r7") = arg4;
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c:74: asm volatile (".long 0x000eaeb0":"=r" (c):"r"(c), "r"(a1), "r"(a2),
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-75- "r"(a3), "r"(a4));
##############################################
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-87- register unsigned long a5 asm("r8") = arg5;
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c:88: asm volatile (".long 0x000eaeb0":"=r" (c):"r"(c), "r"(a1), "r"(a2),
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-89- "r"(a3), "r"(a4), "r"(a5));
##############################################
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-330- ser.sin_port = htons(sim_port);
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c:331: ser.sin_addr.s_addr = inet_addr("127.0.0.1");
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo-socket-proxy.c-332- memset(ser.sin_zero, '\0', sizeof ser.sin_zero);
##############################################
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo_utils.tcl-123- set inst [mysim cpu $p:$c:$t memory display $pc_laddr 4]
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo_utils.tcl:124: set disasm [mysim cpu $p:$c:$t util ppc_disasm $inst $pc]
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo_utils.tcl-125- return "\[$p:$c:$t\]: $pc ($pc_laddr) Enc:$inst : $disasm"
##############################################
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo_utils.tcl-535- set inst [mysim cpu $p:$c:$t memory display $pc_laddr 4]
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo_utils.tcl:536: set disasm [mysim cpu $p:$c:$t util ppc_disasm $inst $pc]
qemu-5.1+dfsg/roms/skiboot/external/mambo/mambo_utils.tcl-537- return $disasm
##############################################
qemu-5.1+dfsg/roms/skiboot/external/memboot/memboot.c-42-{
qemu-5.1+dfsg/roms/skiboot/external/memboot/memboot.c:43: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/external/memboot/memboot.c-44- return *(volatile uint32_t *)addr;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/memboot/memboot.c-48-{
qemu-5.1+dfsg/roms/skiboot/external/memboot/memboot.c:49: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/external/memboot/memboot.c-50- *(volatile uint32_t *)addr = val;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/opal-prd/opal-prd.c-1978- case CONTROL_MSG_HTMGT_PASSTHRU:
qemu-5.1+dfsg/roms/skiboot/external/opal-prd/opal-prd.c:1979: handle_prd_control_htmgt_passthru(send_msg, recv_msg);
qemu-5.1+dfsg/roms/skiboot/external/opal-prd/opal-prd.c-1980- break;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/opal-prd/opal-prd.c-2423-
qemu-5.1+dfsg/roms/skiboot/external/opal-prd/opal-prd.c:2424:static int send_htmgt_passthru(struct opal_prd_ctx *ctx, int argc, char *argv[])
qemu-5.1+dfsg/roms/skiboot/external/opal-prd/opal-prd.c-2425-{
##############################################
qemu-5.1+dfsg/roms/skiboot/external/opal-prd/opal-prd.c-2700-
qemu-5.1+dfsg/roms/skiboot/external/opal-prd/opal-prd.c:2701: rc = send_htmgt_passthru(ctx, argc - optind, &argv[optind]);
qemu-5.1+dfsg/roms/skiboot/external/opal-prd/opal-prd.c-2702- break;
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-66-
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py:67: def mangle_addr(self, addr):
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-68- tmp = (addr & 0xf000000000000000) >> 4
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-81-
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py:82: saddr = self.mangle_addr(addr)
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-83- fd = self.key_val_bin.get(chip_id)
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-95-
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py:96: saddr = self.mangle_addr(addr)
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-97- fd = self.key_val_bin.get(chip_id)
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-114- c = struct.pack('Q',val)
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py:115: saddr = self.mangle_addr(addr)
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-116- fd = self.key_val_bin.get(chip_id)
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-159-
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py:160: def set_addr(self, scom_addr):
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-161- self.addr = scom_addr
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-262-
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py:263: def set_addr(self, addr):
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/adu_scoms.py-264- self.addr = addr
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/sram.c-49-
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/sram.c:50: asm volatile("mfpvr %0" : "=r" (pvr));
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/sram.c-51-
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/xscom.c-131-
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/xscom.c:132:static uint64_t xscom_mangle_addr(uint64_t addr)
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/xscom.c-133-{
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/xscom.c-154- return -ENODEV;
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/xscom.c:155: addr = xscom_mangle_addr(addr);
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/xscom.c-156- lseek64(c->fd, addr, SEEK_SET);
##############################################
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/xscom.c-171- return -ENODEV;
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/xscom.c:172: addr = xscom_mangle_addr(addr);
qemu-5.1+dfsg/roms/skiboot/external/xscom-utils/xscom.c-173- lseek64(c->fd, addr, SEEK_SET);
##############################################
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-117-
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c:118:static inline const char* SKIBOOT_ADDR(const char* addr, const void* p)
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-119-{
##############################################
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-131-{
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c:132: const char* filename = SKIBOOT_ADDR(addr, gi->filename);
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-133- int fd;
##############################################
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-157- functions = (struct gcov_fn_info**)
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c:158: SKIBOOT_ADDR(addr, gi->functions);
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-159-
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-160- fn_info = (struct gcov_fn_info*)
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c:161: SKIBOOT_ADDR(addr, functions[fn]);
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-162-
##############################################
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-184- gcov_type *ctrv = (gcov_type *)
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c:185: SKIBOOT_ADDR(addr, ctr_info->values);
qemu-5.1+dfsg/roms/skiboot/extract-gcov.c-186- //printf("%lx\n", be64toh(ctrv[cv]));
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/cpu-common.c-102-
qemu-5.1+dfsg/roms/skiboot/hdata/cpu-common.c:103: cpu = dt_new_addr(cpus, name, int_server);
qemu-5.1+dfsg/roms/skiboot/hdata/cpu-common.c-104- assert(cpu);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/cpu-common.c-217-
qemu-5.1+dfsg/roms/skiboot/hdata/cpu-common.c:218: node = dt_new_addr(cpus, name, unit_addr);
qemu-5.1+dfsg/roms/skiboot/hdata/cpu-common.c-219- assert(node);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-118-
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c:119: node = dt_new_addr(parent, "fsp", i);
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-120- assert(node);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-343- for (i = 0; i < be32_to_cpu(ipmi_sensors->count); i++) {
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c:344: if(dt_find_by_name_addr(sensors_node, "sensor",
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-345- ipmi_sensors->data[i].id)) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-354-
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c:355: sensor_node = dt_new_addr(sensors_node, "sensor",
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-356- ipmi_sensors->data[i].id);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-414- phys_map_get(chip_id, LPC_BUS, 0, &lpcm_base, NULL);
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c:415: lpcm = dt_new_addr(dt_root, "lpcm-opb", lpcm_base);
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-416- assert(lpcm);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-455- /* Add the various internal bus devices */
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c:456: n = dt_new_addr(lpcm, "opb-master", internal_bar + 0x10000);
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-457- dt_add_property_string(n, "compatible", "ibm,power9-lpcm-opb-master");
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-459-
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c:460: n = dt_new_addr(lpcm, "opb-arbiter", internal_bar + 0x11000);
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-461- dt_add_property_string(n, "compatible", "ibm,power9-lpcm-opb-arbiter");
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-463-
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c:464: n = dt_new_addr(lpcm, "lpc-controller", internal_bar + 0x12000);
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-465- dt_add_property_string(n, "compatible", "ibm,power9-lpc-controller");
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-471- */
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c:472: lpc = dt_new_addr(lpcm, "lpc", 0x0);
qemu-5.1+dfsg/roms/skiboot/hdata/fsp.c-473- dt_add_property_cells(lpc, "#address-cells", 2);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c-51-
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c:52: i2cm = dt_find_by_name_addr(xscom, "i2cm", xscom_base);
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c-53- if (!i2cm) {
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c:54: i2cm = dt_new_addr(xscom, "i2cm", xscom_base);
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c-55- dt_add_property_cells(i2cm, "reg", xscom_base,
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c-79-
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c:80: bus = dt_find_by_name_addr(i2cm, "i2c-bus", port);
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c-81- if (!bus) {
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c:82: bus = dt_new_addr(i2cm, "i2c-bus", port);
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c-83- dt_add_property_cells(bus, "reg", port);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c-344-
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c:345: node = dt_new_addr(bus, name, dev_addr);
qemu-5.1+dfsg/roms/skiboot/hdata/i2c.c-346- if (!node)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-117- /* Create PBCQ node under xscom */
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c:118: pbcq = dt_new_addr(xcom, "pbcq", pe_xscom);
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-119- if (!pbcq)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-174-
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c:175: stack = dt_new_addr(pbcq, "stack", stack_index);
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-176- assert(stack);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-224- /* Create PBCQ node under xscom */
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c:225: pbcq = dt_new_addr(xcom, "pbcq", pe_xscom);
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-226- if (!pbcq)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-572- case st_rc_slot:
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c:573: node = dt_new_2addr(dt_slots, "root-complex",
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-574- chip_id, entry->phb_index);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-614- if (type == st_sw_upstream && vid && did) {
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c:615: node = dt_new_2addr(parent, st_name(type), vid, did);
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-616- dt_add_property_cells(node, "reg", vid, did);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-633- case st_sw_downstream: /* slot connected to switch output */
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c:634: node = dt_new_addr(parent, "down-port", entry->down_port);
qemu-5.1+dfsg/roms/skiboot/hdata/iohub.c-635- dt_add_property_strings(node, "compatible",
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-153- /* reg contains start and length */
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:154: reg[0] = cleanup_addr(be64_to_cpu(arange->start));
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:155: reg[1] = cleanup_addr(be64_to_cpu(arange->end)) - reg[0];
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-156-
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-179- if (be16_to_cpu(id->flags) & MS_AREA_SHARED) {
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:180: mem = dt_find_by_name_addr(dt_root, name, reg[0]);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-181- if (mem) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-188-
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:189: mem = dt_new_addr(root, name, reg[0]);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-190- if (compat)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-411- /* Use Resource ID to add dimm node */
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:412: dimm = dt_find_by_name_addr(mca, "dimm",
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-413- be16_to_cpu(fru_id->rsrc_id));
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-415- continue;
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:416: dimm= dt_new_addr(mca, "dimm", be16_to_cpu(fru_id->rsrc_id));
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-417- assert(dimm);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-481- mcbist_id = MS_CONTROLLER_MCBIST_ID(controller_id);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:482: mcbist = dt_find_by_name_addr(xscom, "mcbist", mcbist_id);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-483- if (!mcbist) {
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:484: mcbist = dt_new_addr(xscom, "mcbist", mcbist_id);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-485- assert(mcbist);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-491- mcs_id = MS_CONTROLLER_MCS_ID(controller_id);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:492: mcs = dt_find_by_name_addr(mcbist, "mcs", mcs_id);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-493- if (!mcs) {
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:494: mcs = dt_new_addr(mcbist, "mcs", mcs_id);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-495- assert(mcs);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-499- mca_id = MS_CONTROLLER_MCA_ID(controller_id);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:500: mca = dt_find_by_name_addr(mcs, "mca", mca_id);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-501- if (!mca) {
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:502: mca = dt_new_addr(mcs, "mca", mca_id);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-503- assert(mca);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-639-
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c:640: node = dt_new_addr(dt_hb_reserves, node_name, start);
qemu-5.1+dfsg/roms/skiboot/hdata/memory.c-641- if (!node) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/paca.c-171- continue;
qemu-5.1+dfsg/roms/skiboot/hdata/paca.c:172: ibase = cleanup_addr(be64_to_cpu(id->ibase));
qemu-5.1+dfsg/roms/skiboot/hdata/paca.c-173- found = true;
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/paca.c-181-
qemu-5.1+dfsg/roms/skiboot/hdata/paca.c:182: icp = dt_new_addr(dt_root, "interrupt-controller", ibase);
qemu-5.1+dfsg/roms/skiboot/hdata/paca.c-183- if (!icp)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/paca.c-215- prerror("Invalid PACA (PCIA = %p)\n",
qemu-5.1+dfsg/roms/skiboot/hdata/paca.c:216: ntuple_addr(&spira.ntuples.pcia));
qemu-5.1+dfsg/roms/skiboot/hdata/paca.c-217- return false;
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/pcia.c-75- irange[0] = be32_to_cpu(t->pir);
qemu-5.1+dfsg/roms/skiboot/hdata/pcia.c:76: reg[i * 2] = cpu_to_be64(cleanup_addr(be64_to_cpu(t->ibase)));
qemu-5.1+dfsg/roms/skiboot/hdata/pcia.c-77- reg[i * 2 + 1] = cpu_to_be64(0x1000);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/pcia.c-80-
qemu-5.1+dfsg/roms/skiboot/hdata/pcia.c:81: icp = dt_new_addr(dt_root, "interrupt-controller", be64_to_cpu(reg[0]));
qemu-5.1+dfsg/roms/skiboot/hdata/pcia.c-82- if (!icp) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-216-{
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:217: struct HDIF_common_hdr *h = ntuple_addr(n);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-218- u16 act_cnt, alloc_cnt;
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-275-
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:276: node = dt_new_addr(dt_root, "xscom", addr);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-277- if (!node)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-388-
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:389: psi_np = dt_new_addr(np, "psihb", psi_scom);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-390- if (!psi_np)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-400-{
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:401: struct dt_node *xive = dt_new_addr(np, "xive", 0x5013000);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-402-
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-416-{
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:417: struct dt_node *vas = dt_new_addr(np, "vas", VAS_SCOM_BASE_ADDR);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-418-
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-654- /* Get rid of the top bits */
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:655: xscom_base = cleanup_addr(xscom_base);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-656-
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-695-
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:696: node = dt_new_addr(xscom_node, "chiptod", addr);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-697- if (!node)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-815-
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:816: nx = dt_new_addr(xscom, "nx", addr);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-817- if (!nx)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-871- dt_for_each_compatible(dt_root, xscom, "ibm,xscom") {
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:872: nmmu = dt_new_addr(xscom, "nmmu", 0x5012c40);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-873- dt_add_property_strings(nmmu, "compatible", "ibm,power9-nest-mmu");
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-1020-
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:1021: /* On an ASM initiated factory reset, this bit will be set
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-1022- * and the FSP expects the firmware to reset the PCI bus
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-1079- i, rsrc_id, ipser->loc_code);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:1080: ser_node = dt_new_addr(node, "serial", rsrc_id);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-1081- if (!ser_node)
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-1356-
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:1357: npu = dt_new_addr(xscom, "npu", NPU_BASE);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-1358- dt_add_property_cells(npu, "reg", NPU_BASE, NPU_SIZE);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-1408-
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c:1409: node = dt_new_addr(npu, "link", link_count);
qemu-5.1+dfsg/roms/skiboot/hdata/spira.c-1410- if (!node) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.h-189- for (_p = get_hdif((_ntuples), _id ""); \
qemu-5.1+dfsg/roms/skiboot/hdata/spira.h:190: _p && (void *)_p < ntuple_addr(_ntuples) \
qemu-5.1+dfsg/roms/skiboot/hdata/spira.h-191- + (be16_to_cpu((_ntuples)->act_cnt) * \
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/spira.h-201-#ifndef ntuple_addr
qemu-5.1+dfsg/roms/skiboot/hdata/spira.h:202:#define ntuple_addr(_ntuples) ((void *)BE64_TO_CPU((_ntuples)->addr))
qemu-5.1+dfsg/roms/skiboot/hdata/spira.h-203-#endif
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/test/hdata_to_dt.c-46-struct spira_ntuple;
qemu-5.1+dfsg/roms/skiboot/hdata/test/hdata_to_dt.c:47:static void *ntuple_addr(const struct spira_ntuple *n);
qemu-5.1+dfsg/roms/skiboot/hdata/test/hdata_to_dt.c-48-
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/test/hdata_to_dt.c-197-
qemu-5.1+dfsg/roms/skiboot/hdata/test/hdata_to_dt.c:198:static void *ntuple_addr(const struct spira_ntuple *n)
qemu-5.1+dfsg/roms/skiboot/hdata/test/hdata_to_dt.c-199-{
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/test/hdata_to_dt.c-203- if (addr < base_addr) {
qemu-5.1+dfsg/roms/skiboot/hdata/test/hdata_to_dt.c:204: fprintf(stderr, "assert failed: addr >= base_addr (%"PRIu64" >= %"PRIu64")\n", addr, base_addr);
qemu-5.1+dfsg/roms/skiboot/hdata/test/hdata_to_dt.c-205- exit(EXIT_FAILURE);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/tpmrel.c-209-
qemu-5.1+dfsg/roms/skiboot/hdata/tpmrel.c:210: node = dt_new_addr(parent, "ibm,cvc-service", offset);
qemu-5.1+dfsg/roms/skiboot/hdata/tpmrel.c-211- dt_add_property_strings(node, "compatible", compat);
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c-466- /* Check node is already created or not */
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c:467: if (dt_find_by_name_addr(dt_vpd, name, addr))
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c-468- goto next_entry;
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c-478- p_addr = be16_to_cpu(p_entry->rsrc_id);
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c:479: parent = dt_find_by_name_addr(dt_vpd, p_name, p_addr);
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c-480- }
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c-483-
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c:484: node = dt_new_addr(parent, name, addr);
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c-485- if (!node) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c-534- /* Get the node already created */
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c:535: node = dt_find_by_name_addr(dt_vpd, name, addr);
qemu-5.1+dfsg/roms/skiboot/hdata/vpd.c-536- /*
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/ast-bmc/ast-sf-ctrl.c-180-
qemu-5.1+dfsg/roms/skiboot/hw/ast-bmc/ast-sf-ctrl.c:181:static int ast_sf_send_addr(struct ast_sf_ctrl *ct, uint32_t addr)
qemu-5.1+dfsg/roms/skiboot/hw/ast-bmc/ast-sf-ctrl.c-182-{
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/ast-bmc/ast-sf-ctrl.c-207- if (has_addr) {
qemu-5.1+dfsg/roms/skiboot/hw/ast-bmc/ast-sf-ctrl.c:208: rc = ast_sf_send_addr(ct, addr);
qemu-5.1+dfsg/roms/skiboot/hw/ast-bmc/ast-sf-ctrl.c-209- if (rc)
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/ast-bmc/ast-sf-ctrl.c-229- if (has_addr) {
qemu-5.1+dfsg/roms/skiboot/hw/ast-bmc/ast-sf-ctrl.c:230: rc = ast_sf_send_addr(ct, addr);
qemu-5.1+dfsg/roms/skiboot/hw/ast-bmc/ast-sf-ctrl.c-231- if (rc)
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/fsp/fsp-op-panel.c-222- * HTML/Javascript through the Operator Panel.
qemu-5.1+dfsg/roms/skiboot/hw/fsp/fsp-op-panel.c:223: * You get to inject it into the ASM web ui!
qemu-5.1+dfsg/roms/skiboot/hw/fsp/fsp-op-panel.c-224- * So we filter out anything suspect here,
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/ipmi/ipmi-sel.c-545-
qemu-5.1+dfsg/roms/skiboot/hw/ipmi/ipmi-sel.c:546: node = dt_find_by_name_addr(sensors_node, "sensor", sensor);
qemu-5.1+dfsg/roms/skiboot/hw/ipmi/ipmi-sel.c-547- if (!node) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c-669-
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:670: mem = dt_find_by_name_addr(dt_root, "memory", addr);
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c-671- if (mem)
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c-673-
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:674: mem = dt_new_addr(dt_root, "memory", addr);
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c-675- if (!mem)
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c-1617- /* Populate PCI root device node */
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:1618: np = dt_new_addr(dt_root, "pciex", reg[0]);
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c-1619- assert(np);
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c-1992- dt_add_property_u64s(np, "ibm,mmio-atsd",
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:1993: MMIO_ATSD_ADDR(p->regs, 0),
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:1994: MMIO_ATSD_ADDR(p->regs, 1),
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:1995: MMIO_ATSD_ADDR(p->regs, 2),
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:1996: MMIO_ATSD_ADDR(p->regs, 3),
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:1997: MMIO_ATSD_ADDR(p->regs, 4),
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:1998: MMIO_ATSD_ADDR(p->regs, 5),
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:1999: MMIO_ATSD_ADDR(p->regs, 6),
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c:2000: MMIO_ATSD_ADDR(p->regs, 7));
qemu-5.1+dfsg/roms/skiboot/hw/npu2.c-2001-
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu2-common.c-35- */
qemu-5.1+dfsg/roms/skiboot/hw/npu2-common.c:36:static void npu2_scom_set_addr(uint64_t gcid, uint64_t scom_base,
qemu-5.1+dfsg/roms/skiboot/hw/npu2-common.c-37- uint64_t addr, uint64_t size)
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu2-common.c-47-{
qemu-5.1+dfsg/roms/skiboot/hw/npu2-common.c:48: npu2_scom_set_addr(gcid, scom_base, reg, size);
qemu-5.1+dfsg/roms/skiboot/hw/npu2-common.c-49- xscom_write(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_DATA, val);
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu2-common.c-56-
qemu-5.1+dfsg/roms/skiboot/hw/npu2-common.c:57: npu2_scom_set_addr(gcid, scom_base, reg, size);
qemu-5.1+dfsg/roms/skiboot/hw/npu2-common.c-58- xscom_read(gcid, scom_base + NPU2_MISC_SCOM_IND_SCOM_DATA, &val);
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu2-opencapi.c-1663- mm_win[0], mm_win[1]);
qemu-5.1+dfsg/roms/skiboot/hw/npu2-opencapi.c:1664: dn_phb = dt_new_addr(dt_root, "pciex", mm_win[0]);
qemu-5.1+dfsg/roms/skiboot/hw/npu2-opencapi.c-1665- assert(dn_phb);
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu.c-1137- /* Create PCI root device node */
qemu-5.1+dfsg/roms/skiboot/hw/npu.c:1138: np = dt_new_addr(dt_root, "pciex", at_bar[0]);
qemu-5.1+dfsg/roms/skiboot/hw/npu.c-1139- assert(np);
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu.c-1587- * which is to do a TCE kill all instead. */
qemu-5.1+dfsg/roms/skiboot/hw/npu.c:1588: tkill = cleanup_addr((uint64_t)p->at_regs) + NPU_TCE_KILL;
qemu-5.1+dfsg/roms/skiboot/hw/npu.c-1589- dt_add_property_cells(np, "ibm,opal-num-pes",
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu-hw-procedures.c-53- else
qemu-5.1+dfsg/roms/skiboot/hw/npu-hw-procedures.c:54: out_be16((void *) npu_dev->pl_base + PL_MMIO_ADDR(addr), val);
qemu-5.1+dfsg/roms/skiboot/hw/npu-hw-procedures.c-55-}
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/npu-hw-procedures.c-63- else
qemu-5.1+dfsg/roms/skiboot/hw/npu-hw-procedures.c:64: val = in_be16((void *) npu_dev->pl_base + PL_MMIO_ADDR(addr));
qemu-5.1+dfsg/roms/skiboot/hw/npu-hw-procedures.c-65-
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/nx-rng.c-124-
qemu-5.1+dfsg/roms/skiboot/hw/nx-rng.c:125: rng = dt_new_addr(dt_root, "hwrng", rng_addr);
qemu-5.1+dfsg/roms/skiboot/hw/nx-rng.c-126- if (!rng)
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/occ.c-727- occ_data = get_occ_pstate_table(chip);
qemu-5.1+dfsg/roms/skiboot/hw/occ.c:728: occ_node = dt_new_addr(power_mgt, "occ", (uint64_t)occ_data);
qemu-5.1+dfsg/roms/skiboot/hw/occ.c-729- if (!occ_node) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/occ.c-1515-
qemu-5.1+dfsg/roms/skiboot/hw/occ.c:1516: cnode = dt_new_addr(node, "cpu-to-gpu", handle);
qemu-5.1+dfsg/roms/skiboot/hw/occ.c-1517- if (!cnode) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/occ.c-1674- groups[j].type, i);
qemu-5.1+dfsg/roms/skiboot/hw/occ.c:1675: node = dt_new_addr(sg, name, handle);
qemu-5.1+dfsg/roms/skiboot/hw/occ.c-1676- if (!node) {
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/occ-sensor.c-472- handler = sensor_handler(occ_num, i, attr);
qemu-5.1+dfsg/roms/skiboot/hw/occ-sensor.c:473: node = dt_new_addr(sensor_node, name, handler);
qemu-5.1+dfsg/roms/skiboot/hw/occ-sensor.c-474- dt_add_property_string(node, "sensor-type", type);
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c-1305-{
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c:1306: asm volatile("dcbf %0,%1"
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c-1307- :
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c-4541-
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c:4542: reg = cleanup_addr((uint64_t)p->regs);
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c-4543-
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c-4566- */
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c:4567: m32b = cleanup_addr(p->mm1_base);
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c:4568: m64b = cleanup_addr(p->mm0_base);
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c-4569- m64s = p->mm0_size;
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c-5008-
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c:5009: np = dt_new_addr(dt_root, "pciex", reg[0]);
qemu-5.1+dfsg/roms/skiboot/hw/phb3.c-5010- if (!np)
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c-4439- * Table Size(0) must be a '1' (TVE[51] = 1)
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c:4440: * PCI Addr(49:24) >= TVE[52:53]+TVE[0:23] and
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c:4441: * PCI Addr(49:24) < TVE[54:55]+TVE[24:47]
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c-4442- *
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c-5393- */
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c:5394: m32b = cleanup_addr(p->mm1_base);
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c:5395: m64b = cleanup_addr(p->mm0_base);
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c-5396- m64s = p->mm0_size;
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c-5878-
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c:5879: np = dt_new_addr(dt_root, "pciex", reg[0]);
qemu-5.1+dfsg/roms/skiboot/hw/phb4.c-5880- if (!np)
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/psi.c-784-
qemu-5.1+dfsg/roms/skiboot/hw/psi.c:785: np = dt_new_addr(dt_root, "psi", addr);
qemu-5.1+dfsg/roms/skiboot/hw/psi.c-786- if (!np)
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/sfc-ctrl.c-86-#define SFC_REG_CHIPIDCONF_WRITE (1 << 22)
qemu-5.1+dfsg/roms/skiboot/hw/sfc-ctrl.c:87:#define SFC_REG_CHIPIDCONF_USE_ADDR (1 << 21)
qemu-5.1+dfsg/roms/skiboot/hw/sfc-ctrl.c-88-#define SFC_REG_CHIPIDCONF_DUMMY_SHFT 16
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/sfc-ctrl.c-95-#define SFC_OP_WRITERAW 0x02 /* Write Raw */
qemu-5.1+dfsg/roms/skiboot/hw/sfc-ctrl.c:96:#define SFC_OP_ERASM 0x32 /* Erase Small */
qemu-5.1+dfsg/roms/skiboot/hw/sfc-ctrl.c-97-#define SFC_OP_ERALG 0x34 /* Erase Large */
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/vas.c-50-
qemu-5.1+dfsg/roms/skiboot/hw/vas.c:51:static inline uint64_t compute_vas_scom_addr(struct vas *vas, uint64_t reg)
qemu-5.1+dfsg/roms/skiboot/hw/vas.c-52-{
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/vas.c-60-
qemu-5.1+dfsg/roms/skiboot/hw/vas.c:61: addr = compute_vas_scom_addr(chip->vas, reg);
qemu-5.1+dfsg/roms/skiboot/hw/vas.c-62-
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/vas.c-404-
qemu-5.1+dfsg/roms/skiboot/hw/vas.c:405: dn = dt_new_addr(dt_root, "vas", hvwc_start);
qemu-5.1+dfsg/roms/skiboot/hw/vas.c-406-
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xive.c-1989-
qemu-5.1+dfsg/roms/skiboot/hw/xive.c:1990: xive_dt_node = dt_new_addr(dt_root, "interrupt-controller", tb);
qemu-5.1+dfsg/roms/skiboot/hw/xive.c-1991- assert(xive_dt_node);
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-65-
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:66:static inline void *xscom_addr(uint32_t gcid, uint32_t pcb_addr)
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-67-{
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-116- /* First we need to write 0 to a register on our chip */
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:117: out_be64(xscom_addr(this_cpu()->chip_id, recv_status_reg), 0);
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-118- hmer = xscom_wait_done();
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-122- /* Then we need to clear those two other registers on the target */
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:123: out_be64(xscom_addr(gcid, log_reg), 0);
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-124- hmer = xscom_wait_done();
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-126- goto fail;
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:127: out_be64(xscom_addr(gcid, err_reg), 0);
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-128- hmer = xscom_wait_done();
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-205- /* Write 0 to clear the xscom logic errors on target chip */
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:206: out_be64(xscom_addr(gcid, xscom_clear_reg), 0);
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-207- hmer = xscom_wait_done();
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-320-/* Determine if SCOM address is multicast */
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:321:static inline bool xscom_is_multicast_addr(uint32_t addr)
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-322-{
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-347- /* Read value from SCOM */
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:348: *val = in_be64(xscom_addr(gcid, pcb_addr));
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-349-
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-364- /* Do not print error message for multicast SCOMS */
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:365: if (xscom_is_multicast_addr(pcb_addr) && ret == OPAL_XSCOM_CHIPLET_OFF)
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-366- return ret;
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-399- /* Write value to SCOM */
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:400: out_be64(xscom_addr(gcid, pcb_addr), val);
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-401-
##############################################
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-416- /* Do not print error message for multicast SCOMS */
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c:417: if (xscom_is_multicast_addr(pcb_addr) && ret == OPAL_XSCOM_CHIPLET_OFF)
qemu-5.1+dfsg/roms/skiboot/hw/xscom.c-418- return ret;
##############################################
qemu-5.1+dfsg/roms/skiboot/include/cmpxchg.h-27-
qemu-5.1+dfsg/roms/skiboot/include/cmpxchg.h:28: asm volatile(
qemu-5.1+dfsg/roms/skiboot/include/cmpxchg.h-29- "# __cmpxchg32 \n"
##############################################
qemu-5.1+dfsg/roms/skiboot/include/cmpxchg.h-47-
qemu-5.1+dfsg/roms/skiboot/include/cmpxchg.h:48: asm volatile(
qemu-5.1+dfsg/roms/skiboot/include/cmpxchg.h-49- "# __cmpxchg64 \n"
##############################################
qemu-5.1+dfsg/roms/skiboot/include/compiler.h-44-{
qemu-5.1+dfsg/roms/skiboot/include/compiler.h:45: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/include/compiler.h-46-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/cpu.h-36- cpu_state_unavailable, /* Not available */
qemu-5.1+dfsg/roms/skiboot/include/cpu.h:37: cpu_state_present, /* Assumed to spin in asm entry */
qemu-5.1+dfsg/roms/skiboot/include/cpu.h-38- cpu_state_active, /* Secondary called in */
##############################################
qemu-5.1+dfsg/roms/skiboot/include/device.h-81-struct dt_node *dt_new(struct dt_node *parent, const char *name);
qemu-5.1+dfsg/roms/skiboot/include/device.h:82:struct dt_node *dt_new_addr(struct dt_node *parent, const char *name,
qemu-5.1+dfsg/roms/skiboot/include/device.h-83- uint64_t unit_addr);
qemu-5.1+dfsg/roms/skiboot/include/device.h:84:struct dt_node *dt_new_2addr(struct dt_node *parent, const char *name,
qemu-5.1+dfsg/roms/skiboot/include/device.h-85- uint64_t unit_addr0, uint64_t unit_addr1);
##############################################
qemu-5.1+dfsg/roms/skiboot/include/device.h-269-
qemu-5.1+dfsg/roms/skiboot/include/device.h:270:struct dt_node *__dt_find_by_name_addr(struct dt_node *parent, const char *name,
qemu-5.1+dfsg/roms/skiboot/include/device.h-271- const char *addr);
qemu-5.1+dfsg/roms/skiboot/include/device.h:272:struct dt_node *dt_find_by_name_addr(struct dt_node *parent, const char *name,
qemu-5.1+dfsg/roms/skiboot/include/device.h-273- uint64_t addr);
##############################################
qemu-5.1+dfsg/roms/skiboot/include/io.h-37- uint8_t val;
qemu-5.1+dfsg/roms/skiboot/include/io.h:38: asm volatile("lbzcix %0,0,%1" :
qemu-5.1+dfsg/roms/skiboot/include/io.h-39- "=r"(val) : "r"(addr), "m"(*addr) : "memory");
##############################################
qemu-5.1+dfsg/roms/skiboot/include/io.h-51- uint16_t val;
qemu-5.1+dfsg/roms/skiboot/include/io.h:52: asm volatile("lhzcix %0,0,%1" :
qemu-5.1+dfsg/roms/skiboot/include/io.h-53- "=r"(val) : "r"(addr), "m"(*addr) : "memory");
##############################################
qemu-5.1+dfsg/roms/skiboot/include/io.h-70- uint32_t val;
qemu-5.1+dfsg/roms/skiboot/include/io.h:71: asm volatile("lwzcix %0,0,%1" :
qemu-5.1+dfsg/roms/skiboot/include/io.h-72- "=r"(val) : "r"(addr), "m"(*addr) : "memory");
##############################################
qemu-5.1+dfsg/roms/skiboot/include/io.h-89- uint64_t val;
qemu-5.1+dfsg/roms/skiboot/include/io.h:90: asm volatile("ldcix %0,0,%1" :
qemu-5.1+dfsg/roms/skiboot/include/io.h-91- "=r"(val) : "r"(addr), "m"(*addr) : "memory");
##############################################
qemu-5.1+dfsg/roms/skiboot/include/io.h-107-{
qemu-5.1+dfsg/roms/skiboot/include/io.h:108: asm volatile("stbcix %0,0,%1"
qemu-5.1+dfsg/roms/skiboot/include/io.h-109- : : "r"(val), "r"(addr), "m"(*addr) : "memory");
##############################################
qemu-5.1+dfsg/roms/skiboot/include/io.h-119-{
qemu-5.1+dfsg/roms/skiboot/include/io.h:120: asm volatile("sthcix %0,0,%1"
qemu-5.1+dfsg/roms/skiboot/include/io.h-121- : : "r"(val), "r"(addr), "m"(*addr) : "memory");
##############################################
qemu-5.1+dfsg/roms/skiboot/include/io.h-136-{
qemu-5.1+dfsg/roms/skiboot/include/io.h:137: asm volatile("stwcix %0,0,%1"
qemu-5.1+dfsg/roms/skiboot/include/io.h-138- : : "r"(val), "r"(addr), "m"(*addr) : "memory");
##############################################
qemu-5.1+dfsg/roms/skiboot/include/io.h-153-{
qemu-5.1+dfsg/roms/skiboot/include/io.h:154: asm volatile("stdcix %0,0,%1"
qemu-5.1+dfsg/roms/skiboot/include/io.h-155- : : "r"(val), "r"(addr), "m"(*addr) : "memory");
##############################################
qemu-5.1+dfsg/roms/skiboot/include/io.h-177-{
qemu-5.1+dfsg/roms/skiboot/include/io.h:178: asm volatile("twi 0,%0,0;isync" : : "r" (data) : "memory");
qemu-5.1+dfsg/roms/skiboot/include/io.h-179-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/npu2-regs.h-603-#define NPU2_XTS_MMIO_ATSD_STATUS 0x010
qemu-5.1+dfsg/roms/skiboot/include/npu2-regs.h:604:#define MMIO_ATSD_ADDR(p, n) (u64) p + NPU2_REG_OFFSET(NPU2_STACK_ATSD,\
qemu-5.1+dfsg/roms/skiboot/include/npu2-regs.h-605- NPU2_BLOCK_ATSD##n, NPU2_XTS_MMIO_ATSD_LAUNCH)
##############################################
qemu-5.1+dfsg/roms/skiboot/include/npu-regs.h-177-/* Translates a PHY SCOM address to an MMIO offset */
qemu-5.1+dfsg/roms/skiboot/include/npu-regs.h:178:#define PL_MMIO_ADDR(reg) (((reg >> 32) & 0xfffffull) << 1)
qemu-5.1+dfsg/roms/skiboot/include/npu-regs.h-179-
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-246-
qemu-5.1+dfsg/roms/skiboot/include/processor.h:247:static inline void smt_low(void) { asm volatile("or 1,1,1"); }
qemu-5.1+dfsg/roms/skiboot/include/processor.h:248:static inline void smt_medium(void) { asm volatile("or 2,2,2"); }
qemu-5.1+dfsg/roms/skiboot/include/processor.h:249:static inline void smt_high(void) { asm volatile("or 3,3,3"); }
qemu-5.1+dfsg/roms/skiboot/include/processor.h:250:static inline void smt_medium_high(void){ asm volatile("or 5,5,5"); }
qemu-5.1+dfsg/roms/skiboot/include/processor.h:251:static inline void smt_medium_low(void) { asm volatile("or 6,6,6"); }
qemu-5.1+dfsg/roms/skiboot/include/processor.h:252:static inline void smt_extra_high(void) { asm volatile("or 7,7,7"); }
qemu-5.1+dfsg/roms/skiboot/include/processor.h:253:static inline void smt_very_low(void) { asm volatile("or 31,31,31"); }
qemu-5.1+dfsg/roms/skiboot/include/processor.h-254-static inline void smt_lowest(void) { smt_low(); smt_very_low(); }
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-263-
qemu-5.1+dfsg/roms/skiboot/include/processor.h:264: asm volatile("mfmsr %0" : "=r"(val) : : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-265- return val;
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-269-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:270: asm volatile("mtmsr %0" : : "r"(val) : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-271-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-274-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:275: asm volatile("mtmsrd %0,%1" : : "r"(val), "i"(l) : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-276-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-282-
qemu-5.1+dfsg/roms/skiboot/include/processor.h:283: asm volatile("mfspr %0,%1" : "=r"(val) : "i"(spr) : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-284- return val;
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-289-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:290: asm volatile("mtspr %0,%1" : : "i"(spr), "r"(val) : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-291-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-302-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:303: asm volatile("eieio" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-304-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-307-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:308: asm volatile("sync" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-309-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-312-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:313: asm volatile("lwsync" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-314-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-317-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:318: asm volatile("isync" : : : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-319-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-326-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:327: asm volatile("sync; icbi 0,%0; sync; isync" : : "r" (0) : "memory");
qemu-5.1+dfsg/roms/skiboot/include/processor.h-328-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-335- uint64_t rb = (0x05 << (63-36));
qemu-5.1+dfsg/roms/skiboot/include/processor.h:336: asm volatile(MSGCLR(%0) : : "r"(rb));
qemu-5.1+dfsg/roms/skiboot/include/processor.h-337-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-341- uint64_t rb = (0x05 << (63-36));
qemu-5.1+dfsg/roms/skiboot/include/processor.h:342: asm volatile(MSGCLR(%0) ";"
qemu-5.1+dfsg/roms/skiboot/include/processor.h-343- MSGSYNC ";"
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-350- uint64_t rb = (0x05 << (63-36)) | pir;
qemu-5.1+dfsg/roms/skiboot/include/processor.h:351: asm volatile("sync ;"
qemu-5.1+dfsg/roms/skiboot/include/processor.h-352- MSGSND(%0)
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-362- uint16_t val;
qemu-5.1+dfsg/roms/skiboot/include/processor.h:363: asm volatile("lhbrx %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr));
qemu-5.1+dfsg/roms/skiboot/include/processor.h-364- return val;
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-369- uint32_t val;
qemu-5.1+dfsg/roms/skiboot/include/processor.h:370: asm volatile("lwbrx %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr));
qemu-5.1+dfsg/roms/skiboot/include/processor.h-371- return val;
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-375-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:376: asm volatile("sthbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr));
qemu-5.1+dfsg/roms/skiboot/include/processor.h-377-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/processor.h-380-{
qemu-5.1+dfsg/roms/skiboot/include/processor.h:381: asm volatile("stwbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr));
qemu-5.1+dfsg/roms/skiboot/include/processor.h-382-}
##############################################
qemu-5.1+dfsg/roms/skiboot/include/skiboot.h-125-
qemu-5.1+dfsg/roms/skiboot/include/skiboot.h:126: asm volatile ("cntlzd %0,%1" : "=r" (left_zeros) : "r" (val));
qemu-5.1+dfsg/roms/skiboot/include/skiboot.h-127-
##############################################
qemu-5.1+dfsg/roms/skiboot/include/skiboot.h-153-/* Clean the stray high bit which the FSP inserts: we only have 52 bits real */
qemu-5.1+dfsg/roms/skiboot/include/skiboot.h:154:static inline u64 cleanup_addr(u64 addr)
qemu-5.1+dfsg/roms/skiboot/include/skiboot.h-155-{
##############################################
qemu-5.1+dfsg/roms/skiboot/include/timebase.h-34- */
qemu-5.1+dfsg/roms/skiboot/include/timebase.h:35: asm volatile("mftb %0" : "=r"(tb) : : "memory");
qemu-5.1+dfsg/roms/skiboot/include/timebase.h-36- return tb;
##############################################
qemu-5.1+dfsg/roms/skiboot/include/vas.h-87-/*
qemu-5.1+dfsg/roms/skiboot/include/vas.h:88: * NOTE: VAS_SCOM_BASE_ADDR (0x3011800) includes the SCOM ring of 6. So,
qemu-5.1+dfsg/roms/skiboot/include/vas.h-89- * setting the ring to 0 here.
##############################################
qemu-5.1+dfsg/roms/skiboot/libc/string/memset.c-29- while (size >= CACHE_LINE_SIZE) {
qemu-5.1+dfsg/roms/skiboot/libc/string/memset.c:30: asm volatile ("dcbz 0,%0\n" : : "r"(d) : "memory");
qemu-5.1+dfsg/roms/skiboot/libc/string/memset.c-31- d+= CACHE_LINE_SIZE;
##############################################
qemu-5.1+dfsg/roms/skiboot/libc/test/Makefile.check-25- $(eval LCOV_DIRS += -d $(dir $<) )
qemu-5.1+dfsg/roms/skiboot/libc/test/Makefile.check:26: $(call Q, TEST-COVERAGE , (cd $(dir $<); GCOV_PREFIX_STRIP=`(c=0; while [ "\`pwd\`" != '/' ]; do cd ..; c=\`expr 1 + $$c\`; done; echo $$c)` ./$(notdir $<) ), $< )
qemu-5.1+dfsg/roms/skiboot/libc/test/Makefile.check-27-
##############################################
qemu-5.1+dfsg/roms/skiboot/libflash/mbox-flash.c-352- time_wait_ms(MBOX_DEFAULT_POLL_MS);
qemu-5.1+dfsg/roms/skiboot/libflash/mbox-flash.c:353: asm volatile ("" ::: "memory");
qemu-5.1+dfsg/roms/skiboot/libflash/mbox-flash.c-354- }
##############################################
qemu-5.1+dfsg/roms/skiboot/libflash/test/test-flash.c-281-
qemu-5.1+dfsg/roms/skiboot/libflash/test/test-flash.c:282:static int sim_send_addr(uint32_t addr)
qemu-5.1+dfsg/roms/skiboot/libflash/test/test-flash.c-283-{
##############################################
qemu-5.1+dfsg/roms/skiboot/libflash/test/test-flash.c-307- if (has_addr) {
qemu-5.1+dfsg/roms/skiboot/libflash/test/test-flash.c:308: rc = sim_send_addr(addr);
qemu-5.1+dfsg/roms/skiboot/libflash/test/test-flash.c-309- if (rc)
##############################################
qemu-5.1+dfsg/roms/skiboot/libflash/test/test-flash.c-328- if (has_addr) {
qemu-5.1+dfsg/roms/skiboot/libflash/test/test-flash.c:329: rc = sim_send_addr(addr);
qemu-5.1+dfsg/roms/skiboot/libflash/test/test-flash.c-330- if (rc)
##############################################
qemu-5.1+dfsg/roms/skiboot/libpore/p8_delta_scan_rw.h-103-#define IMGBUILD_ERR_PORE_INLINE 20 // Pore inline error.
qemu-5.1+dfsg/roms/skiboot/libpore/p8_delta_scan_rw.h:104:#define IMGBUILD_ERR_PORE_INLINE_ASM 21 // Err assoc w/inline assembler.
qemu-5.1+dfsg/roms/skiboot/libpore/p8_delta_scan_rw.h-105-#define IMGBUILD_RING_SEARCH_MATCH 0
##############################################
qemu-5.1+dfsg/roms/skiboot/libpore/p9_stop_api.C-1128-
qemu-5.1+dfsg/roms/skiboot/libpore/p9_stop_api.C:1129: pScomEntry = CACHE_SCOM_ADDR(i_pImage,
qemu-5.1+dfsg/roms/skiboot/libpore/p9_stop_api.C-1130- chipletId,
##############################################
qemu-5.1+dfsg/roms/skiboot/libpore/p9_stop_data_struct.H-189-
qemu-5.1+dfsg/roms/skiboot/libpore/p9_stop_data_struct.H:190:#define CACHE_SCOM_ADDR(io_image,\
qemu-5.1+dfsg/roms/skiboot/libpore/p9_stop_data_struct.H-191- i_chipletId,\
##############################################
qemu-5.1+dfsg/roms/skiboot/Makefile.main-313- $(call Q, HOSTCC ,$(HOSTCC) $(HOSTCFLAGS) \
qemu-5.1+dfsg/roms/skiboot/Makefile.main:314: -DTARGET__GNUC__=`echo '__GNUC__'|$(CC) -E -|grep -v '^#'` \
qemu-5.1+dfsg/roms/skiboot/Makefile.main:315: -DTARGET__GNUC_MINOR__=`echo '__GNUC_MINOR__'|$(CC) -E -|grep -v '^#'` \
qemu-5.1+dfsg/roms/skiboot/Makefile.main-316- -Wpadded -O0 -g -I$(SRC) -o $@ $<,$<)
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/astbmc/witherspoon.c-74-
qemu-5.1+dfsg/roms/skiboot/platforms/astbmc/witherspoon.c:75: i2c_bus = dt_new_addr(i2cm, "i2c-bus", 4);
qemu-5.1+dfsg/roms/skiboot/platforms/astbmc/witherspoon.c-76- dt_add_property_cells(i2c_bus, "reg", 4);
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/astbmc/zaius.c-208-
qemu-5.1+dfsg/roms/skiboot/platforms/astbmc/zaius.c:209: i2c_bus = dt_new_addr(i2cm, "i2c-bus", 4);
qemu-5.1+dfsg/roms/skiboot/platforms/astbmc/zaius.c-210- dt_add_property_cells(i2c_bus, "reg", 4);
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/firenze.c-37- /* Each master registers set is of length 0x20 */
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/firenze.c:38: i2cm = dt_new_addr(n, "i2cm", 0xa0000 + eng_id * 0x20);
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/firenze.c-39- if (!i2cm)
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/firenze.c-64-
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/firenze.c:65: port = dt_new_addr(i2cm, "i2c-bus", port_id);
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/firenze.c-66- if (!port)
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/firenze.c-85-
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/firenze.c:86: dev = dt_new_addr(bus, name, addr);
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/firenze.c-87- if (!dev)
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/zz.c-67-
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/zz.c:68: link = dt_new_addr(npu, "link", index);
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/zz.c-69- dt_add_property_string(link, "compatible", "ibm,npu-link");
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/zz.c-122- */
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/zz.c:123: npu = dt_find_by_name_addr(xscom, "npu", NPU_BASE);
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/zz.c-124- if (npu)
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/zz.c-126-
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/zz.c:127: npu = dt_new_addr(xscom, "npu", NPU_BASE);
qemu-5.1+dfsg/roms/skiboot/platforms/ibm-fsp/zz.c-128- dt_add_property_cells(npu, "reg", NPU_BASE, NPU_SIZE);
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/mambo/mambo.h-22- register uint64_t c asm("r3") = command;
qemu-5.1+dfsg/roms/skiboot/platforms/mambo/mambo.h:23: asm volatile (".long 0x000eaeb0":"=r" (c):"r"(c));
qemu-5.1+dfsg/roms/skiboot/platforms/mambo/mambo.h-24- return c;
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/mambo/mambo.h-32- register unsigned long a2 asm("r5") = arg2;
qemu-5.1+dfsg/roms/skiboot/platforms/mambo/mambo.h:33: asm volatile (".long 0x000eaeb0":"=r" (c):"r"(c), "r"(a1), "r"(a2));
qemu-5.1+dfsg/roms/skiboot/platforms/mambo/mambo.h-34- return c;
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/mambo/mambo.h-43- register unsigned long a3 asm("r6") = arg3;
qemu-5.1+dfsg/roms/skiboot/platforms/mambo/mambo.h:44: asm volatile (".long 0x000eaeb0":"=r" (c):"r"(c), "r"(a1), "r"(a2),
qemu-5.1+dfsg/roms/skiboot/platforms/mambo/mambo.h-45- "r"(a3));
##############################################
qemu-5.1+dfsg/roms/skiboot/platforms/rhesus/rhesus.c-219- */
qemu-5.1+dfsg/roms/skiboot/platforms/rhesus/rhesus.c:220: rtc = dt_new_addr(lpc, "rtc", EC_RTC_PORT_BASE);
qemu-5.1+dfsg/roms/skiboot/platforms/rhesus/rhesus.c-221- assert(rtc);
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c-21- set_ci();
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c:22: asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr));
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c-23- clr_ci();
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c-31- set_ci();
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c:32: asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr));
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c-33- clr_ci();
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c-40- set_ci();
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c:41: asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr));
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c-42- clr_ci();
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c-48- set_ci();
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c:49: asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr));
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/hw.c-50- clr_ci();
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c-55- printf("\r\n exception %llx ", gVecNum);
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c:56: asm volatile ("mfsrr0 %0":"=r" (val):);
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c-57- printf("\r\nSRR0 = %08llx%08llx ", val >> 32, val);
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c:58: asm volatile ("mfsrr1 %0":"=r" (val):);
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c-59- printf(" SRR1 = %08llx%08llx ", val >> 32, val);
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c-60-
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c:61: asm volatile ("mfsprg %0,2":"=r" (val):);
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c-62- printf("\r\nSPRG2 = %08llx%08llx ", val >> 32, val);
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c:63: asm volatile ("mfsprg %0,3":"=r" (val):);
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c-64- printf(" SPRG3 = %08llx%08llx \r\n", val >> 32, val);
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c-272- */
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c:273: asm volatile("isync; sync;" : : : "memory");
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.c-274- ofw_start(0, romfs_base, 0, 0, 0);
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.lds-48- . = ALIGN(256);
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.lds:49: __toc_start = DEFINED (.TOC.) ? .TOC. : ADDR (.got) + 0x8000;
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/stage2.lds-50- .got :
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/u4mem.c-57- */
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/u4mem.c:58:#define U4_BASE_ADDR ((uint64_t) 0xf8000000 )
qemu-5.1+dfsg/roms/SLOF/board-js2x/llfw/u4mem.c-59-#define u4reg( reg ) (U4_BASE_ADDR + (uint64_t) (reg))
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/rtas/Makefile-25-# Board specific RTAS files:
qemu-5.1+dfsg/roms/SLOF/board-js2x/rtas/Makefile:26:BOARD_SRC_ASM =
qemu-5.1+dfsg/roms/SLOF/board-js2x/rtas/Makefile-27-BOARD_SRC_C = rtas_flash.c rtas_board.c rtas_pci.c \
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/rtas/Makefile-34-# Common RTAS files (from $(RTASCMNDIR) directory):
qemu-5.1+dfsg/roms/SLOF/board-js2x/rtas/Makefile:35:RTAS_SRC_ASM = rtas_entry.S rtas_common.S reloc.S
qemu-5.1+dfsg/roms/SLOF/board-js2x/rtas/Makefile-36-RTAS_SRC_C = rtas_call.c
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/rtas/rtas_board.c-43- pIface->id = 0;
qemu-5.1+dfsg/roms/SLOF/board-js2x/rtas/rtas_board.c:44: asm volatile (" mr 3,%0 ; mtctr %1 ; bctr "
qemu-5.1+dfsg/roms/SLOF/board-js2x/rtas/rtas_board.c-45- ::"r"(pIface->r3), "r"(pIface->addr));
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/i2c.fs-39-
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/i2c.fs:40:: i2c-addr ( addr -- ) 50 i2c! 2 10 i2c! BEGIN 30 i2c@ 2 and UNTIL ;
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/i2c.fs:41:: i2c-subaddr ( suba -- ) 60 i2c! ;
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/i2c.fs-42-: i2c-stop ( -- ) BEGIN 30 i2c@ dup 30 i2c! 4 and UNTIL ;
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/i2c.fs-60-: i2c-sub-read ( buf len addr suba -- error? )
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/i2c.fs:61: c 0 i2c! i2c-subaddr (read) ;
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/i2c.fs-62-
##############################################
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/u4-mem.fs-26-
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/u4-mem.fs:27:: i2c-addr ( addr -- ) 50 i2c! 2 10 i2c! BEGIN 30 i2c@ 2 and UNTIL ;
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/u4-mem.fs:28:: i2c-addr-subaddr ( addr suba -- ) 60 i2c! i2c-addr ;
qemu-5.1+dfsg/roms/SLOF/board-js2x/slof/u4-mem.fs-29-: i2c-stop ( -- ) BEGIN 30 i2c@ dup 30 i2c! 4 and UNTIL ;
##############################################
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-55- printf("\r\n exception %llx ", gVecNum);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c:56: asm volatile ("mfsrr0 %0":"=r" (val):);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-57- printf("\r\nSRR0 = %08llx%08llx ", val >> 32, val);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c:58: asm volatile ("mfsrr1 %0":"=r" (val):);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-59- printf(" SRR1 = %08llx%08llx ", val >> 32, val);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-60-
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c:61: asm volatile ("mfsprg %0,2":"=r" (val):);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-62- printf("\r\nSPRG2 = %08llx%08llx ", val >> 32, val);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c:63: asm volatile ("mfsprg %0,3":"=r" (val):);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-64- printf(" SPRG3 = %08llx%08llx \r\n", val >> 32, val);
##############################################
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-179- }
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c:180: rc = elf_load_file_to_addr((void *)fileInfo.addr_data, (void*)paflof_base,
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-181- ofw_addr, NULL, flush_cache);
##############################################
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-200- */
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c:201: asm volatile("isync; sync;" : : : "memory");
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-202- ofw_start(fdt_addr, romfs_base, 0, 0x65504150, fdt_addr);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c:203: asm volatile("isync; sync;" : : : "memory");
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.c-204- // never return
##############################################
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.lds-52- . = ALIGN(256);
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.lds:53: __toc_start = DEFINED (.TOC.) ? .TOC. : ADDR (.got) + 0x8000;
qemu-5.1+dfsg/roms/SLOF/board-qemu/llfw/stage2.lds-54- .got :
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.c-113-static void
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.c:114:dev_find_vmem_addr(void)
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.c-115-{
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.c-285- dev_get_addr_info();
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.c:286: dev_find_vmem_addr();
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.c-287- dev_get_puid();
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h-116-{
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h:117: asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr));
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h-118-}
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h-124- const uint32_t *zaddr = addr;
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h:125: asm volatile ("lwbrx %0, %y1" : "=r"(val) : "Z"(*zaddr));
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h-126- return val;
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h-131-{
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h:132: asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr));
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h-133-}
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h-139- const uint16_t *zaddr = addr;
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h:140: asm volatile ("lhbrx %0, %y1" : "=r"(val) : "Z"(*zaddr));
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/app/biosemu/device.h-141- return val;
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/client.lds-49- {
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/client.lds:50: _got = DEFINED (.TOC.) ? .TOC. : ADDR (.got) + 0x8000;
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/client.lds-51- *(.got)
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/libc/time/timer.c-27-{
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/libc/time/timer.c:28: asm volatile ("mtdec %0"::"r" (val));
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/libc/time/timer.c-29-}
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/libc/time/timer.c-33- int val;
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/libc/time/timer.c:34: asm volatile ("mfdec %0":"=r" (val));
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/libc/time/timer.c-35- return val;
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/oflib/of.c-406- const unsigned int nsc = 2; //PCI
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/oflib/of.c:407: /* up to 11 pairs of (phys-addr(3) size(2)) */
qemu-5.1+dfsg/roms/SLOF/clients/net-snk/oflib/of.c-408- unsigned char buf[11 * (nac + nsc) * sizeof(int)];
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/takeover/client.lds-46- . = ALIGN(256);
qemu-5.1+dfsg/roms/SLOF/clients/takeover/client.lds:47: _got = DEFINED (.TOC.) ? .TOC. : ADDR (.got) + 0x8000;
qemu-5.1+dfsg/roms/SLOF/clients/takeover/client.lds-48- *(.got .toc)
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/takeover/main.c-51- while (dly--)
qemu-5.1+dfsg/roms/SLOF/clients/takeover/main.c:52: asm volatile (" nop ");
qemu-5.1+dfsg/roms/SLOF/clients/takeover/main.c-53- printf("\b%c", wheel[i++]);
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/takeover/main.c-94-
qemu-5.1+dfsg/roms/SLOF/clients/takeover/main.c:95: asm volatile ("mfmsr %0":"=r" (msr));
qemu-5.1+dfsg/roms/SLOF/clients/takeover/main.c-96- if (msr & 0x1000000000000000)
##############################################
qemu-5.1+dfsg/roms/SLOF/clients/takeover/main.c-154-
qemu-5.1+dfsg/roms/SLOF/clients/takeover/main.c:155: asm volatile(" mtctr %0 ; bctr " : : "r" (TAKEOVERBASEADDRESS+0x180) );
qemu-5.1+dfsg/roms/SLOF/clients/takeover/main.c-156-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/libelf.h-74- void (*post_load)(void*, long));
qemu-5.1+dfsg/roms/SLOF/include/libelf.h:75:int elf_load_file_to_addr(void *file_addr, void *addr, unsigned long *entry,
qemu-5.1+dfsg/roms/SLOF/include/libelf.h-76- int (*pre_load)(void*, long),
##############################################
qemu-5.1+dfsg/roms/SLOF/include/libelf.h-88-
qemu-5.1+dfsg/roms/SLOF/include/libelf.h:89:long elf_get_base_addr(void *file_addr);
qemu-5.1+dfsg/roms/SLOF/include/libelf.h-90-long elf_get_base_addr32(void *file_addr);
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-78- unsigned long tmp;
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h:79: asm volatile(EXPAND(SETCI(%0)) : "=r"(tmp) :: "memory", "cc");
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-80-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-85- unsigned long tmp;
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h:86: asm volatile(EXPAND(CLRCI(%0)) : "=r"(tmp) :: "memory", "cc");
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-87-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-90-{
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h:91: asm volatile ("eieio":::"memory");
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-92-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-95-{
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h:96: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-97-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-101-{
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h:102: asm volatile ("sync" ::: "memory");
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-103-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-107-{
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h:108: asm volatile(EXPAND(FLUSH_CACHE(%0, %1)) : "+r"(r), "+r"(n) :: "memory", "cc", "r0", "ctr");
qemu-5.1+dfsg/roms/SLOF/include/ppc970/cpu.h-109-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-22- { \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:23: register uint64_t arg0 asm ("r3"); \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:24: register uint64_t arg1 asm ("r4"); \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:25: register uint64_t arg2 asm ("r5"); \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-26- \
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-30- \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:31: asm volatile( \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-32- ".long 0x44000022 \n" /* HVCALL */ \
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-41- { \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:42: register uint64_t arg0 asm ("r3"); \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:43: register uint64_t arg1 asm ("r4"); \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:44: register uint64_t arg2 asm ("r5"); \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:45: register uint64_t arg3 asm ("r6"); \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-46- \
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-51- \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:52: asm volatile( \
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-53- ".long 0x44000022 \n" /* HVCALL */ \
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-91-{
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:92: register uint64_t arg0 asm ("r3");
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:93: register uint64_t arg1 asm ("r4");
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:94: register uint64_t arg2 asm ("r5");
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:95: register uint64_t arg3 asm ("r6");
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:96: register uint64_t arg4 asm ("r7");
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:97: register uint64_t arg5 asm ("r8");
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-98-
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-105-
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:106: asm volatile(".long 0x44000022 \n" /* HVCALL */
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-107- : "=&r"(arg0),"=&r"(arg1),"=&r"(arg2),
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-132- unsigned int val;
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:133: asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr));
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-134- return val;
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-139- unsigned int val;
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:140: asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr));
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-141- return val;
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-145-{
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:146: asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr));
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-147-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-150-{
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h:151: asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr));
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cache.h-152-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h-41-{
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h:42: asm volatile(EXPAND(FLUSH_CACHE(%0, %1))
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h-43- : "+r"(r), "+r"(n)
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h-48-{
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h:49: asm volatile ("eieio":::"memory");
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h-50-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h-53-{
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h:54: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h-55-}
##############################################
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h-59-{
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h:60: asm volatile ("sync" ::: "memory");
qemu-5.1+dfsg/roms/SLOF/include/ppcp7/cpu.h-61-}
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c-1332- /*
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c:1333: * setup rx standard rcb using recommended NIC addr (hard coded)
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c-1334- */
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c-1465- /*
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c:1466: * setup tx rcb using recommended NIC addr (hard coded)
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c-1467- */
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c-2354- (uint64_t) SLOF_translate_my_address((void *)bcm_baseaddr_u64);
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c:2355: /*snk_kernel_interface->translate_addr(((void *)&(bcm_baseaddr_u64)));*/
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c-2356- bcm_memaddr_u64 = bcm_baseaddr_u64 + BCM_MEMORY_OFFS;
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c-3333- (uint64_t)SLOF_translate_my_address((void *)bcm_baseaddr_u64);
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c:3334: /*snk_kernel_interface->translate_addr(((void *)&(bcm_baseaddr_u64)));*/
qemu-5.1+dfsg/roms/SLOF/lib/libbcm/bcm57xx.c-3335- bcm_memaddr_u64 = bcm_baseaddr_u64 + BCM_MEMORY_OFFS;
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libc/ctype/Makefile.inc-14-CTYPE_SRC_C = isdigit.c isprint.c isspace.c isxdigit.c tolower.c toupper.c
qemu-5.1+dfsg/roms/SLOF/lib/libc/ctype/Makefile.inc:15:CTYPE_SRC_ASM =
qemu-5.1+dfsg/roms/SLOF/lib/libc/ctype/Makefile.inc-16-CTYPE_SRCS = $(CTYPE_SRC_C:%=$(CTYPECMNDIR)/%) $(CTYPE_SRC_ASM:%=$(CTYPECMNDIR)/%)
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libc/stdio/Makefile.inc-17-
qemu-5.1+dfsg/roms/SLOF/lib/libc/stdio/Makefile.inc:18:STDIO_SRC_ASM =
qemu-5.1+dfsg/roms/SLOF/lib/libc/stdio/Makefile.inc-19-STDIO_SRCS = $(STDIO_SRC_C:%=$(STDIOCMNDIR)/%) $(STDIO_SRC_ASM:%=$(STDIOCMNDIR)/%)
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libc/stdlib/Makefile.inc-16-
qemu-5.1+dfsg/roms/SLOF/lib/libc/stdlib/Makefile.inc:17:STDLIB_SRC_ASM =
qemu-5.1+dfsg/roms/SLOF/lib/libc/stdlib/Makefile.inc-18-STDLIB_SRCS = $(STDLIB_SRC_C:%=$(STDLIBCMNDIR)/%) $(STDLIB_SRC_ASM:%=$(STDLIBCMNDIR)/%)
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libc/string/Makefile.inc-16- memcmp.c strcasecmp.c strncasecmp.c strtok.c strrchr.c
qemu-5.1+dfsg/roms/SLOF/lib/libc/string/Makefile.inc:17:STRING_SRC_ASM =
qemu-5.1+dfsg/roms/SLOF/lib/libc/string/Makefile.inc-18-STRING_SRCS = $(STRING_SRC_C:%=$(STRINGCMNDIR)/%) $(STRING_SRC_ASM:%=$(STRINGCMNDIR)/%)
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libe1k/e1k.h-100-
qemu-5.1+dfsg/roms/SLOF/lib/libe1k/e1k.h:101://#define mb() asm volatile("sync" ::: "memory");
qemu-5.1+dfsg/roms/SLOF/lib/libe1k/e1k.h-102-
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf32.c-117- if (phdr->p_paddr != phdr->p_vaddr) {
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf32.c:118: printf("ELF32: VirtAddr(%lx) != PhysAddr(%lx) not supported, aborting\n",
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf32.c-119- (long)phdr->p_vaddr, (long)phdr->p_paddr);
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf64.c-254- if (phdr->p_paddr != phdr->p_vaddr) {
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf64.c:255: printf("ELF64: VirtAddr(%lx) != PhysAddr(%lx) not supported, aborting\n",
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf64.c-256- (long)phdr->p_vaddr, (long)phdr->p_paddr);
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf.c-136-int
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf.c:137:elf_load_file_to_addr(void *file_addr, void *addr, unsigned long *entry,
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf.c-138- int (*pre_load)(void*, long),
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf.c-179-long
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf.c:180:elf_get_base_addr(void *file_addr)
qemu-5.1+dfsg/roms/SLOF/lib/libelf/elf.c-181-{
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libelf/libelf.code-30-
qemu-5.1+dfsg/roms/SLOF/lib/libelf/libelf.code:31:// : elf-load-file-to-addr ( fileaddr destaddr -- entry type )
qemu-5.1+dfsg/roms/SLOF/lib/libelf/libelf.code-32-PRIM(ELF_X2d_LOAD_X2d_FILE_X2d_TO_X2d_ADDR)
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libelf/libelf.code-37- unsigned long entry;
qemu-5.1+dfsg/roms/SLOF/lib/libelf/libelf.code:38: type = elf_load_file_to_addr(file_addr, dest_addr, &entry,
qemu-5.1+dfsg/roms/SLOF/lib/libelf/libelf.code-39- elf_forth_claim, flush_cache);
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libhvcall/brokensc1.c-19- register unsigned long r5 asm("r5") = inst;
qemu-5.1+dfsg/roms/SLOF/lib/libhvcall/brokensc1.c:20: asm volatile("bl 1f \n"
qemu-5.1+dfsg/roms/SLOF/lib/libhvcall/brokensc1.c-21- "1: \n"
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/icmpv6.c-95- /* Add address created from prefix to IPv6 address list */
qemu-5.1+dfsg/roms/SLOF/lib/libnet/icmpv6.c:96: new_address = ip6_prefix2addr (prefix);
qemu-5.1+dfsg/roms/SLOF/lib/libnet/icmpv6.c-97- if (!new_address)
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/icmpv6.c-120-static void
qemu-5.1+dfsg/roms/SLOF/lib/libnet/icmpv6.c:121:handle_source_lladdr ( struct option_ll_address *option, struct router *rtr)
qemu-5.1+dfsg/roms/SLOF/lib/libnet/icmpv6.c-122-{
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/icmpv6.c-136- case ND_OPTION_SOURCE_LL_ADDR:
qemu-5.1+dfsg/roms/SLOF/lib/libnet/icmpv6.c:137: handle_source_lladdr ((struct option_ll_address *) option, r);
qemu-5.1+dfsg/roms/SLOF/lib/libnet/icmpv6.c-138- break;
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c-95-
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c:96:static arp_entry_t *lookup_mac_addr(uint32_t ipv4_addr);
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c-97-
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c-483- if((subnet_mask & own_ip) == (subnet_mask & ip->ip_dst))
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c:484: arp_entry = lookup_mac_addr(ip->ip_dst);
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c-485- // if not then we need to know the router's IP address
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c-487- ip_dst = router_ip;
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c:488: arp_entry = lookup_mac_addr(router_ip);
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c-489- }
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c-601-
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c:602:static arp_entry_t* lookup_mac_addr(uint32_t ipv4_addr)
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv4.c-603-{
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c-118- */
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c:119:static int8_t find_ip6addr(ip6_addr_t ip)
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c-120-{
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c-148- /* Only handle packets which are for us */
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c:149: if (!find_ip6addr(ip6->dst))
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c-150- return -1;
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c-269- */
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c:270:void *ip6_prefix2addr(ip6_addr_t prefix)
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c-271-{
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c-306- /* Don't add the same address twice */
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c:307: if (find_ip6addr(new_address->addr))
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.c-308- return 0;
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.h-160- * and add it to our IPv6 address list */
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.h:161:void * ip6_prefix2addr (ip6_addr_t prefix);
qemu-5.1+dfsg/roms/SLOF/lib/libnet/ipv6.h-162-
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libnet/netload.c-402-
qemu-5.1+dfsg/roms/SLOF/lib/libnet/netload.c:403: asm volatile("mftbl %0" : "=r"(seed));
qemu-5.1+dfsg/roms/SLOF/lib/libnet/netload.c-404- seed ^= (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c-554- attr = 0;
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c:555: attr = EDA_FADDR(pipe->dev->addr) | EDA_MPS(pipe->mps) | EDA_SKIP;
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c-556- ohci_fill_ed(ed, PTR_U32(td_phys), td_next, attr, 0);
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c-672- dir = pipe->dir ? EDA_DIR_IN : EDA_DIR_OUT;
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c:673: attr = dir | EDA_FADDR(pipe->dev->addr) | EDA_MPS(pipe->mps)
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c-674- | EDA_SKIP | pipe->dev->speed | EDA_EP(pipe->epno);
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c-749- ed->attr = cpu_to_le32(EDA_DIR_IN |
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c:750: EDA_FADDR(dev->addr) |
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c-751- dev->speed |
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c-887- ed->attr = cpu_to_le32(dir |
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c:888: EDA_FADDR(dev->addr) |
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.c-889- dev->speed |
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.h-51-
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.h:52:#define EDA_FADDR(x) ((x & 0x7F))
qemu-5.1+dfsg/roms/SLOF/lib/libusb/usb-ohci.h-53-#define EDA_EP(x) ((x & 0x0F) << 7)
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-100-
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c:101:static void virtio_cap_set_base_addr(struct virtio_cap *cap, uint32_t offset)
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-102-{
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-147- cap->bar = bar;
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c:148: virtio_cap_set_base_addr(cap, offset);
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-149- cap->cap_id = cfg_type;
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-181- dev->legacy.bar = 0;
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c:182: virtio_cap_set_base_addr(&dev->legacy, 0);
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-183- }
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-316-
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c:317:void *virtio_desc_addr(struct virtio_device *vdev, int queue, int id)
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-318-{
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-359- */
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c:360:static void virtio_set_qaddr(struct virtio_device *dev, int queue, unsigned long qaddr)
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-361-{
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-424- memset(vq->desc, 0, virtio_vring_size(vq->size));
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c:425: virtio_set_qaddr(dev, id, (unsigned long)vq->desc);
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.c-426-
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.h-86- struct vring_used *used;
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.h:87: void **desc_gpas; /* to get gpa from desc->addr (which is ioba) */
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.h-88- uint64_t bus_desc;
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.h-114-extern void virtio_free_desc(struct vqs *vq, int id, uint64_t features);
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.h:115:void *virtio_desc_addr(struct virtio_device *vdev, int queue, int id);
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio.h-116-extern struct vqs *virtio_queue_init_vq(struct virtio_device *dev, unsigned int id);
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio-net.c-37-
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio-net.c:38:#define sync() asm volatile (" sync \n" ::: "memory")
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio-net.c-39-
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio-net.c-322- /* Copy data to destination buffer */
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio-net.c:323: memcpy(buf, virtio_desc_addr(vdev, VQ_RX, id), len);
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio-net.c-324-
##############################################
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio-serial.c-176- /* Copy data to destination buffer */
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio-serial.c:177: memcpy(buf, virtio_desc_addr(dev, RX_Q, id - 1), RX_ELEM_SIZE);
qemu-5.1+dfsg/roms/SLOF/lib/libvirtio/virtio-serial.c-178-
##############################################
qemu-5.1+dfsg/roms/SLOF/llfw/clib/iolib.c-19-{
qemu-5.1+dfsg/roms/SLOF/llfw/clib/iolib.c:20: asm volatile ("":::"3","4","5","6","7");
qemu-5.1+dfsg/roms/SLOF/llfw/clib/iolib.c-21- io_putchar(b);
##############################################
qemu-5.1+dfsg/roms/SLOF/llfw/clib/Makefile.inc-20-
qemu-5.1+dfsg/roms/SLOF/llfw/clib/Makefile.inc:21:COMLIB_SRC_ASM =
qemu-5.1+dfsg/roms/SLOF/llfw/clib/Makefile.inc-22-COMLIB_SRC_C = iolib.c
##############################################
qemu-5.1+dfsg/roms/SLOF/llfw/clib/Makefile.inc-25- $(COMLIB_SRC_C:%=$(COMLIBDIR)/%)
qemu-5.1+dfsg/roms/SLOF/llfw/clib/Makefile.inc:26:COMLIB_OBJ_ASM = $(COMLIB_SRC_ASM:%.S=%.o)
qemu-5.1+dfsg/roms/SLOF/llfw/clib/Makefile.inc-27-COMLIB_OBJ_C = $(COMLIB_SRC_C:%.c=%.o)
##############################################
qemu-5.1+dfsg/roms/SLOF/llfw/io_generic/Makefile.inc-14-
qemu-5.1+dfsg/roms/SLOF/llfw/io_generic/Makefile.inc:15:IO_GENERIC_SRC_ASM = io_generic.S
qemu-5.1+dfsg/roms/SLOF/llfw/io_generic/Makefile.inc-16-IO_GENERIC_SRC_C =
##############################################
qemu-5.1+dfsg/roms/SLOF/llfw/io_generic/Makefile.inc-19- $(IO_GENERIC_SRC_C:%=$(IOGENERICDIR)/%)
qemu-5.1+dfsg/roms/SLOF/llfw/io_generic/Makefile.inc:20:IO_GENERIC_OBJ_ASM = $(IO_GENERIC_SRC_ASM:%.S=%.o)
qemu-5.1+dfsg/roms/SLOF/llfw/io_generic/Makefile.inc-21-IO_GENERIC_OBJ_C = $(IO_GENERIC_SRC_C:%.c=%.o)
##############################################
qemu-5.1+dfsg/roms/SLOF/llfw/romfs.S-22- * 8: flags (return)
qemu-5.1+dfsg/roms/SLOF/llfw/romfs.S:23: * 10: fileaddr (return and input: tells if first search)
qemu-5.1+dfsg/roms/SLOF/llfw/romfs.S-24- * 18: nextfile (return)
##############################################
qemu-5.1+dfsg/roms/SLOF/llfw/romfs.S-110- /* info for file at rombase (R8=R4) */
qemu-5.1+dfsg/roms/SLOF/llfw/romfs.S:111: ld r6, RFS_T_FILEADDR(r4)
qemu-5.1+dfsg/roms/SLOF/llfw/romfs.S-112- mfsprg r8, 1
##############################################
qemu-5.1+dfsg/roms/SLOF/llfw/romfs.S-132- mfsprg r3, 1
qemu-5.1+dfsg/roms/SLOF/llfw/romfs.S:133: std r8, RFS_T_FILEADDR(r16)
qemu-5.1+dfsg/roms/SLOF/llfw/romfs.S-134-
##############################################
qemu-5.1+dfsg/roms/SLOF/llfw/romfs_wrap.c-16-{
qemu-5.1+dfsg/roms/SLOF/llfw/romfs_wrap.c:17: asm volatile ("":::"3","4","5","6","7","9","10");
qemu-5.1+dfsg/roms/SLOF/llfw/romfs_wrap.c:18: asm volatile ("":::"11","12");
qemu-5.1+dfsg/roms/SLOF/llfw/romfs_wrap.c:19: asm volatile ("":::"13","14","15","16","17","18");
qemu-5.1+dfsg/roms/SLOF/llfw/romfs_wrap.c-20-
##############################################
qemu-5.1+dfsg/roms/SLOF/Makefile-22- if [ "X$$b" != "Xsimics" ]; then \
qemu-5.1+dfsg/roms/SLOF/Makefile:23: if [ "X$$b" != "X`echo $$a|sed -e s/board-//g`" ]; then \
qemu-5.1+dfsg/roms/SLOF/Makefile-24- targets="$$targets $$a-$$b"; \
##############################################
qemu-5.1+dfsg/roms/SLOF/Makefile-63- fi
qemu-5.1+dfsg/roms/SLOF/Makefile:64: @b=`echo $@ | grep "-"`; \
qemu-5.1+dfsg/roms/SLOF/Makefile-65- if [ -n "$$b" ]; then \
##############################################
qemu-5.1+dfsg/roms/SLOF/Makefile-78- @echo "******** Building $(BOARD) system ********"
qemu-5.1+dfsg/roms/SLOF/Makefile:79: @b=`echo $(BOARD) | grep "-"`; \
qemu-5.1+dfsg/roms/SLOF/Makefile-80- if [ -n "$$b" ]; then \
##############################################
qemu-5.1+dfsg/roms/SLOF/Makefile-100- tar=`cat .target`; \
qemu-5.1+dfsg/roms/SLOF/Makefile:101: b=`echo $$tar | grep "-"`; \
qemu-5.1+dfsg/roms/SLOF/Makefile-102- if [ -n "$$b" ]; then \
##############################################
qemu-5.1+dfsg/roms/SLOF/Makefile-114- tar=`cat .target`; \
qemu-5.1+dfsg/roms/SLOF/Makefile:115: b=`echo $$tar | grep "-"`; \
qemu-5.1+dfsg/roms/SLOF/Makefile-116- if [ -n "$$b" ]; then \
##############################################
qemu-5.1+dfsg/roms/SLOF/make.rules-60-MAKE += -s
qemu-5.1+dfsg/roms/SLOF/make.rules:61:CC = printf "\t[CC]\t%s\n" `basename "$@"`; $(ONLY_CC)
qemu-5.1+dfsg/roms/SLOF/make.rules:62:AS = printf "\t[AS]\t%s\n" `basename "$@"`; $(ONLY_AS)
qemu-5.1+dfsg/roms/SLOF/make.rules:63:LD = printf "\t[LD]\t%s\n" `basename "$@"`; $(ONLY_LD)
qemu-5.1+dfsg/roms/SLOF/make.rules-64-CLEAN = printf "\t[CLEAN]\t%s\n" "$(DIRECTORY)$$dir"
##############################################
qemu-5.1+dfsg/roms/SLOF/rtas/Makefile.inc-32-# Common RTAS files:
qemu-5.1+dfsg/roms/SLOF/rtas/Makefile.inc:33:RTAS_SRC_ASM = reloc.S rtas_common.S rtas_entry.S rtas_term.S \
qemu-5.1+dfsg/roms/SLOF/rtas/Makefile.inc-34- rtas_cpu.S rtas_flash_asm.S rtas_mem.S rtas_ras.S
##############################################
qemu-5.1+dfsg/roms/SLOF/rtas/Makefile.inc-38-RTAS_SRCS = $(RTAS_SRC_ASM) $(RTAS_SRC_C)
qemu-5.1+dfsg/roms/SLOF/rtas/Makefile.inc:39:RTAS_OBJ_ASM = $(RTAS_SRC_ASM:%.S=%.o)
qemu-5.1+dfsg/roms/SLOF/rtas/Makefile.inc-40-RTAS_OBJ_C = $(RTAS_SRC_C:%.c=%.o)
##############################################
qemu-5.1+dfsg/roms/SLOF/rtas/rtas_call.c-41-Decription: Handle RTAS call. This C function is called
qemu-5.1+dfsg/roms/SLOF/rtas/rtas_call.c:42: from the asm function rtas_entry.
qemu-5.1+dfsg/roms/SLOF/rtas/rtas_call.c-43-*/
##############################################
qemu-5.1+dfsg/roms/SLOF/rtas/rtas.lds-31- . = ALIGN(256);
qemu-5.1+dfsg/roms/SLOF/rtas/rtas.lds:32: _got = DEFINED (.TOC.) ? .TOC. : ADDR (.got) + 0x8000;
qemu-5.1+dfsg/roms/SLOF/rtas/rtas.lds-33- *(.got .toc)
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/debug.fs-29-\ Search for xt of given address
qemu-5.1+dfsg/roms/SLOF/slof/fs/debug.fs:30:: find-xt-addr ( addr -- xt )
qemu-5.1+dfsg/roms/SLOF/slof/fs/debug.fs-31- BEGIN
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/debug.fs-58- ['] tib here within IF
qemu-5.1+dfsg/roms/SLOF/slof/fs/debug.fs:59: dup rpick find-xt-addr (.xt)
qemu-5.1+dfsg/roms/SLOF/slof/fs/debug.fs-60- THEN
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/fbuffer.fs-59-: fb8-columns2bytes ( #columns -- #bytes ) char-width * screen-depth * ;
qemu-5.1+dfsg/roms/SLOF/slof/fs/fbuffer.fs:60:: fb8-line2addr ( line# -- addr )
qemu-5.1+dfsg/roms/SLOF/slof/fs/fbuffer.fs-61- char-height * window-top + screen-line-bytes *
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/fcode/core.fs-120- read-byte \ get string length ( -- len )
qemu-5.1+dfsg/roms/SLOF/slof/fs/fcode/core.fs:121: next-ip get-ip \ get string addr ( -- len str )
qemu-5.1+dfsg/roms/SLOF/slof/fs/fcode/core.fs-122- swap \ type needs the parameters swapped ( -- str len )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-helper.fs-29-\ convert busnr devnr to addr
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-helper.fs:30:: pci-bus2addr ( busnr devnr -- addr ) B lshift swap 10 lshift + ;
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-helper.fs-31-
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-helper.fs-94-\ calc the address of the next capability
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-helper.fs:95:: pci-cap-next-addr ( cap-addr -- next-cap-addr ) 1+ dup pci-cap-next dup IF swap -100 and + ELSE nip THEN ;
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-helper.fs-96-
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-266- 20 lshift + -10 and >r \ | calc 64 bit value and save it ( paddr plen baddr R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:267: 82000000 or encode-int+ \ | Encode config addr ( paddr plen R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:268: r> encode-64+ \ | Encode assigned addr ( paddr plen R: size )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-269- r> encode-64+ \ | Encode size ( paddr plen )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-282- 20 lshift + -10 and >r \ | calc 64 bit value and save it ( paddr plen baddr R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:283: C3000000 or encode-int+ \ | Encode config addr ( paddr plen R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:284: r> encode-64+ \ | Encode assigned addr ( paddr plen R: size )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-285- r> encode-64+ \ | Encode size ( paddr plen )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-297- -10 and >r \ | calc 32 bit value and save it ( paddr plen baddr R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:298: 82000000 or encode-int+ \ | Encode config addr ( paddr plen R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:299: r> encode-64+ \ | Encode assigned addr ( paddr plen R: size )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-300- r> encode-64+ \ | Encode size ( paddr plen )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-312- -10 and >r \ | calc 32 bit value and save it ( paddr plen baddr R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:313: C2000000 or encode-int+ \ | Encode config addr ( paddr plen R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:314: r> encode-64+ \ | Encode assigned addr ( paddr plen R: size )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-315- r> encode-64+ \ | Encode size ( paddr plen )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-327- -4 and >r \ | calc 32 bit value and save it ( paddr plen baddr R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:328: 81000000 or encode-int+ \ | Encode config addr ( paddr plen R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:329: r> encode-64+ \ | Encode assigned addr ( paddr plen R: size )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-330- r> encode-64+ \ | Encode size ( paddr plen )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-342- FFFFF800 and >r \ | calc 32 bit value and save it ( paddr plen baddr R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:343: 82000000 or encode-int+ \ | Encode config addr ( paddr plen R: size val )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:344: r> encode-64+ \ | Encode assigned addr ( paddr plen R: size )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-345- r> encode-64+ \ | Encode size ( paddr plen )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-463- 1 encode-int s" #interrupt-cells" property \ encode the cell#
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:464: f800 encode-int 0 encode-int+ 0 encode-int+ \ encode the bit mask for config addr (Dev only)
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-465- 7 encode-int+ s" interrupt-map-mask" property \ encode IRQ#=7 and generate property
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-571- 18 10 DO \ | loop over all BARs
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:572: 2 pick i + \ | calc bar-addr ( caddr paddr plen baddr )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-573- encode-bar \ | encode this BAR ( caddr paddr plen blen )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-578- 28 10 DO \ | loop over all BARs
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs:579: 2 pick i + \ | calc bar-addr ( caddr paddr plen baddr )
qemu-5.1+dfsg/roms/SLOF/slof/fs/pci-properties.fs-580- encode-bar \ | encode this BAR ( caddr paddr plen blen )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/translate.fs-27- IF 2drop -1 EXIT THEN 4 / 5 /
qemu-5.1+dfsg/roms/SLOF/slof/fs/translate.fs:28: \ advance (phys-addr(3) size(2)) steps
qemu-5.1+dfsg/roms/SLOF/slof/fs/translate.fs-29- 0 DO
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/translate.fs-43- THEN
qemu-5.1+dfsg/roms/SLOF/slof/fs/translate.fs:44: \ advance in 4 byte steps and (phys-addr(3) size(2)) steps
qemu-5.1+dfsg/roms/SLOF/slof/fs/translate.fs-45- 4 5 * +
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/fs/usb/dev-storage.fs-155-: build-cbw ( tag xfer-len dir lun cmd-len addr -- )
qemu-5.1+dfsg/roms/SLOF/slof/fs/usb/dev-storage.fs:156: TO cbw-addr ( tag xfer-len dir lun cmd-len )
qemu-5.1+dfsg/roms/SLOF/slof/fs/usb/dev-storage.fs-157- cbw-addr cbw-length erase ( tag xfer-len dir lun cmd-len )
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc-59-ifeq ($(V),1)
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc:60: printf "\t[FPP]\t%s\n" `basename "$@"`
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc-61-endif
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc-142- @for i in $(OF_FFS_FILES) ; do \
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc:143: CURRENTDIR=`pwd` ; cd `dirname $$i` ; \
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc-144- DIRNAME=`pwd` ; cd $$CURRENTDIR ; \
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc:145: echo `basename $$i | sed -e s/\.fsi/\.fs/` \
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc:146: $$DIRNAME/`basename $$i` 0 0 >> OF.ffs ; \
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc-147- done
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc-169- cpp -M -MG $(FPPFLAGS) $(FPPINCLUDES) -MT $$i \
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc:170: `echo $$i | sed -e 's/\.fsi/\.fs/'` >> Makefile.dep ; \
qemu-5.1+dfsg/roms/SLOF/slof/Makefile.inc-171- done
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-20- unsigned long hid0 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:21: asm volatile("sync ; mtspr 1008,%0 ; mfspr %0,1008 ; mfspr %0,1008 ; mfspr %0,1008 ; mfspr %0,1008 ; mfspr %0,1008 ; mfspr %0,1008" : "+r"(hid0));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-22- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-26- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:27: asm volatile("mfspr %0,1008" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-28-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-31- unsigned long hid1 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:32: asm volatile("mtspr 1009,%0 ; mtspr 1009,%0 ; isync" : : "r"(hid1));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-33- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-37- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:38: asm volatile("mfspr %0,1009" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-39-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-42- unsigned long hid4 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:43: asm volatile("sync ; mtspr 1012,%0 ; isync" : : "r"(hid4));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-44- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-48- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:49: asm volatile("mfspr %0,1012" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-50-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-53- unsigned long hid5 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:54: asm volatile("mtspr 1014,%0" : : "r"(hid5));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-55- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-59- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:60: asm volatile("mfspr %0,1014" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-61-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-65- unsigned long msr = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:66: asm volatile("mtmsrd %0" : : "r"(msr));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-67- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-71- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:72: asm volatile("mfmsr %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-73-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-76- unsigned long sdr1 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:77: asm volatile("mtsdr1 %0" : : "r"(sdr1));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-78- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-82- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:83: asm volatile("mfsdr1 %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-84-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-87- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:88: asm volatile("mfpvr %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-89-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-92- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:93: asm volatile("mfspr %0,1023" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-94-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-97- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:98: asm volatile("mftbl %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-99-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-102- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:103: asm volatile("mftbu %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-104-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-107- unsigned long dabr = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:108: asm volatile("mtspr 1013,%0" : : "r"(dabr));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-109- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-113- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:114: asm volatile("mfspr %0,1013" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-115-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-118- unsigned long dabr = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:119: asm volatile("mtspr 311,%0" : : "r"(dabr));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-120- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-124- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:125: asm volatile("mfspr %0,311" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-126-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-131- unsigned long sprg0 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:132: asm volatile("mtsprg0 %0" : "+r"(sprg0));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-133- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-137- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:138: asm volatile("mfsprg0 %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-139-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-142- unsigned long sprg1 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:143: asm volatile("mtsprg1 %0" : "+r"(sprg1));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-144- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-148- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:149: asm volatile("mfsprg1 %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-150-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-153- unsigned long sprg2 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:154: asm volatile("mtsprg2 %0" : "+r"(sprg2));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-155- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-159- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:160: asm volatile("mfsprg2 %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-161-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-164- unsigned long sprg3 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:165: asm volatile("mtsprg3 %0" : "+r"(sprg3));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-166- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-170- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:171: asm volatile("mfsprg3 %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-172-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-175- unsigned long hsprg0 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:176: asm volatile("mtspr 304,%0" : "+r"(hsprg0));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-177- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-181- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:182: asm volatile("mfspr %0,304" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-183-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-186- unsigned long hsprg1 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:187: asm volatile("mtspr 305,%0" : "+r"(hsprg1));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-188- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-192- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:193: asm volatile("mfspr %0,305" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-194-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-198- unsigned long mmcr0 = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:199: asm volatile("sync ; mtspr 795,%0 ; isync" : : "r"(mmcr0));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-200- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-204- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:205: asm volatile("sync ; mfspr %0,787" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-206-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-208-PRIM(ICBI)
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:209: asm volatile("dcbst 0,%0 ; sync ; icbi 0,%0 ; sync ; isync" : : "r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-210- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-246- unsigned long dec = TOS.u;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:247: asm volatile("mtdec %0" : "+r"(dec));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-248- POP;
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-252- PUSH;
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code:253: asm volatile("mfdec %0" : "=r"(TOS));
qemu-5.1+dfsg/roms/SLOF/slof/ppc64.code-254-MIRP
##############################################
qemu-5.1+dfsg/roms/SLOF/slof/prim.code-23-#define PRIM(name) code_##name: { \
qemu-5.1+dfsg/roms/SLOF/slof/prim.code:24: asm volatile ("#### " #name : : : "memory"); \
qemu-5.1+dfsg/roms/SLOF/slof/prim.code-25- void *w = (cfa = (++ip)->a)->a;
##############################################
qemu-5.1+dfsg/roms/SLOF/tools/create_reloc_table.sh-14-
qemu-5.1+dfsg/roms/SLOF/tools/create_reloc_table.sh:15:CROSSTMP=`grep ^CROSS $(dirname $0)/../make.rules | cut -d\ -f2`
qemu-5.1+dfsg/roms/SLOF/tools/create_reloc_table.sh-16-
##############################################
qemu-5.1+dfsg/roms/SLOF/tools/create_reloc_table.sh-24-
qemu-5.1+dfsg/roms/SLOF/tools/create_reloc_table.sh:25:DIRNAME=`dirname $0`
qemu-5.1+dfsg/roms/SLOF/tools/create_reloc_table.sh-26-
##############################################
qemu-5.1+dfsg/roms/SLOF/Makefile.gen-40-
qemu-5.1+dfsg/roms/SLOF/Makefile.gen:41:FLASH_SIZE_MB = `echo $$[ $(FLASH_SIZE)/1024/1024 ]`
qemu-5.1+dfsg/roms/SLOF/Makefile.gen-42-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/api/api.c-527- /* start over */
qemu-5.1+dfsg/roms/u-boot-sam460ex/api/api.c:528: *next = ((char *)env_get_addr(0));
qemu-5.1+dfsg/roms/u-boot-sam460ex/api/api.c-529- else {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/api/api.c-550-
qemu-5.1+dfsg/roms/u-boot-sam460ex/api/api.c:551: *next = ((char *)env_get_addr(i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/api/api.c-552- return 0;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1136/cpu.c-73-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1136/cpu.c:74: asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1136/cpu.c:75: asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1136/cpu.c:76: asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1136/cpu.c-77-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1176/cpu.c-63- /* invalidate both caches and flush btb */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1176/cpu.c:64: asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1176/cpu.c-65- /* mem barrier to sync things */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1176/cpu.c:66: asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm1176/cpu.c-67-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm720t/cpu.c-82-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm720t/cpu.c:83: asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm720t/cpu.c-84-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/at91rm9200/ether.c-195-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/at91rm9200/ether.c:196: eth_getenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/at91rm9200/ether.c-197-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/cpu.c-66-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/cpu.c:67: asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/cpu.c-68-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm925t/cpu.c-64-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm925t/cpu.c:65: asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm925t/cpu.c-66-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm926ejs/cpu.c-63-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm926ejs/cpu.c:64: asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm926ejs/cpu.c-65-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm946es/cpu.c-66-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm946es/cpu.c:67: asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm946es/cpu.c:68: asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm946es/cpu.c-69-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/cpu.c-81-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/cpu.c:82: asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/cpu.c-83-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/cpu.c-48-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/cpu.c:49: asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/cpu.c-50-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/cpu.c-103-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/cpu.c:104: asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/cpu.c-105-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h-96- * Retrieve the number of leading zero bits starting from the MSB
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h:97: * This function is implemented as an (extremely fast) asm routine
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/npe/include/IxQMgrDispatcher_p.h-98- * for XSCALE processor (see clz instruction) and as a (slower) C
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/npe/npe.c-574- if (eth_num == 1) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/npe/npe.c:575: if (!eth_getenv_enetaddr("eth1addr", enetaddr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/npe/npe.c-576- continue;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/npe/npe.c-578-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/npe/npe.c:579: if (!eth_getenv_enetaddr("ethaddr", enetaddr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/ixp/npe/npe.c-580- continue;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/cpu.c-63-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/cpu.c:64: asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/cpu.c-65-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/pxa/cpu.c-65-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/pxa/cpu.c:66: asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/pxa/cpu.c-67-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/sa1100/cpu.c-68-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/sa1100/cpu.c:69: asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/cpu/sa1100/cpu.c-70-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h-38-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h:39:#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h-40-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h-40-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h:41:#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c)))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h:42:#define get_eni_ctl_reg_addr(minor) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h:43: (get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h-44-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h-60-#define NETARM_ENI_ENI_PULSED_INTR (0x34)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h:61:#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h-62-#define NETARM_ENI_ENI_SHARED (0x3c)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h-39-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h:40:#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c)))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h-41-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h-56-#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h:57:#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h-58-#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h-43-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h:44:#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h-45-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-44-#define NETARM_MEM_MODULE_CONFIG (0x00)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h:45:#define NETARM_MEM_CS0_BASE_ADDR (0x10)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-46-#define NETARM_MEM_CS0_OPTIONS (0x14)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h:47:#define NETARM_MEM_CS1_BASE_ADDR (0x20)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-48-#define NETARM_MEM_CS1_OPTIONS (0x24)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h:49:#define NETARM_MEM_CS2_BASE_ADDR (0x30)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-50-#define NETARM_MEM_CS2_OPTIONS (0x34)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h:51:#define NETARM_MEM_CS3_BASE_ADDR (0x40)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-52-#define NETARM_MEM_CS3_OPTIONS (0x44)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h:53:#define NETARM_MEM_CS4_BASE_ADDR (0x50)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-54-#define NETARM_MEM_CS4_OPTIONS (0x54)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-69-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h:70:#define NETARM_MEM_CFG_A27_ADDR (0x00080000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-71-#define NETARM_MEM_CFG_A27_CS0OE (0x00000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-72-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h:73:#define NETARM_MEM_CFG_A26_ADDR (0x00040000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-74-#define NETARM_MEM_CFG_A26_CS0WE (0x00000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-75-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h:76:#define NETARM_MEM_CFG_A25_ADDR (0x00020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h-77-#define NETARM_MEM_CFG_A25_BLAST (0x00000000)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h-41-#ifdef CONFIG_SOC_DM365
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h:42:#define EMAC_BASE_ADDR (0x01d07000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h:43:#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h:44:#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h:45:#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h-46-#define DAVINCI_EMAC_VERSION2
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h-53-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h:54:#define EMAC_BASE_ADDR (0x01c80000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h:55:#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h:56:#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h:57:#define EMAC_MDIO_BASE_ADDR (0x01c84000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h-58-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h-369-int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h:370:void davinci_eth_set_mac_addr(const u_int8_t *addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/emac_defs.h-371-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/hardware.h-428-#define DAVINCI_UART_CTRL_BASE 0x28
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/hardware.h:429:#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/hardware.h:430:#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/hardware.h:431:#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-davinci/hardware.h-432-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h-127-#define PCI_PCIDOORBELL_OFFSET (0x3C)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:128:#define PCI_ATPDMA0_AHBADDR (0x40)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:129:#define PCI_ATPDMA0_PCIADDR (0x44)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:130:#define PCI_ATPDMA0_LENADDR (0x48)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:131:#define PCI_ATPDMA1_AHBADDR (0x4C)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:132:#define PCI_ATPDMA1_PCIADDR (0x50)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:133:#define PCI_ATPDMA1_LENADDR (0x54)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:134:#define PCI_PTADMA0_AHBADDR (0x58)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:135:#define PCI_PTADMA0_PCIADDR (0x5C)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:136:#define PCI_PTADMA0_LENADDR (0x60)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:137:#define PCI_PTADMA1_AHBADDR (0x64)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:138:#define PCI_PTADMA1_PCIADDR (0x68)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h:139:#define PCI_PTADMA1_LENADDR (0x6C)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-ixp/ixp425pci.h-140-*/
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-kirkwood/cpu.h-93- unsigned int val;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-kirkwood/cpu.h:94: asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-kirkwood/cpu.h-95- (val)::"cc");
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-kirkwood/cpu.h-104-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-kirkwood/cpu.h:105: asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-kirkwood/cpu.h-106- (val):"cc");
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h-42-#define DEBUG_BASE_ADDR 0x60000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:43:#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:44:#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:45:#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:46:#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:47:#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:48:#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:49:#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:50:#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h-51-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h-56-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:57:#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:58:#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:59:#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:60:#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:61:#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:62:#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:63:#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:64:#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:65:#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:66:#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:67:#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:68:#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h-69-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h-74-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:75:#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:76:#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:77:#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:78:#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:79:#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:80:#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:81:#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:82:#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:83:#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:84:#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:85:#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:86:#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:87:#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:88:#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:89:#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:90:#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:91:#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:92:#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:93:#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:94:#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h-95-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h-100-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:101:#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:102:#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:103:#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:104:#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:105:#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:106:#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:107:#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:108:#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:109:#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:110:#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:111:#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:112:#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:113:#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:114:#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:115:#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:116:#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:117:#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:118:#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:119:#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:120:#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:121:#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:122:#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:123:#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:124:#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:125:#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:126:#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:127:#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:128:#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:129:#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:130:#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:131:#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h:132:#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-mx51/imx-regs.h-133-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/cpu.h-144- unsigned int val;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/cpu.h:145: asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/cpu.h-146- (val) : : "cc");
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/cpu.h-155-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/cpu.h:156: asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/cpu.h-157- (val) : "cc");
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-pxa/pxa-regs.h-295-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-pxa/pxa-regs.h:296:#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-pxa/pxa-regs.h:297:#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-pxa/pxa-regs.h-298-#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/s3c6400.h-579-#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/s3c6400.h:580:#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/arch-s3c64xx/s3c6400.h-581-#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/cache.h-36-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/cache.h:37: asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/cache.h-38- : : "r" (val) : "cc");
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/global_data.h-69-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/global_data.h:70:#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/global_data.h-71-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/io.h-246- * Define:
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/io.h:247: * iomem_valid_addr(off,size)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/io.h-248- * iomem_to_phys(off)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/io.h-254- void *_ret = (void *)0; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/io.h:255: if (iomem_valid_addr(_off, _size)) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/io.h-256- _ret = __ioremap(iomem_to_phys(_off),_size,nocache); \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/processor.h-17- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/processor.h:18:#define current_text_addr() ({ __label__ _l; _l: &&_l;})
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/processor.h-19-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/string.h-5- * We don't do inline string functions, since the
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/string.h:6: * optimised inline asm versions are not small.
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/string.h-7- */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/system.h-51- * the compiler from one version to another so a bit of paranoia won't hurt.
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/system.h:52: * This string is meant to be concatenated with the inline asm string and
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/system.h-53- * will cause compilation to stop on mismatch.
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/system.h-72-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/system.h:73: asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/include/asm/system.h-74- : : "r" (val) : "cc");
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-80-#ifdef CONFIG_DRIVER_RTL8019
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c:81:extern void rtl8019_get_enetaddr (uchar * addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-82-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-362- /* IP Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c:363: gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-364-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-390- /* XXX: this needs to be moved to board init */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c:391:extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-392- if (getenv ("ethaddr")) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-393- uchar enetaddr[6];
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c:394: eth_getenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c:395: davinci_eth_set_mac_addr(enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-396- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-402- uchar enetaddr[6];
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c:403: eth_getenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c:404: smc_set_mac_addr(enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/arm/lib/board.c-405- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/cpu/cpu.c-65- sysreg_write(EVBA, (unsigned long)&_evba);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/cpu/cpu.c:66: asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/cpu/cpu.c-67-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/cpu/cpu.c-73- /* Flush both caches and the write buffer */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/cpu/cpu.c:74: asm volatile("cache %0[4], 010\n\t"
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/cpu/cpu.c-75- "cache %0[0], 000\n\t"
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/cpu/cpu.c-85- /* Flush the pipeline before we declare it a failure */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/cpu/cpu.c:86: asm volatile("sub pc, pc, -4");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/cpu/cpu.c-87-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-37-/* Returns the physical address of a PnSEG (n=1,2) address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:38:#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-39-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-42- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:43:#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:44:#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:45:#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:46:#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-47-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-50-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:51: return PHYSADDR(address);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-52-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-55-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:56: return (void *)P1SEGADDR(address);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-57-}
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-58-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:59:#define cached(addr) ((void *)P1SEGADDR(addr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:60:#define uncached(addr) ((void *)P2SEGADDR(addr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-61-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-78- if (flags == MAP_WRBACK)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:79: return (void *)P1SEGADDR(paddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-80- else
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h:81: return (void *)P2SEGADDR(paddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/addrspace.h-82-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-33-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h:34: asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-35-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-42-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h:43: asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-44-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-51-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h:52: asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-53-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-60-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h:61: asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-62-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-74-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h:75: asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-76-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-80- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h:81:#define sync_write_buffer() asm volatile("sync 0" : : : "memory")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/arch-at32ap700x/cacheflush.h-82-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/processor.h-26-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/processor.h:27:#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; })
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/processor.h-28-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/processor.h-51-#define cpu_relax() barrier()
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/processor.h:52:#define cpu_sync_pipeline() asm volatile("sub pc, -2" : : : "memory")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/include/asm/processor.h-53-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/board.c-333-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/board.c:334: bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/board.c-335-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/bootm.c-191- params = setup_ramdisk_tag(params,
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/bootm.c:192: PHYSADDR(images->rd_start),
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/bootm.c:193: PHYSADDR(images->rd_end));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/bootm.c-194- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/interrupts.c-27-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/interrupts.c:28: asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/interrupts.c-29-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/interrupts.c-35- sr = sysreg_read(SR);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/interrupts.c:36: asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/avr32/lib/interrupts.c-37-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/bootrom-asm-offsets.c.in-8-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/bootrom-asm-offsets.c.in:9:#define _DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/bootrom-asm-offsets.c.in-10-#define DEFINE(s, m) _DEFINE(offset_##s##_##m, offsetof(s, m))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/cache.S-16-/* Since all L1 caches work the same way, we use the same method for flushing
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/cache.S:17: * them. Only the actual flush instruction differs. We write this in asm as
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/cache.S-18- * GCC can be hard to coax into writing nice hardware loops.
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/initcode.c-61- while (i--)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/initcode.c:62: asm volatile("" : : : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/initcode.c-63- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/interrupts.c-87-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/interrupts.c:88: asm volatile (" %0 = CYCLES;" : "=r" (start));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/interrupts.c-89- do {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/interrupts.c:90: asm volatile (" %0 = CYCLES; " : "=r" (stop));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/interrupts.c-91- } while (stop - start < delay);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/os_log.c-11-#define OS_LOG_MAGIC 0xDEADBEEF
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/os_log.c:12:#define OS_LOG_MAGIC_ADDR ((unsigned long *)0x4f0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/os_log.c:13:#define OS_LOG_PTR_ADDR ((char **)0x4f4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/os_log.c-14-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/traps.c-127-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/traps.c:128: new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/traps.c-129-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/traps.c-330- if (fp->seqstat & EXCAUSE) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/traps.c:331: decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/traps.c-332- printf("DCPLB_FAULT_ADDR: %s\n", buf);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/traps.c:333: decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/cpu/traps.c-334- printf("ICPLB_FAULT_ADDR: %s\n", buf);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/config.h-112-#ifndef CONFIG_SYS_GBL_DATA_ADDR
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/config.h:113:# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/config.h-114-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/global_data.h-69-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/global_data.h:70:#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/global_data.h-71-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-447-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:448:#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:449:#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:450:#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-451-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-468-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:469:#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:470:#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:471:#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-472-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-486-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:487:#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:488:#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:489:#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-490-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-507-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:508:#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:509:#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:510:#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-511-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-525-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:526:#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:527:#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:528:#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-529-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-546-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:547:#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:548:#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:549:#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-550-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-564-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:565:#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:566:#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:567:#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-568-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-585-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:586:#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:587:#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:588:#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-589-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-603-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:604:#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:605:#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:606:#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-607-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-624-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:625:#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:626:#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:627:#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-628-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-642-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:643:#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:644:#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:645:#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-646-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-663-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:664:#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:665:#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:666:#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-667-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-681-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:682:#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:683:#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:684:#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-685-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-702-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:703:#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:704:#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:705:#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-706-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-720-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:721:#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:722:#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:723:#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-724-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-741-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:742:#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:743:#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:744:#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-745-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-759-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:760:#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:761:#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:762:#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-763-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-780-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:781:#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:782:#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:783:#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-784-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-798-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:799:#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:800:#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:801:#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-802-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-819-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:820:#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:821:#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:822:#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-823-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-837-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:838:#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:839:#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:840:#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-841-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-858-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:859:#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:860:#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:861:#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-862-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-876-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:877:#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:878:#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:879:#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-880-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-897-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:898:#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:899:#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:900:#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-901-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-915-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:916:#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:917:#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:918:#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-919-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-936-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:937:#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:938:#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:939:#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-940-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-954-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:955:#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:956:#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:957:#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-958-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-975-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:976:#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:977:#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:978:#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-979-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-993-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:994:#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:995:#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:996:#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-997-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1014-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1015:#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1016:#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1017:#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1018-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1032-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1033:#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1034:#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1035:#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1036-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1053-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1054:#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1055:#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1056:#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1057-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1095-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1096:#define pTWI_SLAVE_ADDR ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1097:#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1098:#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1099-#define pTWI_MASTER_CTL ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1104-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1105:#define pTWI_MASTER_ADDR ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1106:#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1107:#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1108-#define pTWI_INT_STAT ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1467-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1468:#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1469:#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h:1470:#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h-1471-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h-36-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h:37:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h:38:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h:39:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h-40-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h-45-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h:46:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h:47:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h:48:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h-49-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h-159-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h:160:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h:161:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h:162:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h-163-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h-36-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h:37:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h:38:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h:39:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h-40-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h-45-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h:46:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h:47:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h:48:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h-49-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h-159-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h:160:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h:161:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h:162:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h-163-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h-36-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:37:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:38:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:39:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h-40-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h-45-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:46:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:47:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:48:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h-49-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h-159-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:160:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:161:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:162:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h-163-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h-339-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:340:#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:341:#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h:342:#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h-343-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h-36-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:37:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:38:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:39:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h-40-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h-45-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:46:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:47:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:48:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h-49-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h-159-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:160:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:161:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:162:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h-163-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h-339-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:340:#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:341:#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h:342:#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h-343-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h-36-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:37:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:38:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:39:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h-40-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h-45-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:46:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:47:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:48:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h-49-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h-159-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:160:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:161:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:162:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h-163-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h-576-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:577:#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:578:#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h:579:#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h-580-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h-36-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:37:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:38:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:39:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h-40-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h-45-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:46:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:47:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:48:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h-49-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h-159-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:160:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:161:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:162:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h-163-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h-576-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:577:#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:578:#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h:579:#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h-580-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-447-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:448:#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:449:#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:450:#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-451-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-468-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:469:#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:470:#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:471:#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-472-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-486-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:487:#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:488:#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:489:#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-490-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-507-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:508:#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:509:#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:510:#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-511-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-525-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:526:#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:527:#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:528:#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-529-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-546-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:547:#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:548:#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:549:#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-550-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-564-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:565:#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:566:#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:567:#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-568-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-585-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:586:#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:587:#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:588:#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-589-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-603-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:604:#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:605:#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:606:#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-607-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-624-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:625:#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:626:#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:627:#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-628-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-642-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:643:#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:644:#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:645:#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-646-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-663-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:664:#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:665:#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:666:#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-667-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-681-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:682:#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:683:#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:684:#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-685-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-702-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:703:#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:704:#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:705:#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-706-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-720-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:721:#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:722:#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:723:#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-724-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-741-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:742:#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:743:#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:744:#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-745-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-759-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:760:#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:761:#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:762:#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-763-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-780-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:781:#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:782:#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:783:#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-784-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-798-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:799:#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:800:#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:801:#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-802-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-819-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:820:#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:821:#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:822:#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-823-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-837-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:838:#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:839:#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:840:#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-841-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-858-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:859:#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:860:#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:861:#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-862-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-876-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:877:#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:878:#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:879:#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-880-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-897-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:898:#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:899:#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:900:#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-901-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-915-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:916:#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:917:#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:918:#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-919-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-936-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:937:#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:938:#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:939:#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-940-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-954-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:955:#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:956:#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:957:#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-958-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-975-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:976:#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:977:#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:978:#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-979-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-993-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:994:#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:995:#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:996:#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-997-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1014-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1015:#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1016:#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1017:#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1018-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1032-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1033:#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1034:#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1035:#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1036-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1053-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1054:#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1055:#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1056:#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1057-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1095-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1096:#define pTWI_SLAVE_ADDR ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1097:#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1098:#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1099-#define pTWI_MASTER_CTL ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1104-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1105:#define pTWI_MASTER_ADDR ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1106:#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:1107:#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-1108-#define pTWI_INT_STAT ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-2418-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:2419:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:2420:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:2421:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-2422-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-2427-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:2428:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:2429:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:2430:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-2431-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-2541-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:2542:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:2543:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h:2544:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h-2545-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-89-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:90:#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:91:#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:92:#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-93-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-110-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:111:#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:112:#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:113:#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-114-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-128-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:129:#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:130:#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:131:#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-132-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-149-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:150:#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:151:#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:152:#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-153-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-167-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:168:#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:169:#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:170:#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-171-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-188-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:189:#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:190:#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:191:#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-192-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-206-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:207:#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:208:#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:209:#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-210-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-227-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:228:#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:229:#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:230:#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-231-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-245-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:246:#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:247:#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:248:#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-249-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-266-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:267:#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:268:#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:269:#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-270-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-284-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:285:#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:286:#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:287:#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-288-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-305-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:306:#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:307:#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:308:#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-309-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-323-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:324:#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:325:#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:326:#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-327-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-344-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:345:#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:346:#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:347:#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-348-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-362-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:363:#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:364:#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:365:#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-366-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-383-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:384:#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:385:#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:386:#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-387-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-401-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:402:#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:403:#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:404:#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-405-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-422-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:423:#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:424:#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:425:#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-426-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-440-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:441:#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:442:#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:443:#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-444-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-461-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:462:#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:463:#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:464:#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-465-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-479-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:480:#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:481:#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:482:#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-483-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-500-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:501:#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:502:#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:503:#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-504-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-518-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:519:#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:520:#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:521:#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-522-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-539-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:540:#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:541:#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:542:#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-543-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-557-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:558:#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:559:#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:560:#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-561-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-578-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:579:#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:580:#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:581:#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-582-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-596-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:597:#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:598:#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:599:#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-600-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-617-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:618:#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:619:#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:620:#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-621-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-635-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:636:#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:637:#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:638:#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-639-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-656-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:657:#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:658:#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:659:#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-660-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-674-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:675:#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:676:#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:677:#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-678-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-695-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:696:#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:697:#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:698:#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-699-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-713-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:714:#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:715:#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:716:#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-717-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-734-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:735:#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:736:#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:737:#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-738-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-752-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:753:#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:754:#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:755:#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-756-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-773-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:774:#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:775:#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:776:#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-777-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-791-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:792:#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:793:#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:794:#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-795-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-812-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:813:#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:814:#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:815:#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-816-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-830-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:831:#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:832:#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:833:#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-834-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-851-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:852:#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:853:#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:854:#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-855-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-869-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:870:#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:871:#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:872:#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-873-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-890-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:891:#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:892:#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:893:#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-894-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-908-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:909:#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:910:#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:911:#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-912-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-929-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:930:#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:931:#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:932:#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-933-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-947-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:948:#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:949:#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:950:#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-951-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-968-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:969:#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:970:#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:971:#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-972-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-986-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:987:#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:988:#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:989:#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-990-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1007-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1008:#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1009:#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1010:#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1011-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1025-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1026:#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1027:#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1028:#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1029-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1046-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1047:#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1048:#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1049:#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1050-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1064-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1065:#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1066:#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1067:#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1068-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1085-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1086:#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1087:#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1088:#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1089-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1103-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1104:#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1105:#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1106:#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1107-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1124-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1125:#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1126:#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1127:#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1128-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1142-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1143:#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1144:#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1145:#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1146-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1163-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1164:#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1165:#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1166:#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1167-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1181-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1182:#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1183:#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1184:#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1185-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1202-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1203:#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1204:#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1205:#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1206-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1220-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1221:#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1222:#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1223:#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1224-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1241-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1242:#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1243:#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1244:#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1245-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1259-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1260:#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1261:#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1262:#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1263-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1280-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1281:#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1282:#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1283:#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1284-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1298-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1299:#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1300:#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1301:#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1302-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1319-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1320:#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1321:#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:1322:#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-1323-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-2189-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:2190:#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:2191:#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:2192:#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-2193-#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-2294-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:2295:#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:2296:#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:2297:#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-2298-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-3530-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:3531:#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:3532:#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:3533:#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-3534-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-3539-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:3540:#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:3541:#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:3542:#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-3543-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-3869-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:3870:#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:3871:#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h:3872:#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h-3873-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-89-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:90:#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:91:#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:92:#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-93-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-110-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:111:#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:112:#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:113:#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-114-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-128-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:129:#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:130:#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:131:#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-132-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-149-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:150:#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:151:#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:152:#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-153-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-167-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:168:#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:169:#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:170:#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-171-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-188-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:189:#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:190:#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:191:#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-192-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-206-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:207:#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:208:#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:209:#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-210-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-227-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:228:#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:229:#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:230:#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-231-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-245-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:246:#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:247:#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:248:#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-249-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-266-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:267:#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:268:#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:269:#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-270-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-284-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:285:#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:286:#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:287:#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-288-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-305-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:306:#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:307:#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:308:#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-309-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-323-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:324:#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:325:#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:326:#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-327-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-344-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:345:#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:346:#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:347:#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-348-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-362-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:363:#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:364:#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:365:#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-366-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-383-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:384:#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:385:#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:386:#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-387-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-401-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:402:#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:403:#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:404:#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-405-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-422-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:423:#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:424:#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:425:#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-426-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-440-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:441:#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:442:#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:443:#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-444-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-461-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:462:#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:463:#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:464:#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-465-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-479-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:480:#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:481:#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:482:#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-483-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-500-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:501:#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:502:#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:503:#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-504-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-518-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:519:#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:520:#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:521:#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-522-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-539-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:540:#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:541:#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:542:#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-543-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-557-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:558:#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:559:#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:560:#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-561-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-578-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:579:#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:580:#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:581:#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-582-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-596-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:597:#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:598:#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:599:#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-600-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-617-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:618:#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:619:#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:620:#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-621-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-635-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:636:#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:637:#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:638:#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-639-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-656-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:657:#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:658:#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:659:#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-660-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-674-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:675:#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:676:#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:677:#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-678-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-695-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:696:#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:697:#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:698:#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-699-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-713-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:714:#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:715:#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:716:#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-717-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-734-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:735:#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:736:#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:737:#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-738-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-752-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:753:#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:754:#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:755:#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-756-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-773-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:774:#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:775:#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:776:#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-777-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-791-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:792:#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:793:#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:794:#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-795-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-812-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:813:#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:814:#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:815:#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-816-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-830-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:831:#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:832:#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:833:#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-834-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-851-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:852:#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:853:#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:854:#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-855-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-869-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:870:#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:871:#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:872:#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-873-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-890-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:891:#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:892:#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:893:#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-894-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-908-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:909:#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:910:#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:911:#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-912-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-929-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:930:#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:931:#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:932:#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-933-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-947-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:948:#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:949:#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:950:#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-951-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-968-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:969:#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:970:#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:971:#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-972-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-986-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:987:#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:988:#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:989:#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-990-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1007-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1008:#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1009:#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1010:#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1011-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1025-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1026:#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1027:#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1028:#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1029-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1046-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1047:#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1048:#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1049:#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1050-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1064-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1065:#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1066:#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1067:#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1068-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1085-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1086:#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1087:#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1088:#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1089-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1103-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1104:#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1105:#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1106:#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1107-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1124-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1125:#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1126:#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1127:#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1128-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1142-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1143:#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1144:#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1145:#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1146-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1163-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1164:#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1165:#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1166:#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1167-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1181-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1182:#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1183:#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1184:#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1185-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1202-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1203:#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1204:#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1205:#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1206-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1220-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1221:#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1222:#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1223:#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1224-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1241-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1242:#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1243:#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1244:#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1245-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1259-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1260:#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1261:#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1262:#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1263-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1280-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1281:#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1282:#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1283:#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1284-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1298-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1299:#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1300:#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1301:#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1302-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1319-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1320:#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1321:#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:1322:#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-1323-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-2219-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:2220:#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:2221:#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:2222:#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-2223-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-4583-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4584:#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4585:#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4586:#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-4587-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-4592-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4593:#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4594:#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4595:#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-4596-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-4631-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4632:#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4633:#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4634:#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-4635-#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-4640-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4641:#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4642:#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h:4643:#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h-4644-#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-89-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:90:#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:91:#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:92:#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-93-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-110-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:111:#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:112:#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:113:#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-114-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-128-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:129:#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:130:#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:131:#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-132-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-149-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:150:#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:151:#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:152:#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-153-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-167-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:168:#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:169:#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:170:#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-171-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-188-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:189:#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:190:#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:191:#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-192-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-206-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:207:#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:208:#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:209:#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-210-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-227-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:228:#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:229:#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:230:#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-231-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-245-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:246:#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:247:#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:248:#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-249-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-266-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:267:#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:268:#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:269:#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-270-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-284-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:285:#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:286:#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:287:#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-288-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-305-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:306:#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:307:#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:308:#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-309-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-323-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:324:#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:325:#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:326:#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-327-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-344-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:345:#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:346:#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:347:#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-348-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-362-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:363:#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:364:#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:365:#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-366-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-383-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:384:#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:385:#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:386:#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-387-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-401-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:402:#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:403:#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:404:#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-405-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-422-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:423:#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:424:#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:425:#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-426-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-440-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:441:#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:442:#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:443:#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-444-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-461-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:462:#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:463:#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:464:#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-465-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-479-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:480:#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:481:#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:482:#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-483-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-500-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:501:#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:502:#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:503:#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-504-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-518-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:519:#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:520:#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:521:#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-522-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-539-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:540:#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:541:#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:542:#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-543-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-557-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:558:#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:559:#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:560:#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-561-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-578-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:579:#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:580:#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:581:#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-582-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-596-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:597:#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:598:#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:599:#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-600-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-617-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:618:#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:619:#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:620:#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-621-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-635-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:636:#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:637:#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:638:#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-639-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-656-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:657:#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:658:#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:659:#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-660-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-674-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:675:#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:676:#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:677:#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-678-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-695-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:696:#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:697:#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:698:#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-699-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-713-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:714:#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:715:#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:716:#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-717-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-734-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:735:#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:736:#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:737:#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-738-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-752-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:753:#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:754:#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:755:#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-756-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-773-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:774:#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:775:#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:776:#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-777-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-791-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:792:#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:793:#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:794:#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-795-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-812-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:813:#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:814:#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:815:#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-816-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-830-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:831:#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:832:#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:833:#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-834-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-851-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:852:#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:853:#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:854:#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-855-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-869-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:870:#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:871:#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:872:#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-873-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-890-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:891:#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:892:#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:893:#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-894-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-908-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:909:#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:910:#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:911:#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-912-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-929-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:930:#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:931:#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:932:#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-933-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-947-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:948:#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:949:#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:950:#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-951-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-968-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:969:#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:970:#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:971:#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-972-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-986-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:987:#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:988:#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:989:#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-990-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1007-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1008:#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1009:#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1010:#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1011-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1025-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1026:#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1027:#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1028:#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1029-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1046-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1047:#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1048:#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1049:#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1050-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1064-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1065:#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1066:#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1067:#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1068-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1085-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1086:#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1087:#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1088:#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1089-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1103-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1104:#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1105:#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1106:#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1107-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1124-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1125:#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1126:#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1127:#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1128-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1142-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1143:#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1144:#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1145:#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1146-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1163-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1164:#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1165:#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1166:#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1167-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1181-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1182:#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1183:#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1184:#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1185-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1202-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1203:#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1204:#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1205:#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1206-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1220-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1221:#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1222:#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1223:#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1224-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1241-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1242:#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1243:#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1244:#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1245-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1259-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1260:#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1261:#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1262:#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1263-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1280-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1281:#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1282:#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1283:#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1284-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1298-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1299:#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1300:#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1301:#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1302-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1319-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1320:#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1321:#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:1322:#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-1323-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2300-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2301:#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2302:#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2303:#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2304-#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2405-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2406:#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2407:#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2408:#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2409-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2618-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2619:#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2620:#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2621:#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2622-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2627-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2628:#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2629:#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2630:#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2631-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2666-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2667:#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2668:#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2669:#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2670-#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2675-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2676:#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2677:#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:2678:#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-2679-#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-3106-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:3107:#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:3108:#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h:3109:#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h-3110-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-89-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:90:#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:91:#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:92:#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-93-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-110-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:111:#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:112:#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:113:#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-114-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-128-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:129:#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:130:#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:131:#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-132-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-149-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:150:#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:151:#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:152:#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-153-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-167-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:168:#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:169:#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:170:#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-171-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-188-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:189:#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:190:#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:191:#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-192-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-206-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:207:#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:208:#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:209:#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-210-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-227-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:228:#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:229:#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:230:#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-231-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-245-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:246:#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:247:#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:248:#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-249-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-266-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:267:#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:268:#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:269:#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-270-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-284-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:285:#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:286:#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:287:#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-288-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-305-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:306:#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:307:#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:308:#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-309-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-323-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:324:#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:325:#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:326:#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-327-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-344-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:345:#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:346:#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:347:#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-348-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-362-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:363:#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:364:#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:365:#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-366-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-383-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:384:#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:385:#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:386:#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-387-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-401-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:402:#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:403:#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:404:#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-405-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-422-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:423:#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:424:#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:425:#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-426-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-440-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:441:#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:442:#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:443:#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-444-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-461-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:462:#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:463:#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:464:#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-465-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-479-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:480:#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:481:#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:482:#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-483-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-500-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:501:#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:502:#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:503:#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-504-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-518-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:519:#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:520:#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:521:#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-522-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-539-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:540:#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:541:#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:542:#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-543-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-557-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:558:#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:559:#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:560:#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-561-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-578-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:579:#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:580:#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:581:#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-582-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-596-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:597:#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:598:#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:599:#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-600-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-617-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:618:#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:619:#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:620:#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-621-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-635-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:636:#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:637:#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:638:#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-639-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-656-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:657:#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:658:#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:659:#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-660-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-674-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:675:#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:676:#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:677:#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-678-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-695-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:696:#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:697:#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:698:#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-699-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-713-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:714:#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:715:#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:716:#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-717-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-734-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:735:#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:736:#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:737:#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-738-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-752-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:753:#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:754:#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:755:#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-756-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-773-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:774:#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:775:#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:776:#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-777-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-791-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:792:#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:793:#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:794:#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-795-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-812-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:813:#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:814:#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:815:#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-816-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-830-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:831:#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:832:#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:833:#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-834-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-851-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:852:#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:853:#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:854:#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-855-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-869-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:870:#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:871:#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:872:#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-873-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-890-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:891:#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:892:#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:893:#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-894-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-908-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:909:#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:910:#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:911:#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-912-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-929-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:930:#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:931:#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:932:#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-933-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-947-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:948:#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:949:#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:950:#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-951-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-968-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:969:#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:970:#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:971:#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-972-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-986-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:987:#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:988:#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:989:#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-990-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1007-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1008:#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1009:#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1010:#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1011-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1025-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1026:#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1027:#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1028:#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1029-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1046-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1047:#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1048:#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1049:#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1050-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1064-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1065:#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1066:#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1067:#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1068-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1085-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1086:#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1087:#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1088:#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1089-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1103-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1104:#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1105:#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1106:#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1107-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1124-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1125:#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1126:#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1127:#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1128-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1142-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1143:#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1144:#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1145:#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1146-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1163-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1164:#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1165:#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1166:#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1167-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1181-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1182:#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1183:#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1184:#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1185-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1202-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1203:#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1204:#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1205:#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1206-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1220-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1221:#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1222:#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1223:#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1224-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1241-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1242:#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1243:#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1244:#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1245-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1259-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1260:#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1261:#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1262:#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1263-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1280-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1281:#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1282:#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1283:#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1284-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1298-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1299:#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1300:#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1301:#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1302-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1319-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1320:#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1321:#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:1322:#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-1323-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-2300-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:2301:#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:2302:#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:2303:#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-2304-#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-2405-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:2406:#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:2407:#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:2408:#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-2409-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-4790-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4791:#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4792:#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4793:#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-4794-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-4799-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4800:#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4801:#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4802:#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-4803-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-4838-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4839:#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4840:#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4841:#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-4842-#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-4847-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4848:#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4849:#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:4850:#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-4851-#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-5278-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:5279:#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:5280:#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h:5281:#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h-5282-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-89-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:90:#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:91:#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:92:#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-93-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-110-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:111:#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:112:#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:113:#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-114-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-128-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:129:#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:130:#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:131:#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-132-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-149-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:150:#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:151:#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:152:#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-153-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-167-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:168:#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:169:#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:170:#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-171-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-188-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:189:#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:190:#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:191:#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-192-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-206-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:207:#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:208:#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:209:#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-210-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-227-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:228:#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:229:#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:230:#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-231-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-245-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:246:#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:247:#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:248:#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-249-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-266-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:267:#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:268:#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:269:#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-270-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-284-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:285:#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:286:#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:287:#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-288-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-305-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:306:#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:307:#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:308:#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-309-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-323-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:324:#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:325:#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:326:#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-327-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-344-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:345:#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:346:#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:347:#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-348-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-362-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:363:#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:364:#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:365:#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-366-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-383-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:384:#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:385:#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:386:#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-387-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-401-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:402:#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:403:#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:404:#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-405-#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-422-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:423:#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:424:#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:425:#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-426-#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-440-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:441:#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:442:#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:443:#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-444-#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-461-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:462:#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:463:#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:464:#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-465-#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-479-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:480:#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:481:#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:482:#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-483-#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-500-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:501:#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:502:#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:503:#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-504-#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-518-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:519:#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:520:#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:521:#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-522-#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-539-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:540:#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:541:#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:542:#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-543-#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-557-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:558:#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:559:#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:560:#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-561-#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-578-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:579:#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:580:#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:581:#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-582-#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-596-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:597:#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:598:#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:599:#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-600-#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-617-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:618:#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:619:#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:620:#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-621-#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-635-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:636:#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:637:#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:638:#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-639-#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-656-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:657:#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:658:#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:659:#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-660-#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-674-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:675:#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:676:#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:677:#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-678-#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-695-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:696:#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:697:#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:698:#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-699-#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-713-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:714:#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:715:#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:716:#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-717-#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-734-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:735:#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:736:#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:737:#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-738-#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-752-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:753:#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:754:#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:755:#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-756-#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-773-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:774:#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:775:#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:776:#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-777-#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-791-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:792:#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:793:#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:794:#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-795-#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-812-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:813:#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:814:#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:815:#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-816-#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-830-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:831:#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:832:#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:833:#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-834-#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-851-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:852:#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:853:#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:854:#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-855-#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-869-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:870:#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:871:#define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:872:#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-873-#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-890-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:891:#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:892:#define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:893:#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-894-#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-908-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:909:#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:910:#define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:911:#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-912-#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-929-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:930:#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:931:#define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:932:#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-933-#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-947-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:948:#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:949:#define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:950:#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-951-#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-968-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:969:#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:970:#define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:971:#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-972-#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-986-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:987:#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:988:#define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:989:#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-990-#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1007-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1008:#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1009:#define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1010:#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1011-#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1025-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1026:#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1027:#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1028:#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1029-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1046-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1047:#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1048:#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1049:#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1050-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1064-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1065:#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1066:#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1067:#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1068-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1085-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1086:#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1087:#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1088:#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1089-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1103-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1104:#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1105:#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1106:#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1107-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1124-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1125:#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1126:#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1127:#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1128-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1142-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1143:#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1144:#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1145:#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1146-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1163-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1164:#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1165:#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1166:#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1167-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1181-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1182:#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1183:#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1184:#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1185-#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1202-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1203:#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1204:#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1205:#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1206-#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1220-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1221:#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1222:#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1223:#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1224-#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1241-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1242:#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1243:#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1244:#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1245-#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1259-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1260:#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1261:#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1262:#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1263-#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1280-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1281:#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1282:#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1283:#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1284-#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1298-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1299:#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1300:#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1301:#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1302-#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1319-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1320:#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1321:#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:1322:#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-1323-#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2216-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2217:#define pMXVR_LADDR ((uint32_t volatile *)MXVR_LADDR) /* MXVR Logical Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2218:#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2219:#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2220:#define pMXVR_GADDR ((uint16_t volatile *)MXVR_GADDR) /* MXVR Group Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2221:#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2222:#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2223:#define pMXVR_AADDR ((uint32_t volatile *)MXVR_AADDR) /* MXVR Alternate Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2224:#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2225:#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2226-#define pMXVR_ALLOC_0 ((uint32_t volatile *)MXVR_ALLOC_0) /* MXVR Allocation Table Register 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2297-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2298:#define pMXVR_DMA0_START_ADDR ((void * volatile *)MXVR_DMA0_START_ADDR) /* MXVR Sync Data DMA0 Start Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2299:#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2300:#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2301-#define pMXVR_DMA0_COUNT ((uint16_t volatile *)MXVR_DMA0_COUNT) /* MXVR Sync Data DMA0 Loop Count Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2303-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2304:#define pMXVR_DMA0_CURR_ADDR ((void * volatile *)MXVR_DMA0_CURR_ADDR) /* MXVR Sync Data DMA0 Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2305:#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2306:#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2307-#define pMXVR_DMA0_CURR_COUNT ((uint16_t volatile *)MXVR_DMA0_CURR_COUNT) /* MXVR Sync Data DMA0 Current Loop Count */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2312-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2313:#define pMXVR_DMA1_START_ADDR ((void * volatile *)MXVR_DMA1_START_ADDR) /* MXVR Sync Data DMA1 Start Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2314:#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2315:#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2316-#define pMXVR_DMA1_COUNT ((uint16_t volatile *)MXVR_DMA1_COUNT) /* MXVR Sync Data DMA1 Loop Count Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2318-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2319:#define pMXVR_DMA1_CURR_ADDR ((void * volatile *)MXVR_DMA1_CURR_ADDR) /* MXVR Sync Data DMA1 Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2320:#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2321:#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2322-#define pMXVR_DMA1_CURR_COUNT ((uint16_t volatile *)MXVR_DMA1_CURR_COUNT) /* MXVR Sync Data DMA1 Current Loop Count */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2327-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2328:#define pMXVR_DMA2_START_ADDR ((void * volatile *)MXVR_DMA2_START_ADDR) /* MXVR Sync Data DMA2 Start Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2329:#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2330:#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2331-#define pMXVR_DMA2_COUNT ((uint16_t volatile *)MXVR_DMA2_COUNT) /* MXVR Sync Data DMA2 Loop Count Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2333-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2334:#define pMXVR_DMA2_CURR_ADDR ((void * volatile *)MXVR_DMA2_CURR_ADDR) /* MXVR Sync Data DMA2 Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2335:#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2336:#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2337-#define pMXVR_DMA2_CURR_COUNT ((uint16_t volatile *)MXVR_DMA2_CURR_COUNT) /* MXVR Sync Data DMA2 Current Loop Count */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2342-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2343:#define pMXVR_DMA3_START_ADDR ((void * volatile *)MXVR_DMA3_START_ADDR) /* MXVR Sync Data DMA3 Start Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2344:#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2345:#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2346-#define pMXVR_DMA3_COUNT ((uint16_t volatile *)MXVR_DMA3_COUNT) /* MXVR Sync Data DMA3 Loop Count Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2348-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2349:#define pMXVR_DMA3_CURR_ADDR ((void * volatile *)MXVR_DMA3_CURR_ADDR) /* MXVR Sync Data DMA3 Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2350:#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2351:#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2352-#define pMXVR_DMA3_CURR_COUNT ((uint16_t volatile *)MXVR_DMA3_CURR_COUNT) /* MXVR Sync Data DMA3 Current Loop Count */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2357-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2358:#define pMXVR_DMA4_START_ADDR ((void * volatile *)MXVR_DMA4_START_ADDR) /* MXVR Sync Data DMA4 Start Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2359:#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2360:#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2361-#define pMXVR_DMA4_COUNT ((uint16_t volatile *)MXVR_DMA4_COUNT) /* MXVR Sync Data DMA4 Loop Count Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2363-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2364:#define pMXVR_DMA4_CURR_ADDR ((void * volatile *)MXVR_DMA4_CURR_ADDR) /* MXVR Sync Data DMA4 Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2365:#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2366:#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2367-#define pMXVR_DMA4_CURR_COUNT ((uint16_t volatile *)MXVR_DMA4_CURR_COUNT) /* MXVR Sync Data DMA4 Current Loop Count */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2372-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2373:#define pMXVR_DMA5_START_ADDR ((void * volatile *)MXVR_DMA5_START_ADDR) /* MXVR Sync Data DMA5 Start Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2374:#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2375:#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2376-#define pMXVR_DMA5_COUNT ((uint16_t volatile *)MXVR_DMA5_COUNT) /* MXVR Sync Data DMA5 Loop Count Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2378-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2379:#define pMXVR_DMA5_CURR_ADDR ((void * volatile *)MXVR_DMA5_CURR_ADDR) /* MXVR Sync Data DMA5 Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2380:#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2381:#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2382-#define pMXVR_DMA5_CURR_COUNT ((uint16_t volatile *)MXVR_DMA5_CURR_COUNT) /* MXVR Sync Data DMA5 Current Loop Count */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2387-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2388:#define pMXVR_DMA6_START_ADDR ((void * volatile *)MXVR_DMA6_START_ADDR) /* MXVR Sync Data DMA6 Start Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2389:#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2390:#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2391-#define pMXVR_DMA6_COUNT ((uint16_t volatile *)MXVR_DMA6_COUNT) /* MXVR Sync Data DMA6 Loop Count Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2393-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2394:#define pMXVR_DMA6_CURR_ADDR ((void * volatile *)MXVR_DMA6_CURR_ADDR) /* MXVR Sync Data DMA6 Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2395:#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2396:#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2397-#define pMXVR_DMA6_CURR_COUNT ((uint16_t volatile *)MXVR_DMA6_CURR_COUNT) /* MXVR Sync Data DMA6 Current Loop Count */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2402-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2403:#define pMXVR_DMA7_START_ADDR ((void * volatile *)MXVR_DMA7_START_ADDR) /* MXVR Sync Data DMA7 Start Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2404:#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2405:#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2406-#define pMXVR_DMA7_COUNT ((uint16_t volatile *)MXVR_DMA7_COUNT) /* MXVR Sync Data DMA7 Loop Count Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2408-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2409:#define pMXVR_DMA7_CURR_ADDR ((void * volatile *)MXVR_DMA7_CURR_ADDR) /* MXVR Sync Data DMA7 Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2410:#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2411:#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2412-#define pMXVR_DMA7_CURR_COUNT ((uint16_t volatile *)MXVR_DMA7_CURR_COUNT) /* MXVR Sync Data DMA7 Current Loop Count */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2417-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2418:#define pMXVR_APRB_START_ADDR ((void * volatile *)MXVR_APRB_START_ADDR) /* MXVR Async Packet RX Buffer Start Addr Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2419:#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2420:#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2421:#define pMXVR_APRB_CURR_ADDR ((void * volatile *)MXVR_APRB_CURR_ADDR) /* MXVR Async Packet RX Buffer Current Addr Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2422:#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2423:#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2424:#define pMXVR_APTB_START_ADDR ((void * volatile *)MXVR_APTB_START_ADDR) /* MXVR Async Packet TX Buffer Start Addr Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2425:#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2426:#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2427:#define pMXVR_APTB_CURR_ADDR ((void * volatile *)MXVR_APTB_CURR_ADDR) /* MXVR Async Packet TX Buffer Current Addr Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2428:#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2429:#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2430-#define pMXVR_CM_CTL ((uint32_t volatile *)MXVR_CM_CTL) /* MXVR Control Message Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2432-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2433:#define pMXVR_CMRB_START_ADDR ((void * volatile *)MXVR_CMRB_START_ADDR) /* MXVR Control Message RX Buffer Start Addr Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2434:#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2435:#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2436:#define pMXVR_CMRB_CURR_ADDR ((void * volatile *)MXVR_CMRB_CURR_ADDR) /* MXVR Control Message RX Buffer Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2437:#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2438:#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2439:#define pMXVR_CMTB_START_ADDR ((void * volatile *)MXVR_CMTB_START_ADDR) /* MXVR Control Message TX Buffer Start Addr Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2440:#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2441:#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2442:#define pMXVR_CMTB_CURR_ADDR ((void * volatile *)MXVR_CMTB_CURR_ADDR) /* MXVR Control Message TX Buffer Current Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2443:#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2444:#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2445:#define pMXVR_RRDB_START_ADDR ((void * volatile *)MXVR_RRDB_START_ADDR) /* MXVR Remote Read Buffer Start Addr Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2446:#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2447:#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2448:#define pMXVR_RRDB_CURR_ADDR ((void * volatile *)MXVR_RRDB_CURR_ADDR) /* MXVR Remote Read Buffer Current Addr Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2449:#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2450:#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2451-#define pMXVR_PAT_DATA_0 ((uint32_t volatile *)MXVR_PAT_DATA_0) /* MXVR Pattern Data Register 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2648-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2649:#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2650:#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2651:#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2652-#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2753-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2754:#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2755:#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:2756:#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-2757-#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5138-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5139:#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5140:#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5141:#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5142-#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5147-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5148:#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5149:#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5150:#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5151-#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5186-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5187:#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5188:#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5189:#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5190-#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5195-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5196:#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5197:#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5198:#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5199-#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5626-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5627:#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5628:#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h:5629:#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h-5630-#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h-21-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h:22:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h:23:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h:24:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h-25-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h-30-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h:31:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h:32:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h:33:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h-34-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h-144-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h:145:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h:146:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h:147:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h-148-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h-21-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h:22:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h:23:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h:24:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h-25-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h-30-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h:31:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h:32:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h:33:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h-34-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h-144-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h:145:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h:146:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h:147:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h-148-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h-21-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h:22:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h:23:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h:24:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h-25-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h-30-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h:31:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h:32:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h:33:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h-34-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h-144-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h:145:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h:146:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h:147:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h-148-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h-21-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h:22:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h:23:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h:24:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h-25-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h-30-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h:31:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h:32:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h:33:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h-34-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h-144-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h:145:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h:146:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h:147:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h-148-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h-21-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h:22:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h:23:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h:24:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h-25-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h-30-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h:31:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h:32:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h:33:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h-34-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h-144-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h:145:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h:146:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h:147:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h-148-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h-21-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h:22:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h:23:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h:24:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h-25-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h-30-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h:31:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h:32:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h:33:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h-34-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h-144-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h:145:#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h:146:#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h:147:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h-148-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h-12-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h:13:#define pSRAM_BASE_ADDR ((uint32_t volatile *)SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h:14:#define bfin_read_SRAM_BASE_ADDR() bfin_read32(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h:15:#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h-16-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h-21-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h:22:#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h:23:#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h:24:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h-25-#define pDCPLB_ADDR0 ((uint32_t volatile *)DCPLB_ADDR0)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h-135-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h:136:#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h:137:#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h:138:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h-139-#define pICPLB_ADDR0 ((uint32_t volatile *)ICPLB_ADDR0)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-77-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:78:#define pDMA1_0_START_ADDR ((void * volatile *)DMA1_0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:79:#define bfin_read_DMA1_0_START_ADDR() bfin_readPTR(DMA1_0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:80:#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-81-#define pDMA1_0_X_COUNT ((uint16_t volatile *)DMA1_0_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-95-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:96:#define pDMA1_0_CURR_ADDR ((void * volatile *)DMA1_0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:97:#define bfin_read_DMA1_0_CURR_ADDR() bfin_readPTR(DMA1_0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:98:#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-99-#define pDMA1_0_CURR_X_COUNT ((uint16_t volatile *)DMA1_0_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-116-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:117:#define pDMA1_1_START_ADDR ((void * volatile *)DMA1_1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:118:#define bfin_read_DMA1_1_START_ADDR() bfin_readPTR(DMA1_1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:119:#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-120-#define pDMA1_1_X_COUNT ((uint16_t volatile *)DMA1_1_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-134-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:135:#define pDMA1_1_CURR_ADDR ((void * volatile *)DMA1_1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:136:#define bfin_read_DMA1_1_CURR_ADDR() bfin_readPTR(DMA1_1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:137:#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-138-#define pDMA1_1_CURR_X_COUNT ((uint16_t volatile *)DMA1_1_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-155-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:156:#define pDMA1_2_START_ADDR ((void * volatile *)DMA1_2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:157:#define bfin_read_DMA1_2_START_ADDR() bfin_readPTR(DMA1_2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:158:#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-159-#define pDMA1_2_X_COUNT ((uint16_t volatile *)DMA1_2_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-173-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:174:#define pDMA1_2_CURR_ADDR ((void * volatile *)DMA1_2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:175:#define bfin_read_DMA1_2_CURR_ADDR() bfin_readPTR(DMA1_2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:176:#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-177-#define pDMA1_2_CURR_X_COUNT ((uint16_t volatile *)DMA1_2_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-194-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:195:#define pDMA1_3_START_ADDR ((void * volatile *)DMA1_3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:196:#define bfin_read_DMA1_3_START_ADDR() bfin_readPTR(DMA1_3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:197:#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-198-#define pDMA1_3_X_COUNT ((uint16_t volatile *)DMA1_3_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-212-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:213:#define pDMA1_3_CURR_ADDR ((void * volatile *)DMA1_3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:214:#define bfin_read_DMA1_3_CURR_ADDR() bfin_readPTR(DMA1_3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:215:#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-216-#define pDMA1_3_CURR_X_COUNT ((uint16_t volatile *)DMA1_3_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-233-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:234:#define pDMA1_4_START_ADDR ((void * volatile *)DMA1_4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:235:#define bfin_read_DMA1_4_START_ADDR() bfin_readPTR(DMA1_4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:236:#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-237-#define pDMA1_4_X_COUNT ((uint16_t volatile *)DMA1_4_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-251-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:252:#define pDMA1_4_CURR_ADDR ((void * volatile *)DMA1_4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:253:#define bfin_read_DMA1_4_CURR_ADDR() bfin_readPTR(DMA1_4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:254:#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-255-#define pDMA1_4_CURR_X_COUNT ((uint16_t volatile *)DMA1_4_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-272-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:273:#define pDMA1_5_START_ADDR ((void * volatile *)DMA1_5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:274:#define bfin_read_DMA1_5_START_ADDR() bfin_readPTR(DMA1_5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:275:#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-276-#define pDMA1_5_X_COUNT ((uint16_t volatile *)DMA1_5_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-290-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:291:#define pDMA1_5_CURR_ADDR ((void * volatile *)DMA1_5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:292:#define bfin_read_DMA1_5_CURR_ADDR() bfin_readPTR(DMA1_5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:293:#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-294-#define pDMA1_5_CURR_X_COUNT ((uint16_t volatile *)DMA1_5_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-311-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:312:#define pDMA1_6_START_ADDR ((void * volatile *)DMA1_6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:313:#define bfin_read_DMA1_6_START_ADDR() bfin_readPTR(DMA1_6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:314:#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-315-#define pDMA1_6_X_COUNT ((uint16_t volatile *)DMA1_6_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-329-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:330:#define pDMA1_6_CURR_ADDR ((void * volatile *)DMA1_6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:331:#define bfin_read_DMA1_6_CURR_ADDR() bfin_readPTR(DMA1_6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:332:#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-333-#define pDMA1_6_CURR_X_COUNT ((uint16_t volatile *)DMA1_6_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-350-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:351:#define pDMA1_7_START_ADDR ((void * volatile *)DMA1_7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:352:#define bfin_read_DMA1_7_START_ADDR() bfin_readPTR(DMA1_7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:353:#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-354-#define pDMA1_7_X_COUNT ((uint16_t volatile *)DMA1_7_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-368-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:369:#define pDMA1_7_CURR_ADDR ((void * volatile *)DMA1_7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:370:#define bfin_read_DMA1_7_CURR_ADDR() bfin_readPTR(DMA1_7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:371:#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-372-#define pDMA1_7_CURR_X_COUNT ((uint16_t volatile *)DMA1_7_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-389-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:390:#define pDMA1_8_START_ADDR ((void * volatile *)DMA1_8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:391:#define bfin_read_DMA1_8_START_ADDR() bfin_readPTR(DMA1_8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:392:#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-393-#define pDMA1_8_X_COUNT ((uint16_t volatile *)DMA1_8_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-407-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:408:#define pDMA1_8_CURR_ADDR ((void * volatile *)DMA1_8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:409:#define bfin_read_DMA1_8_CURR_ADDR() bfin_readPTR(DMA1_8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:410:#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-411-#define pDMA1_8_CURR_X_COUNT ((uint16_t volatile *)DMA1_8_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-428-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:429:#define pDMA1_9_START_ADDR ((void * volatile *)DMA1_9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:430:#define bfin_read_DMA1_9_START_ADDR() bfin_readPTR(DMA1_9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:431:#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-432-#define pDMA1_9_X_COUNT ((uint16_t volatile *)DMA1_9_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-446-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:447:#define pDMA1_9_CURR_ADDR ((void * volatile *)DMA1_9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:448:#define bfin_read_DMA1_9_CURR_ADDR() bfin_readPTR(DMA1_9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:449:#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-450-#define pDMA1_9_CURR_X_COUNT ((uint16_t volatile *)DMA1_9_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-467-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:468:#define pDMA1_10_START_ADDR ((void * volatile *)DMA1_10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:469:#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:470:#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-471-#define pDMA1_10_X_COUNT ((uint16_t volatile *)DMA1_10_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-485-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:486:#define pDMA1_10_CURR_ADDR ((void * volatile *)DMA1_10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:487:#define bfin_read_DMA1_10_CURR_ADDR() bfin_readPTR(DMA1_10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:488:#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-489-#define pDMA1_10_CURR_X_COUNT ((uint16_t volatile *)DMA1_10_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-506-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:507:#define pDMA1_11_START_ADDR ((void * volatile *)DMA1_11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:508:#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:509:#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-510-#define pDMA1_11_X_COUNT ((uint16_t volatile *)DMA1_11_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-524-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:525:#define pDMA1_11_CURR_ADDR ((void * volatile *)DMA1_11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:526:#define bfin_read_DMA1_11_CURR_ADDR() bfin_readPTR(DMA1_11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:527:#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-528-#define pDMA1_11_CURR_X_COUNT ((uint16_t volatile *)DMA1_11_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-551-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:552:#define pDMA2_0_START_ADDR ((void * volatile *)DMA2_0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:553:#define bfin_read_DMA2_0_START_ADDR() bfin_readPTR(DMA2_0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:554:#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-555-#define pDMA2_0_X_COUNT ((uint16_t volatile *)DMA2_0_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-569-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:570:#define pDMA2_0_CURR_ADDR ((void * volatile *)DMA2_0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:571:#define bfin_read_DMA2_0_CURR_ADDR() bfin_readPTR(DMA2_0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:572:#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-573-#define pDMA2_0_CURR_X_COUNT ((uint16_t volatile *)DMA2_0_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-590-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:591:#define pDMA2_1_START_ADDR ((void * volatile *)DMA2_1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:592:#define bfin_read_DMA2_1_START_ADDR() bfin_readPTR(DMA2_1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:593:#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-594-#define pDMA2_1_X_COUNT ((uint16_t volatile *)DMA2_1_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-608-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:609:#define pDMA2_1_CURR_ADDR ((void * volatile *)DMA2_1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:610:#define bfin_read_DMA2_1_CURR_ADDR() bfin_readPTR(DMA2_1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:611:#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-612-#define pDMA2_1_CURR_X_COUNT ((uint16_t volatile *)DMA2_1_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-629-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:630:#define pDMA2_2_START_ADDR ((void * volatile *)DMA2_2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:631:#define bfin_read_DMA2_2_START_ADDR() bfin_readPTR(DMA2_2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:632:#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-633-#define pDMA2_2_X_COUNT ((uint16_t volatile *)DMA2_2_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-647-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:648:#define pDMA2_2_CURR_ADDR ((void * volatile *)DMA2_2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:649:#define bfin_read_DMA2_2_CURR_ADDR() bfin_readPTR(DMA2_2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:650:#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-651-#define pDMA2_2_CURR_X_COUNT ((uint16_t volatile *)DMA2_2_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-668-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:669:#define pDMA2_3_START_ADDR ((void * volatile *)DMA2_3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:670:#define bfin_read_DMA2_3_START_ADDR() bfin_readPTR(DMA2_3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:671:#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-672-#define pDMA2_3_X_COUNT ((uint16_t volatile *)DMA2_3_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-686-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:687:#define pDMA2_3_CURR_ADDR ((void * volatile *)DMA2_3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:688:#define bfin_read_DMA2_3_CURR_ADDR() bfin_readPTR(DMA2_3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:689:#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-690-#define pDMA2_3_CURR_X_COUNT ((uint16_t volatile *)DMA2_3_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-707-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:708:#define pDMA2_4_START_ADDR ((void * volatile *)DMA2_4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:709:#define bfin_read_DMA2_4_START_ADDR() bfin_readPTR(DMA2_4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:710:#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-711-#define pDMA2_4_X_COUNT ((uint16_t volatile *)DMA2_4_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-725-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:726:#define pDMA2_4_CURR_ADDR ((void * volatile *)DMA2_4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:727:#define bfin_read_DMA2_4_CURR_ADDR() bfin_readPTR(DMA2_4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:728:#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-729-#define pDMA2_4_CURR_X_COUNT ((uint16_t volatile *)DMA2_4_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-746-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:747:#define pDMA2_5_START_ADDR ((void * volatile *)DMA2_5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:748:#define bfin_read_DMA2_5_START_ADDR() bfin_readPTR(DMA2_5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:749:#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-750-#define pDMA2_5_X_COUNT ((uint16_t volatile *)DMA2_5_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-764-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:765:#define pDMA2_5_CURR_ADDR ((void * volatile *)DMA2_5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:766:#define bfin_read_DMA2_5_CURR_ADDR() bfin_readPTR(DMA2_5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:767:#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-768-#define pDMA2_5_CURR_X_COUNT ((uint16_t volatile *)DMA2_5_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-785-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:786:#define pDMA2_6_START_ADDR ((void * volatile *)DMA2_6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:787:#define bfin_read_DMA2_6_START_ADDR() bfin_readPTR(DMA2_6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:788:#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-789-#define pDMA2_6_X_COUNT ((uint16_t volatile *)DMA2_6_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-803-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:804:#define pDMA2_6_CURR_ADDR ((void * volatile *)DMA2_6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:805:#define bfin_read_DMA2_6_CURR_ADDR() bfin_readPTR(DMA2_6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:806:#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-807-#define pDMA2_6_CURR_X_COUNT ((uint16_t volatile *)DMA2_6_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-824-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:825:#define pDMA2_7_START_ADDR ((void * volatile *)DMA2_7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:826:#define bfin_read_DMA2_7_START_ADDR() bfin_readPTR(DMA2_7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:827:#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-828-#define pDMA2_7_X_COUNT ((uint16_t volatile *)DMA2_7_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-842-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:843:#define pDMA2_7_CURR_ADDR ((void * volatile *)DMA2_7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:844:#define bfin_read_DMA2_7_CURR_ADDR() bfin_readPTR(DMA2_7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:845:#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-846-#define pDMA2_7_CURR_X_COUNT ((uint16_t volatile *)DMA2_7_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-863-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:864:#define pDMA2_8_START_ADDR ((void * volatile *)DMA2_8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:865:#define bfin_read_DMA2_8_START_ADDR() bfin_readPTR(DMA2_8_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:866:#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-867-#define pDMA2_8_X_COUNT ((uint16_t volatile *)DMA2_8_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-881-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:882:#define pDMA2_8_CURR_ADDR ((void * volatile *)DMA2_8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:883:#define bfin_read_DMA2_8_CURR_ADDR() bfin_readPTR(DMA2_8_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:884:#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-885-#define pDMA2_8_CURR_X_COUNT ((uint16_t volatile *)DMA2_8_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-902-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:903:#define pDMA2_9_START_ADDR ((void * volatile *)DMA2_9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:904:#define bfin_read_DMA2_9_START_ADDR() bfin_readPTR(DMA2_9_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:905:#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-906-#define pDMA2_9_X_COUNT ((uint16_t volatile *)DMA2_9_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-920-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:921:#define pDMA2_9_CURR_ADDR ((void * volatile *)DMA2_9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:922:#define bfin_read_DMA2_9_CURR_ADDR() bfin_readPTR(DMA2_9_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:923:#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-924-#define pDMA2_9_CURR_X_COUNT ((uint16_t volatile *)DMA2_9_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-941-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:942:#define pDMA2_10_START_ADDR ((void * volatile *)DMA2_10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:943:#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:944:#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-945-#define pDMA2_10_X_COUNT ((uint16_t volatile *)DMA2_10_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-959-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:960:#define pDMA2_10_CURR_ADDR ((void * volatile *)DMA2_10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:961:#define bfin_read_DMA2_10_CURR_ADDR() bfin_readPTR(DMA2_10_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:962:#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-963-#define pDMA2_10_CURR_X_COUNT ((uint16_t volatile *)DMA2_10_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-980-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:981:#define pDMA2_11_START_ADDR ((void * volatile *)DMA2_11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:982:#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:983:#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-984-#define pDMA2_11_X_COUNT ((uint16_t volatile *)DMA2_11_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-998-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:999:#define pDMA2_11_CURR_ADDR ((void * volatile *)DMA2_11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1000:#define bfin_read_DMA2_11_CURR_ADDR() bfin_readPTR(DMA2_11_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1001:#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1002-#define pDMA2_11_CURR_X_COUNT ((uint16_t volatile *)DMA2_11_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1019-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1020:#define pIMDMA_S0_START_ADDR ((void * volatile *)IMDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1021:#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1022:#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1023-#define pIMDMA_S0_X_COUNT ((uint16_t volatile *)IMDMA_S0_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1037-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1038:#define pIMDMA_S0_CURR_ADDR ((void * volatile *)IMDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1039:#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1040:#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1041-#define pIMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1055-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1056:#define pIMDMA_D0_START_ADDR ((void * volatile *)IMDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1057:#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1058:#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1059-#define pIMDMA_D0_X_COUNT ((uint16_t volatile *)IMDMA_D0_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1073-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1074:#define pIMDMA_D0_CURR_ADDR ((void * volatile *)IMDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1075:#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1076:#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1077-#define pIMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1091-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1092:#define pIMDMA_S1_START_ADDR ((void * volatile *)IMDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1093:#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1094:#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1095-#define pIMDMA_S1_X_COUNT ((uint16_t volatile *)IMDMA_S1_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1109-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1110:#define pIMDMA_S1_CURR_ADDR ((void * volatile *)IMDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1111:#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1112:#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1113-#define pIMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1127-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1128:#define pIMDMA_D1_START_ADDR ((void * volatile *)IMDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1129:#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1130:#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1131-#define pIMDMA_D1_X_COUNT ((uint16_t volatile *)IMDMA_D1_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1145-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1146:#define pIMDMA_D1_CURR_ADDR ((void * volatile *)IMDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1147:#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1148:#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1149-#define pIMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1163-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1164:#define pMDMA1_S0_START_ADDR ((void * volatile *)MDMA1_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1165:#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1166:#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1167-#define pMDMA1_S0_X_COUNT ((uint16_t volatile *)MDMA1_S0_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1181-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1182:#define pMDMA1_S0_CURR_ADDR ((void * volatile *)MDMA1_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1183:#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1184:#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1185-#define pMDMA1_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1202-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1203:#define pMDMA1_D0_START_ADDR ((void * volatile *)MDMA1_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1204:#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1205:#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1206-#define pMDMA1_D0_X_COUNT ((uint16_t volatile *)MDMA1_D0_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1220-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1221:#define pMDMA1_D0_CURR_ADDR ((void * volatile *)MDMA1_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1222:#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1223:#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1224-#define pMDMA1_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1241-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1242:#define pMDMA1_S1_START_ADDR ((void * volatile *)MDMA1_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1243:#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1244:#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1245-#define pMDMA1_S1_X_COUNT ((uint16_t volatile *)MDMA1_S1_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1259-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1260:#define pMDMA1_S1_CURR_ADDR ((void * volatile *)MDMA1_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1261:#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1262:#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1263-#define pMDMA1_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1280-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1281:#define pMDMA1_D1_START_ADDR ((void * volatile *)MDMA1_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1282:#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1283:#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1284-#define pMDMA1_D1_X_COUNT ((uint16_t volatile *)MDMA1_D1_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1298-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1299:#define pMDMA1_D1_CURR_ADDR ((void * volatile *)MDMA1_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1300:#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1301:#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1302-#define pMDMA1_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1319-#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1320:#define pMDMA2_S0_START_ADDR ((void * volatile *)MDMA2_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1321:#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1322:#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1323-#define pMDMA2_S0_X_COUNT ((uint16_t volatile *)MDMA2_S0_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1337-#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1338:#define pMDMA2_S0_CURR_ADDR ((void * volatile *)MDMA2_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1339:#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1340:#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1341-#define pMDMA2_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1358-#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1359:#define pMDMA2_D0_START_ADDR ((void * volatile *)MDMA2_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1360:#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1361:#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1362-#define pMDMA2_D0_X_COUNT ((uint16_t volatile *)MDMA2_D0_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1376-#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1377:#define pMDMA2_D0_CURR_ADDR ((void * volatile *)MDMA2_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1378:#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1379:#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1380-#define pMDMA2_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1397-#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1398:#define pMDMA2_S1_START_ADDR ((void * volatile *)MDMA2_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1399:#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1400:#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1401-#define pMDMA2_S1_X_COUNT ((uint16_t volatile *)MDMA2_S1_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1415-#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1416:#define pMDMA2_S1_CURR_ADDR ((void * volatile *)MDMA2_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1417:#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1418:#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1419-#define pMDMA2_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1436-#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1437:#define pMDMA2_D1_START_ADDR ((void * volatile *)MDMA2_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1438:#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1439:#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1440-#define pMDMA2_D1_X_COUNT ((uint16_t volatile *)MDMA2_D1_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1454-#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1455:#define pMDMA2_D1_CURR_ADDR ((void * volatile *)MDMA2_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1456:#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h:1457:#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h-1458-#define pMDMA2_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-32-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:33:#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:34:#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:35:#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-36-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-41-#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:42:#define pDCPLB_FAULT_ADDR ((uint32_t volatile *)DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:43:#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:44:#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-45-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-203-#define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:204:#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:205:#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:206:#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-207-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1113-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1114:#define pDMA0_START_ADDR ((uint32_t volatile *)DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1115:#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1116:#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1117-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1134-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1135:#define pDMA0_CURR_ADDR ((uint32_t volatile *)DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1136:#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1137:#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1138-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1152-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1153:#define pDMA1_START_ADDR ((uint32_t volatile *)DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1154:#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1155:#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1156-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1173-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1174:#define pDMA1_CURR_ADDR ((uint32_t volatile *)DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1175:#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1176:#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1177-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1191-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1192:#define pDMA2_START_ADDR ((uint32_t volatile *)DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1193:#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1194:#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1195-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1212-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1213:#define pDMA2_CURR_ADDR ((uint32_t volatile *)DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1214:#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1215:#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1216-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1230-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1231:#define pDMA3_START_ADDR ((uint32_t volatile *)DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1232:#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1233:#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1234-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1251-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1252:#define pDMA3_CURR_ADDR ((uint32_t volatile *)DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1253:#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1254:#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1255-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1269-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1270:#define pDMA4_START_ADDR ((uint32_t volatile *)DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1271:#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1272:#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1273-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1290-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1291:#define pDMA4_CURR_ADDR ((uint32_t volatile *)DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1292:#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1293:#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1294-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1308-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1309:#define pDMA5_START_ADDR ((uint32_t volatile *)DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1310:#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1311:#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1312-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1329-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1330:#define pDMA5_CURR_ADDR ((uint32_t volatile *)DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1331:#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1332:#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1333-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1347-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1348:#define pDMA6_START_ADDR ((uint32_t volatile *)DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1349:#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1350:#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1351-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1368-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1369:#define pDMA6_CURR_ADDR ((uint32_t volatile *)DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1370:#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1371:#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1372-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1386-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1387:#define pDMA7_START_ADDR ((uint32_t volatile *)DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1388:#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1389:#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1390-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1407-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1408:#define pDMA7_CURR_ADDR ((uint32_t volatile *)DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1409:#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1410:#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1411-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1425-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1426:#define pMDMA_D0_START_ADDR ((uint32_t volatile *)MDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1427:#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1428:#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1429-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1446-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1447:#define pMDMA_D0_CURR_ADDR ((uint32_t volatile *)MDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1448:#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1449:#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1450-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1464-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1465:#define pMDMA_S0_START_ADDR ((uint32_t volatile *)MDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1466:#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1467:#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1468-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1485-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1486:#define pMDMA_S0_CURR_ADDR ((uint32_t volatile *)MDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1487:#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1488:#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1489-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1503-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1504:#define pMDMA_D1_START_ADDR ((uint32_t volatile *)MDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1505:#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1506:#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1507-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1524-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1525:#define pMDMA_D1_CURR_ADDR ((uint32_t volatile *)MDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1526:#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1527:#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1528-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1542-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1543:#define pMDMA_S1_START_ADDR ((uint32_t volatile *)MDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1544:#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1545:#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1546-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1563-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1564:#define pMDMA_S1_CURR_ADDR ((uint32_t volatile *)MDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1565:#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h:1566:#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h-1567-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/system.h-73- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/system.h:74:#define nop() asm volatile ("nop;\n\t"::)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/system.h:75:#define mb() asm volatile ("" : : :"memory")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/system.h:76:#define rmb() asm volatile ("" : : :"memory")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/system.h:77:#define wmb() asm volatile ("" : : :"memory")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/include/asm/system.h-78-#define set_rmb(var, value) do { xchg(&var, value); } while (0)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/board.c-306-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/board.c:307: bd->bi_ip_addr = getenv_IPaddr("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/board.c-308-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/boot.c-53- dcache_disable();
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/boot.c:54: asm __volatile__(
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/boot.c-55- "RETX = %[retx];"
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/kgdb.c-421-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/kgdb.c:422: asm volatile ("excpt 0x1\n");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/kgdb.c-423-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/kgdb.h-97-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/kgdb.h:98: asm volatile ("EXCPT 2;");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/kgdb.h-99-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/string.c-170- /* Setup destination start address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/string.c:171: bfin_write_MDMA_D0_START_ADDR(dst);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/string.c-172- /* Setup destination xcount */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/string.c-177- /* Setup Source start address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/string.c:178: bfin_write_MDMA_S0_START_ADDR(src);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/string.c-179- /* Setup Source xcount */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S-84- } >ram_code
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S:85: __initcode_lma = LOADADDR(.text.init);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S-86- __initcode_len = SIZEOF(.text.init);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S-125- } >l1_code AT>ram_code
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S:126: __text_l1_lma = LOADADDR(.text_l1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S-127- __text_l1_len = SIZEOF(.text_l1);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S-138- } >l1_data AT>ram_data
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S:139: __data_l1_lma = LOADADDR(.data_l1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S-140- __data_l1_len = SIZEOF(.data_l1);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S-150- } >ram_data
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S:151: __bss_vma = ADDR(.bss);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/blackfin/lib/u-boot.lds.S-152- __bss_len = SIZEOF(.bss);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/cpu.c-42- /* initialize FPU, reset EM, set MP and NE */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/cpu.c:43: asm ("fninit\n" \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/cpu.c-44- "movl %cr0, %eax\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-52- unsigned long val;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c:53: asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-54- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-59- unsigned long val;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c:60: asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-61- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-66- unsigned long val;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c:67: asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-68- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-73- unsigned long val;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c:74: asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-75- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-163-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c:164: asm volatile("cs lidt %0"::"m" (*dtr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-165-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-221-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c:222: asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/interrupts.c-223-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/sc520/sc520_asm.S-64- *
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/sc520/sc520_asm.S:65: * FILE : sizer.asm - SDRAM DIMM Sizing Algorithm
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/sc520/sc520_asm.S-66- *
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/sc520/sc520_asm.S-102- * $Author: chipf $
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/sc520/sc520_asm.S:103: * $Log: sizer.asm $
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/cpu/sc520/sc520_asm.S-104- * Revision 1.2 1999/09/22 12:49:33 chipf
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/include/asm/bitops.h-22-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/include/asm/bitops.h:23:#define ADDR (*(volatile long *) addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/include/asm/bitops.h-24-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/include/asm/string.h-5- * We don't do inline string functions, since the
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/include/asm/string.h:6: * optimised inline asm versions are not small.
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/include/asm/string.h-7- */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/lib/board.c-296- /* IP Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/lib/board.c:297: bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/i386/lib/board.c-298-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/config.mk-25-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/config.mk:26:clibdir = $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/config.mk-27-STANDALONE_LOAD_ADDR = 0x20000 -L $(clibdir)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/byteorder.h-65-/* alas, egcs sounds like it has a bug in this code that doesn't use the
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/byteorder.h:66: inline asm correctly, and can cause file corruption. Until I hear that
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/byteorder.h-67- it's fixed, I can live without the extra speed. I hope. */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/coldfire/qspi.h-94-/* AR */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/coldfire/qspi.h:95:#define QSPI_QAR_ADDR(x) ((x)&0x003F)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/coldfire/qspi.h-96-#define QSPI_QAR_ADDR_MASK (0xFFC0)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/global_data.h-83-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/global_data.h:84:#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("d7")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/global_data.h-85-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h-288-/* Bit definitions and macros for GPIO_PODR */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h:289:#define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h-290-#define GPIO_PODR_ADDR_MASK (0xE0)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h-306-/* Bit definitions and macros for GPIO_PDDR */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h:307:#define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h-308-#define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h-324-/* Bit definitions and macros for GPIO_PPDSDR */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h:325:#define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h-326-#define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h-342-/* Bit definitions and macros for GPIO_PCLRR */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h:343:#define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5235.h-344-#define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5253.h-46-#define CIM_MISCCR (0x000500)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5253.h:47:#define CIM_ATA_DADDR (0x000504)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5253.h-48-#define CIM_ATA_DCOUNT (0x000508)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5253.h-66-/* Bit definitions and macros for ATA_DADDR */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5253.h:67:#define CIM_ATA_DADDR_ATAADDR(x) (((x)&0x00003FFF)<<2)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5253.h:68:#define CIM_ATA_DADDR_RAMADDR(x) (((x)&0x00003FFF)<<18)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/m5253.h-69-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/processor.h-11-/* Macros for setting and retrieving special purpose registers */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/processor.h:12:#define setvbr(v) asm volatile("movec %0,%%VBR" : : "r" (v))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/processor.h-13-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/uart.h-82-#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/uart.h:83:#define UART_UMR_PM_MULTI_ADDR (0x1C)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/include/asm/uart.h-84-#define UART_UMR_PM_MULTI_DATA (0x18)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/board.c-554- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/board.c:555: bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/board.c-556-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/bootm.c-37-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/bootm.c:38:#define PHYSADDR(x) x
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/bootm.c-39-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/interrupts.c-47-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/interrupts.c:48: asm volatile ("move.w %%sr,%0":"=r" (sr):);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/interrupts.c-49-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/interrupts.c-54-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/interrupts.c:55: asm volatile ("move.w %0,%%sr"::"r" (sr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/m68k/lib/interrupts.c-56-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/cpu/cache.c-77- for (i = 0; i < size; i += 4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/cpu/cache.c:78: asm volatile (
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/cpu/cache.c-79-#ifdef CONFIG_ICACHE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/global_data.h-58-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/global_data.h:59:#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/global_data.h-60-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/ptrace.h-21-#define GPR_ZERO 0 /* constant zero */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/ptrace.h:22:#define GPR_ASM 18 /* reserved for assembler */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/ptrace.h-23-#define GPR_SP 1 /* stack pointer */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/ptrace.h-110- a process is located in memory. */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/ptrace.h:111:#define PT_TEXT_ADDR (PT_SIZE + 1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/ptrace.h-112-#define PT_TEXT_LEN (PT_SIZE + 2)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/ptrace.h:113:#define PT_DATA_ADDR (PT_SIZE + 3)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/include/asm/ptrace.h-114-#define PT_DATA_LEN (PT_SIZE + 4)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/lib/board.c-95-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/lib/board.c:96: asm ("nop"); /* FIXME gd is not initialize - wait */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/lib/board.c-97- memset ((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/lib/board.c-167- /* IP Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/lib/board.c:168: bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/microblaze/lib/board.c-169- eth_init (bd);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-50- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:51:#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:52:#define XPHYSADDR(a) ((_ACAST64_(a)) & \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-53- _CONST64_(0x000000ffffffffff))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-70-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:71:#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:72:#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:73:#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:74:#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-75-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-77-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:78:#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:79:#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:80:#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:81:#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-82-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-85- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:86:#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:87:#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:88:#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:89:#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-90-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-138-#else /* !CONFIG_SOC_AU1X00 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h:139:#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/addrspace.h-140-#endif /* CONFIG_SOC_AU1X00 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h-90-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h:91: asm volatile (
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h-92- ".set\tnoreorder\n\t"
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h-630-#define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h:631:#define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h-632-#define MAC_RX_BUFF1_STATUS 0x10
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h-828-#define SSI_ADATA_D (1<<24)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h:829:#define SSI_ADATA_ADDR (0xFF<<16)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h-830-#define SSI_ADATA_DATA (0x0FFF)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h-1033-#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h:1034:#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/au1x00.h-1035-#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/global_data.h-61-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/global_data.h:62:#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/global_data.h-63-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-690-#define INCA_IP_Switch_MDIO_ACC_RW (1 << 30)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h:691:#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h:692:#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-693-#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-713-#define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h:714:#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h:715:#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-716-#define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-1007-/***MC Access Error Address Register***/
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h:1008:#define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-1009-#define INCA_IP_SDRAM_MC_ERRADDR_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-2322-/***FB Access Error Address Register***/
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h:2323:#define INCA_IP_FB_FB_ERRADDR ((volatile u32*)(INCA_IP_FB+ 0x0108))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-2324-#define INCA_IP_FB_FB_ERRADDR_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-2362-/***BIU Access Error Address Register***/
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h:2363:#define INCA_IP_BIU_BIU_ERRADDR ((volatile u32*)(INCA_IP_BIU+ 0x0108))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/inca-ip.h-2364-#define INCA_IP_BIU_BIU_ERRADDR_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h-122-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h:123: return CPHYSADDR(address);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h-124-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h-127-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h:128: return (void *)KSEG0ADDR(address);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h-129-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h-135-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h:136: return CPHYSADDR(address);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h-137-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h-140-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h:141: return (void *)KSEG0ADDR(address);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/io.h-142-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/mipsregs.h-776-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/mipsregs.h:777:#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/mipsregs.h:778:#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/mipsregs.h-779-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/processor.h-25- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/processor.h:26:#define current_text_addr() ({ __label__ _l; _l: &&_l;})
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/processor.h-27-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/string.h-14- * We don't do inline string functions, since the
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/string.h:15: * optimised inline asm versions are not small.
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/include/asm/string.h-16- */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/lib/board.c-373- /* IP Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/lib/board.c:374: bd->bi_ip_addr = getenv_IPaddr("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/mips/lib/board.c-375-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/global_data.h-50-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/global_data.h:51:#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/global_data.h-52-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-74- ({unsigned char val;\
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h:75: asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-76-#define readw(addr)\
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-77- ({unsigned short val;\
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h:78: asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-79-#define readl(addr)\
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-80- ({unsigned long val;\
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h:81: asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-82-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-83-#define writeb(val,addr)\
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h:84: asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-85-#define writew(val,addr)\
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h:86: asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-87-#define writel(val,addr)\
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h:88: asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/include/asm/io.h-89-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/lib/board.c-145-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/lib/board.c:146: bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/lib/board.c-147-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/lib/longlong.h-47-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/lib/longlong.h:48:/* Define auxiliary asm macros.
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/nios2/lib/longlong.h-49-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc512x/common.c-6-#if defined(CONFIG_SYS_POST_WORD_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc512x/common.c:7:# define _POST_ADDR (CONFIG_SYS_POST_WORD_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc512x/common.c-8-#else
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc512x/cpu.c-158- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc512x/cpu.c:159: eth_getenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc512x/cpu.c-160- do_fixup_by_prop(blob, "device_type", "network", 8,
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc5xxx/cpu.c-132-#ifdef CONFIG_MPC5xxx_FEC
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc5xxx/cpu.c:133: eth_getenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc5xxx/cpu.c-134- do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc5xxx/loadtask.c-74-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc5xxx/loadtask.c:75: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc5xxx/loadtask.c-76-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-615- memctl->cfg1 = cfg_value; /* cfg 1 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:616: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-617-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-639- memctl->cfg2 = cfg_value; /* cfg 2 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:640: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-641-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-670- memctl->ctrl = cfg_value; /* ctrl */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:671: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-672-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-676- memctl->ctrl = temp; /* ctrl */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:677: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-678- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-688-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:689: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-690-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-695- memctl->mode = (temp >> 16); /* mode */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:696: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-697-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-700- memctl->mode = (temp >> 16); /* mode */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:701: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-702- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-717- sysconf->cscfg[banknum] = temp;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:718: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-719- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-726- memctl->ctrl = temp; /* ctrl */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:727: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-728-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-730- memctl->ctrl = temp; /* ctrl */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:731: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-732-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-733- memctl->ctrl = temp; /* ctrl */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:734: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-735-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-738- memctl->mode = (temp >> 16); /* mode */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:739: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-740-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-748- memctl->ctrl = cfg_value; /* ctrl */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c:749: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/dramSetup.c-750-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c-182-/********************************************************************/
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c:183:static void mpc8220_fec_set_hwaddr (mpc8220_fec_priv * fec, char *mac)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c-184-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c-333- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c:334: mpc8220_fec_set_hwaddr (fec, (char *)(dev->enetaddr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c-335-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c-863- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c:864: mpc8220_fec_set_hwaddr (fec, env_enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c-865- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c-874- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c:875: mpc8220_fec_set_hwaddr (fec2, env_enet1addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/fec.c-876- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/loadtask.c-76-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/loadtask.c:77: asm volatile ("sync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/loadtask.c-78-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/speed.c-90- /* CPU Clock - Read HID1 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/speed.c:91: asm volatile ("mfspr %0, 1009":"=r" (hid1):);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8220/speed.c-92-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/cpu_init.c-64-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/cpu_init.c:65:/* MOUSSE board is initialized in asm */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/cpu_init.c-66-#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-35-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c:36:#define I2C_Addr ((unsigned *)(CONFIG_SYS_EUMB_ADDR + 0x3000))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-37-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-151-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c:152:static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-153-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-217-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c:218: if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-219- goto exit;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-223-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c:224: if (i2c_write_addr (dev, I2C_READ, 1) == 0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-225- goto exit;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-242-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c:243: if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc824x/drivers/i2c/i2c.c-244- goto exit;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8260/cpu_init.c-74- if (pmsk != 0) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8260/cpu_init.c:75: volatile ioport_t *iop = ioport_addr (immr, portnum);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8260/cpu_init.c-76- uint tpmsk = ~pmsk;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8260/ether_fcc.c-656-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8260/ether_fcc.c:657: eth_getenv_enetaddr("ethaddr", NetOurEther);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8260/ether_fcc.c-658-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8260/ether_scc.c-264-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8260/ether_scc.c:265: eth_getenv_enetaddr("ethaddr", ea);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8260/ether_scc.c-266- pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc83xx/spd_sdram.c-850- do {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc83xx/spd_sdram.c:851: asm volatile ("mftbu %0":"=r" (tbu1):);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc83xx/spd_sdram.c:852: asm volatile ("mftb %0":"=r" (tbl):);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc83xx/spd_sdram.c:853: asm volatile ("mftbu %0":"=r" (tbu2):);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc83xx/spd_sdram.c-854- } while (tbu1 != tbu2);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/cpu_init.c-110- if (pmsk != 0) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/cpu_init.c:111: volatile ioport_t *iop = ioport_addr (cpm, portnum);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/cpu_init.c-112- uint tpmsk = ~pmsk;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/ddr-gen1.c-59- udelay(200);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/ddr-gen1.c:60: asm volatile("sync;isync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/ddr-gen1.c-61-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/ddr-gen2.c-65- udelay(200);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/ddr-gen2.c:66: asm volatile("sync;isync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/ddr-gen2.c-67-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/ddr-gen3.c-105- udelay(500);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/ddr-gen3.c:106: asm volatile("sync;isync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/ddr-gen3.c-107-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/fdt.c-45- int off;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/fdt.c:46: ulong spin_tbl_addr = get_spin_phys_addr();
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/fdt.c-47- u32 bootpg = determine_mp_bootpg();
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/fixed_ivor.S-24-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/fixed_ivor.S:25:/* This file is intended to be included by other asm code since
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/fixed_ivor.S-26- * we will want to execute this on both the primary core when
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-54- if (nr == id) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c:55: table = (u32 *)get_spin_virt_addr();
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-56- printf("table base @ 0x%p\n", table);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-57- } else {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c:58: table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-59- printf("Running on cpu %d\n", id);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-109-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c:110: u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-111- u64 boot_addr;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-152-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c:153:ulong get_spin_phys_addr(void)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-154-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-161-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c:162:ulong get_spin_virt_addr(void)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-163-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-174- u32 up, cpu_up_mask, whoami;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c:175: u32 *table = (u32 *)get_spin_virt_addr();
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-176- volatile ccsr_gur_t *gur;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-247- u32 up, cpu_up_mask, whoami;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c:248: u32 *table = (u32 *)get_spin_virt_addr();
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.c-249- volatile u32 bpcr;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.h-5-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.h:6:ulong get_spin_phys_addr(void);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.h:7:ulong get_spin_virt_addr(void);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/mp.h-8-u32 get_my_id(void);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/start.S-237-#ifdef CONFIG_MPC8569
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/start.S:238:#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/start.S:239:#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/start.S-240-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/start.S-409- stwu r1,-8(r1) /* Save back chain and move SP */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/start.S:410: stw r0,+12(r1) /* Save return addr (underflow vect) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/start.S-411-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/tlb.c-88-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/tlb.c:89: asm volatile("tlbre;isync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/tlb.c-90- _mas1 = mfspr(MAS1);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/tlb.c-159-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/tlb.c:160: asm volatile("isync;msync;tlbwe;isync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/tlb.c-161-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/tlb.c-208-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/tlb.c:209: asm volatile("tlbre;isync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/tlb.c-210- _mas1 = mfspr(MAS1);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/traps.c-58-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/traps.c:59: asm volatile("mtspr 0x150, %0" : : "r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/traps.c-60-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/traps.c-64- unsigned long val;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/traps.c:65: asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/traps.c-66- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds-117-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds:118: .bootpg ADDR(.text) - 0x1000 :
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds-119- {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds-122-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds:123: . = ADDR(.text) + 0x80000;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds-124-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds-55-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds:56: .resetvec ADDR(.text) + 0xffc : {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds-57- *(.resetvec)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc86xx/cpu_init.c-179- size = BATU_SIZE(upper);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc86xx/cpu_init.c:180: addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc86xx/cpu_init.c-181- size, i);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc86xx/ddr-8641.c-74- udelay(200);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc86xx/ddr-8641.c:75: asm volatile("sync;isync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc86xx/ddr-8641.c-76-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xx/speed.c-43-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xx/speed.c:44: asm volatile("mfmsr %0" : "=r" (msr) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xx/speed.c-45- return msr;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xx/speed.c-49-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xx/speed.c:50: asm volatile("mtmsr %0" : : "r" (msr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xx/speed.c-51-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c-919-/* DDR Initialization Address (DDR_INIT_ADDR) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c:920:static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c-921-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c-927-/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c:928:static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c-929-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c-1353- set_ddr_sdram_clk_cntl(ddr, popts);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c:1354: set_ddr_init_addr(ddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c:1355: set_ddr_init_ext_addr(ddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c-1356- set_timing_cfg_4(ddr, popts);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/4xx_pcie.c-923- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/4xx_pcie.c:924:static inline u64 ppc4xx_get_cfgaddr(int port)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/4xx_pcie.c-925-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/4xx_pcie.c-1046- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/4xx_pcie.c:1047: addr = ppc4xx_get_cfgaddr(port);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/4xx_pcie.c-1048- low = U64_TO_U32_LOW(addr);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/commproc.c-33-#if defined(CONFIG_SYS_POST_WORD_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/commproc.c:34:# define _POST_ADDR ((CONFIG_SYS_OCM_DATA_ADDR) + (CONFIG_SYS_POST_WORD_ADDR))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/commproc.c-35-#elif defined(CONFIG_SYS_POST_ALT_WORD_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/commproc.c:36:# define _POST_ADDR (CONFIG_SYS_POST_ALT_WORD_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/commproc.c-37-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c-248- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:249: asm volatile(" bl 0f" ::: "lr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:250: asm volatile("0: mflr 3" ::: "r3");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:251: asm volatile(" addi 4, 0, 14" ::: "r4");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:252: asm volatile(" mtctr 4" ::: "ctr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:253: asm volatile("1: icbt 0, 3");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:254: asm volatile(" addi 3, 3, 32" ::: "r3");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:255: asm volatile(" bdnz 1b" ::: "ctr", "cr0");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:256: asm volatile(" addis 3, 0, 0x0" ::: "r3");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:257: asm volatile(" ori 3, 3, 0xA000" ::: "r3");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:258: asm volatile(" mtctr 3" ::: "ctr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c:259: asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/cpu_init.c-260-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ecc.c-72-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ecc.c:73:static void program_ecc_addr(unsigned long start_address,
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ecc.c-74- unsigned long num_bytes,
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ecc.c-149- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ecc.c:150: program_ecc_addr((u32)start, size, TLB_WORD2_I_ENABLE);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ecc.c-151-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ecc.c-177-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ecc.c:178: program_ecc_addr(0, memsize, tlb_word2_i_value);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ecc.c-179- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c-59-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c:60: asm volatile("mtspr 0x03f,%0" : : "r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c-61-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c-66-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c:67: asm volatile("mtpit %0" : : "r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c-68-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c-72-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c:73: asm volatile("mttcr %0" : : "r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c-74-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c-78-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c:79: asm volatile("mtevpr %0" : : "r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/interrupts.c-80-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S-789- stwu r1,-8(r1) /* Save back chain and move SP */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S:790: stw r0,+12(r1) /* Save return addr (underflow vect) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S-791-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S-981- stwu r1, -8(r1) /* Save back chain and move SP */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S:982: stw r0, +12(r1) /* Save return addr (underflow vect) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S-983-#endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S-1140- stwu r1, -8(r1) /* Save back chain and move SP */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S:1141: stw r0, +12(r1) /* Save return addr (underflow vect) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S-1142-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S-1165- stwu r1, -8(r1) /* Save back chain and move SP */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S:1166: stw r0, +12(r1) /* Save return addr (underflow vect) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/start.S-1167-#endif /* CONFIG_SYS_INIT_DCACHE_CS */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/tlb.c-233-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/tlb.c:234:static void program_tlb_addr(u64 phys_addr,
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/tlb.c-235- u32 virt_addr,
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/tlb.c-345- /* Call the routine to add in the tlb entries for the memory regions */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/tlb.c:346: program_tlb_addr(region_array.base, virt_addr, region_array.size,
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/tlb.c-347- region_array.tlb_word2_i_value);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c-51-#if defined(CONFIG_440)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c:52: asm volatile("mtspr 0x150, %0" : : "r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c-53-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c:54: asm volatile("mttsr %0" : : "r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c-55-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c-62-#if defined(CONFIG_440)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c:63: asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c-64-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c:65: asm volatile("mfesr %0" : "=r" (val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/traps.c-66-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/bitops.h-159-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/bitops.h:160: asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/bitops.h-161- return 31 - lz;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/byteorder.h-34-/* alas, egcs sounds like it has a bug in this code that doesn't use the
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/byteorder.h:35: inline asm correctly, and can cause file corruption. Until I hear that
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/byteorder.h-36- it's fixed, I can live without the extra speed. I hope. */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/cpm_8260.h-73-#define CPM_CR_RESTART_TX ((ushort)0x0006)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/cpm_8260.h:74:#define CPM_CR_SET_GADDR ((ushort)0x0008)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/cpm_8260.h-75-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/cpm_8260.h-150-#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/cpm_8260.h:151:#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/cpm_8260.h-152-#else
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/cpm_85xx.h-67-#define CPM_CR_RESTART_TX ((ushort)0x0006)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/cpm_85xx.h:68:#define CPM_CR_SET_GADDR ((ushort)0x0008)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/cpm_85xx.h-69-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/fsl_lbc.h-75-#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/fsl_lbc.h:76:#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/fsl_lbc.h-77- ((x & 0x300000000ULL) >> 19)))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/fsl_lbc.h-78-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/fsl_lbc.h:79:#define BR_PHYS_ADDR(x) (x & 0xffff8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/fsl_lbc.h-80-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/global_data.h-190-#if 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/global_data.h:191:#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/global_data.h-192-#else /* We could use plain global data, but the resulting code is bigger */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_83xx.h-861-#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_83xx.h:862:#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_83xx.h-863-#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_83xx.h:864:#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_83xx.h-865-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_83xx.h-874-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_83xx.h:875:#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_83xx.h:876:#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_83xx.h-877-#endif /* __IMMAP_83xx__ */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_85xx.h-2146-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_85xx.h:2147:#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_85xx.h:2148:#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_85xx.h-2149-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h-1297-#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h:1298:#define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h-1299-#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h:1300:#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h-1301-#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h:1302:#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h-1303-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h-1306-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h:1307:#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h:1308:#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/immap_86xx.h-1309-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-130-#define __iomem
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h:131:#define PCI_FIX_ADDR(addr) (addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-132-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-134-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h:135: return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-136-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-138-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h:139: return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-140-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-142-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h:143: return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-144-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-146-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h:147: *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-148-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-150-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h:151: *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-152-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-154-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h:155: *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/io.h-156-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/mmu.h-211-#define BATU_VALID(x) (x & 0x3)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/mmu.h:212:#define BATU_VADDR(x) (x & 0xfffe0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/mmu.h:213:#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/mmu.h-214- | ((x & 0x0e00ULL) << 24) \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-246-#define CPR0_DCR_BASE 0x0C
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h:247:#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-248-#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-250-#define SDR_DCR_BASE 0x0E
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h:251:#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-252-#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-254-#define SDRAM_DCR_BASE 0x10
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h:255:#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-256-#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-258-#define EBC_DCR_BASE 0x12
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h:259:#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-260-#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-314-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h:315: asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-316- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-320-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h:321: asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx.h-322-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx-isram.h-66-#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx-isram.h:67:#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/ppc4xx-isram.h-68-#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-7- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h:8:#define current_text_addr() ({ __label__ _l; _l: &&_l;})
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-9-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-1073-#define mfdcr(rn) ({unsigned int rval; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h:1074: asm volatile("mfdcr %0," stringify(rn) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-1075- : "=r" (rval)); rval;})
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h:1076:#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-1077-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-1078-#define mfmsr() ({unsigned int rval; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h:1079: asm volatile("mfmsr %0" : "=r" (rval)); rval;})
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h:1080:#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-1081-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-1082-#define mfspr(rn) ({unsigned int rval; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h:1083: asm volatile("mfspr %0," stringify(rn) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-1084- : "=r" (rval)); rval;})
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h:1085:#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-1086-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h:1087:#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/include/asm/processor.h-1088-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bat_rw.c-127- size = BATU_SIZE(upper);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bat_rw.c:128: addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bat_rw.c-129- size, batn);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-719-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c:720: asm ("sync ; isync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-721-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-857- /* kept around for legacy kernels only ... ignore the next section */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c:858: eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-859-#ifdef CONFIG_HAS_ETH1
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c:860: eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-861-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-862-#ifdef CONFIG_HAS_ETH2
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c:863: eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-864-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-865-#ifdef CONFIG_HAS_ETH3
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c:866: eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-867-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-868-#ifdef CONFIG_HAS_ETH4
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c:869: eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-870-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-871-#ifdef CONFIG_HAS_ETH5
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c:872: eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-873-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-876- /* IP Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c:877: bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/board.c-878-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-33-#if defined(CONFIG_MPC5xxx)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c:34:#define CONFIG_SYS_BOOTCOUNT_ADDR (MPC5XXX_CDM_BRDCRMB)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-35-#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-38-#if defined(CONFIG_8xx)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c:39:#define CONFIG_SYS_BOOTCOUNT_ADDR (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-40- CPM_BOOTCOUNT_ADDR)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-45-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c:46:#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-47-#endif /* defined(CONFIG_MPC8260) */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-51-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c:52:#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-53- QE_MURAM_SIZE - 2 * sizeof(u32))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-56-#if defined(CONFIG_4xx)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c:57:#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_OCM_DATA_ADDR + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/bootcount.c-58- CONFIG_SYS_BOOTCOUNT_ADDR)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c-37- addr += CONFIG_SYS_CACHELINE_SIZE) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c:38: asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c-39- WATCHDOG_RESET();
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c-41- /* wait for all dcbst to complete on bus */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c:42: asm volatile("sync" : : : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c-43-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c-45- addr += CONFIG_SYS_CACHELINE_SIZE) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c:46: asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c-47- WATCHDOG_RESET();
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c-48- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c:49: asm volatile("sync" : : : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c-50- /* flush prefetch queue */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c:51: asm volatile("isync" : : : "memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/cache.c-52-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c-55-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c:56: asm volatile ("mfmsr %0":"=r" (msr):);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c-57-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c-62-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c:63: asm volatile ("mtmsr %0"::"r" (msr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c-64-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c-69-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c:70: asm volatile ("mfdec %0":"=r" (val):);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c-71-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c-78- if (val)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c:79: asm volatile ("mtdec %0"::"r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/interrupts.c-80-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c-14-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c:15: asm ("mflr 0; stw 0,0(%0);"
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c-16- "stw 1,4(%0); stw 2,8(%0);"
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c-28- val = 1;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c:29: asm ("lmw 13,16(%0);"
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c-30- "lwz 0,12(%0); mtcrf 0x38,0;"
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c-39- unsigned long msr;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c:40: asm volatile("mfmsr %0" : "=r" (msr):);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c-41- return msr;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c-46-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c:47: asm volatile("mtmsr %0" : : "r" (msr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/kgdb.c-48-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/time.c-88- /* reset */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/time.c:89: asm ("li 3,0 ; mttbu 3 ; mttbl 3 ;");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/powerpc/lib/time.c-90-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/cache.h-17- for (v = start; v < end; v += L1_CACHE_BYTES) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/cache.h:18: asm volatile ("ocbwb %0" : /* no output */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/cache.h-19- : "m" (__m(v)));
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/cache.h-28- for (v = start; v < end; v += L1_CACHE_BYTES) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/cache.h:29: asm volatile ("ocbi %0" : /* no output */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/cache.h-30- : "m" (__m(v)));
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/global_data.h-50-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/global_data.h:51:#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/global_data.h-52-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/io.h-144- * Define:
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/io.h:145: * iomem_valid_addr(off,size)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/io.h-146- * iomem_to_phys(off)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/io.h-152- void *_ret = (void *)0; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/io.h:153: if (iomem_valid_addr(_off, _size)) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/include/asm/io.h-154- _ret = __ioremap(iomem_to_phys(_off), _size, 0); \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/lib/board.c-102- DECLARE_GLOBAL_DATA_PTR;
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/lib/board.c:103: gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sh/lib/board.c-104- return 0;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon2/prom.c-944-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon2/prom.c:945: asm volatile ("sta %0, [%%g0] %1\n\t":: "r" (regval), "i"(2):"memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon2/prom.c-946-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/ambapp.c-118- if (amba_membar_type(apbmst->bars[0]) == AMBA_TYPE_AHBIO)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/ambapp.c:119: apbmst_base = AMBA_TYPE_AHBIO_ADDR(apbmst_base);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/ambapp.c-120- apbmst_base &= LEON3_IO_AREA;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/ambapp.c-230- addr =
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/ambapp.c:231: AMBA_TYPE_AHBIO_ADDR(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/ambapp.c-232- dev->address[j] = addr;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/ambapp.c-262- if (amba_membar_type(ahb->bars[info]) == AMBA_TYPE_AHBIO)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/ambapp.c:263: ret = AMBA_TYPE_AHBIO_ADDR(ret);
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/ambapp.c-264- return ret;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/prom.c-975-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/prom.c:976: asm volatile ("sta %0, [%%g0] %1\n\t":: "r" (regval), "i"(2):"memory");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/cpu/leon3/prom.c-977-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/include/asm/global_data.h-86-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/include/asm/global_data.h:87:#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("%g7")
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/include/asm/global_data.h-88-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/include/asm/srmmu.h-222-
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/include/asm/srmmu.h:223:extern __inline__ unsigned int srmmu_get_faddr(void)
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/include/asm/srmmu.h-224-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/include/asm/stack.h-72-#define FW_REGS_SZ 0x88 /* 34*4 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/include/asm/stack.h:73:#endif /* !ASM */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/include/asm/stack.h-74-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/lib/board.c-364- /* IP Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/lib/board.c:365: bd->bi_ip_addr = getenv_IPaddr("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/arch/sparc/lib/board.c-366-#if defined(CONFIG_PCI)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-178- case 0:
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c:179: __asm volatile ("mtdbatu 0, %0" : : "r" (address | length | 3));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c:180: __asm volatile ("mtdbatl 0, %0" : : "r" (address | 0x22));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-181- break;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-182- case 1:
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c:183: __asm volatile ("mtdbatu 1, %0" : : "r" (address | length | 3));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c:184: __asm volatile ("mtdbatl 1, %0" : : "r" (address | 0x22));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-185- break;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-186- case 2:
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c:187: __asm volatile ("mtdbatu 2, %0" : : "r" (address | length | 3));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c:188: __asm volatile ("mtdbatl 2, %0" : : "r" (address | 0x22));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-189- break;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-190- case 3:
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c:191: __asm volatile ("mtdbatu 3, %0" : : "r" (address | length | 3));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c:192: __asm volatile ("mtdbatl 3, %0" : : "r" (address | 0x22));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-193- break;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-200- u32 temp = 0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c:201: __asm volatile(
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue.c-202- "mtdbatu 2, %0\n"
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-176- case 0:
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c:177: __asm volatile ("mtdbatu 0, %0" : : "r" (address | length | 3));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c:178: __asm volatile ("mtdbatl 0, %0" : : "r" (address | 0x22));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-179- break;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-180- case 1:
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c:181: __asm volatile ("mtdbatu 1, %0" : : "r" (address | length | 3));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c:182: __asm volatile ("mtdbatl 1, %0" : : "r" (address | 0x22));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-183- break;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-184- case 2:
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c:185: __asm volatile ("mtdbatu 2, %0" : : "r" (address | length | 3));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c:186: __asm volatile ("mtdbatl 2, %0" : : "r" (address | 0x22));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-187- break;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-188- case 3:
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c:189: __asm volatile ("mtdbatu 3, %0" : : "r" (address | length | 3));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c:190: __asm volatile ("mtdbatl 3, %0" : : "r" (address | 0x22));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-191- break;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-198- u32 temp = 0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c:199: __asm volatile(
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/glue_test.c-200- "mtdbatu 2, %0\n"
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/ops.c-4301-****************************************************************************/
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/ops.c:4302:void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1))
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/ops.c-4303-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-70-#define VAL_TEST_BINARY(name) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c:71: r_asm = name##_asm(&flags,d,s); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-72- r = name(d,s); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c:73: if (r != r_asm || M.x86.R_EFLG != flags) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-74- failed = true; \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-79- name(d,s); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c:80: r = r_asm = 0; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-81- if (M.x86.R_EFLG != flags) \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-202-#define VAL_TEST_TERNARY(name) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c:203: r_asm = name##_asm(&flags,d,s,shift); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-204- r = name(d,s,shift); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c:205: if (r != r_asm || M.x86.R_EFLG != flags) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-206- failed = true; \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-268-#define VAL_TEST_UNARY(name) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c:269: r_asm = name##_asm(&flags,d); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-270- r = name(d); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c:271: if (r != r_asm || M.x86.R_EFLG != flags) { \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-272- failed = true;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-351- r = M.x86.R_AX; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c:352: if (r != r_asm || M.x86.R_EFLG != flags) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/validate.c-353- failed = true; \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-52-u32 get_flags_asm(void);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:53:#pragma aux get_flags_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-54- "pushf" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-59-u16 aaa_word_asm(u32 *flags,u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:60:#pragma aux aaa_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-61- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-70-u16 aas_word_asm(u32 *flags,u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:71:#pragma aux aas_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-72- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-81-u16 aad_word_asm(u32 *flags,u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:82:#pragma aux aad_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-83- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-92-u16 aam_word_asm(u32 *flags,u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:93:#pragma aux aam_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-94- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-103-u8 adc_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:104:#pragma aux adc_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-105- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-114-u16 adc_word_asm(u32 *flags,u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:115:#pragma aux adc_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-116- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-125-u32 adc_long_asm(u32 *flags,u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:126:#pragma aux adc_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-127- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-136-u8 add_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:137:#pragma aux add_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-138- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-147-u16 add_word_asm(u32 *flags,u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:148:#pragma aux add_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-149- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-158-u32 add_long_asm(u32 *flags,u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:159:#pragma aux add_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-160- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-169-u8 and_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:170:#pragma aux and_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-171- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-180-u16 and_word_asm(u32 *flags,u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:181:#pragma aux and_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-182- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-191-u32 and_long_asm(u32 *flags,u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:192:#pragma aux and_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-193- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-202-u8 cmp_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:203:#pragma aux cmp_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-204- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-213-u16 cmp_word_asm(u32 *flags,u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:214:#pragma aux cmp_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-215- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-224-u32 cmp_long_asm(u32 *flags,u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:225:#pragma aux cmp_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-226- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-235-u8 daa_byte_asm(u32 *flags,u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:236:#pragma aux daa_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-237- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-246-u8 das_byte_asm(u32 *flags,u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:247:#pragma aux das_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-248- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-257-u8 dec_byte_asm(u32 *flags,u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:258:#pragma aux dec_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-259- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-268-u16 dec_word_asm(u32 *flags,u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:269:#pragma aux dec_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-270- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-279-u32 dec_long_asm(u32 *flags,u32 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:280:#pragma aux dec_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-281- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-290-u8 inc_byte_asm(u32 *flags,u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:291:#pragma aux inc_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-292- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-301-u16 inc_word_asm(u32 *flags,u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:302:#pragma aux inc_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-303- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-312-u32 inc_long_asm(u32 *flags,u32 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:313:#pragma aux inc_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-314- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-323-u8 or_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:324:#pragma aux or_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-325- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-334-u16 or_word_asm(u32 *flags,u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:335:#pragma aux or_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-336- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-345-u32 or_long_asm(u32 *flags,u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:346:#pragma aux or_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-347- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-356-u8 neg_byte_asm(u32 *flags,u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:357:#pragma aux neg_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-358- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-367-u16 neg_word_asm(u32 *flags,u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:368:#pragma aux neg_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-369- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-378-u32 neg_long_asm(u32 *flags,u32 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:379:#pragma aux neg_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-380- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-389-u8 not_byte_asm(u32 *flags,u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:390:#pragma aux not_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-391- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-400-u16 not_word_asm(u32 *flags,u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:401:#pragma aux not_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-402- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-411-u32 not_long_asm(u32 *flags,u32 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:412:#pragma aux not_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-413- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-422-u8 rcl_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:423:#pragma aux rcl_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-424- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-433-u16 rcl_word_asm(u32 *flags,u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:434:#pragma aux rcl_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-435- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-444-u32 rcl_long_asm(u32 *flags,u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:445:#pragma aux rcl_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-446- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-455-u8 rcr_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:456:#pragma aux rcr_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-457- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-466-u16 rcr_word_asm(u32 *flags,u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:467:#pragma aux rcr_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-468- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-477-u32 rcr_long_asm(u32 *flags,u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:478:#pragma aux rcr_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-479- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-488-u8 rol_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:489:#pragma aux rol_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-490- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-499-u16 rol_word_asm(u32 *flags,u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:500:#pragma aux rol_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-501- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-510-u32 rol_long_asm(u32 *flags,u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:511:#pragma aux rol_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-512- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-521-u8 ror_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:522:#pragma aux ror_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-523- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-532-u16 ror_word_asm(u32 *flags,u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:533:#pragma aux ror_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-534- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-543-u32 ror_long_asm(u32 *flags,u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:544:#pragma aux ror_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-545- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-554-u8 shl_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:555:#pragma aux shl_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-556- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-565-u16 shl_word_asm(u32 *flags,u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:566:#pragma aux shl_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-567- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-576-u32 shl_long_asm(u32 *flags,u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:577:#pragma aux shl_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-578- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-587-u8 shr_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:588:#pragma aux shr_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-589- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-598-u16 shr_word_asm(u32 *flags,u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:599:#pragma aux shr_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-600- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-609-u32 shr_long_asm(u32 *flags,u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:610:#pragma aux shr_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-611- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-620-u8 sar_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:621:#pragma aux sar_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-622- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-631-u16 sar_word_asm(u32 *flags,u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:632:#pragma aux sar_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-633- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-642-u32 sar_long_asm(u32 *flags,u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:643:#pragma aux sar_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-644- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-653-u16 shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:654:#pragma aux shld_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-655- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-664-u32 shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:665:#pragma aux shld_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-666- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-675-u16 shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:676:#pragma aux shrd_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-677- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-686-u32 shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:687:#pragma aux shrd_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-688- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-697-u8 sbb_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:698:#pragma aux sbb_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-699- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-708-u16 sbb_word_asm(u32 *flags,u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:709:#pragma aux sbb_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-710- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-719-u32 sbb_long_asm(u32 *flags,u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:720:#pragma aux sbb_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-721- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-730-u8 sub_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:731:#pragma aux sub_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-732- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-741-u16 sub_word_asm(u32 *flags,u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:742:#pragma aux sub_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-743- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-752-u32 sub_long_asm(u32 *flags,u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:753:#pragma aux sub_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-754- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-763-void test_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:764:#pragma aux test_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-765- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-773-void test_word_asm(u32 *flags,u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:774:#pragma aux test_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-775- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-783-void test_long_asm(u32 *flags,u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:784:#pragma aux test_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-785- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-793-u8 xor_byte_asm(u32 *flags,u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:794:#pragma aux xor_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-795- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-804-u16 xor_word_asm(u32 *flags,u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:805:#pragma aux xor_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-806- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-815-u32 xor_long_asm(u32 *flags,u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:816:#pragma aux xor_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-817- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-826-void imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:827:#pragma aux imul_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-828- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-837-void imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:838:#pragma aux imul_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-839- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-849-void imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:850:#pragma aux imul_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-851- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-861-void mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:862:#pragma aux mul_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-863- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-872-void mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:873:#pragma aux mul_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-874- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-884-void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:885:#pragma aux mul_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-886- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-896-void idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:897:#pragma aux idiv_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-898- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-908-void idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:909:#pragma aux idiv_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-910- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-920-void idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:921:#pragma aux idiv_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-922- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-932-void div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:933:#pragma aux div_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-934- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-944-void div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:945:#pragma aux div_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-946- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-956-void div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h:957:#pragma aux div_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h-958- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-152-
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:153:u32 screen_addr(u32 addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-154-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-159-// Handles all special cases (bios date, model etc), and might need work
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:160:u32 memaddr(u32 addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-161-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-164- if (addr >= 0xA0000 && addr < 0xC0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:165: return screen_addr(addr); //CFG_ISA_IO_BASE_ADDRESS + addr;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-166- else if (addr >= 0xFFFF5 && addr < 0xFFFFE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-184-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:185: u8 a = in8((UBYTE *)memaddr(addr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-186- LOGMEM("rdb: %x -> %x\n", addr, a);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-191-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:192: u16 a = in16r((UWORD *)memaddr(addr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-193- LOGMEM("rdw: %x -> %x\n", addr, a);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-198-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:199: u32 a = in32r((ULONG *)memaddr(addr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-200- LOGMEM("rdl: %x -> %x\n", addr, a);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-206- LOGMEM("wrb: %x <- %x\n", addr, val);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:207: out8((UBYTE *)memaddr(addr), val);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-208-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-212- LOGMEM("wrw: %x <- %x\n", addr, val);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:213: out16r((UWORD *)memaddr(addr), val);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-214-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-218- LOGMEM("wrl: %x <- %x\n", addr, val);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:219: out32r((ULONG *)memaddr(addr), val);
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-220-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-900- {
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c:901: __asm volatile("tlbre %0, %3, 0 \n\
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/bios_emulator/x86interface.c-902- tlbre %1, %3, 1 \n\
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-38- int x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:39: asm volatile ("lbz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-40- return (uint8)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-45-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:46: asm volatile ("stb %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-47-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-51- int x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:52: asm volatile ("lhbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m" (*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-53- return (uint16)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-58- int x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:59: asm volatile ("lhz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-60- return (uint16)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-64-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:65: asm volatile ("sthbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-66-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-69-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:70: asm volatile ("sth %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-71-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-75- unsigned long x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:76: asm volatile ("lwbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m"(*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-77- return (uint32)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-82- unsigned long x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:83: asm volatile ("lwz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-84- return (uint32)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-88-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:89: asm volatile ("stwbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-90-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-93-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:94: asm volatile ("stw %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x));
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-95-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-97-/*
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h:98:#define CONFIG_ADDR(bus, devfn, offset) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/memio.h-99- write_long_big((uint32 *)0xEEC00000, \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/sys_dep.c-346-
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/sys_dep.c:347:static void set_load_addr(void * const new_load_addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/board/ACube/common/sys_dep.c-348-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-1607-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:1608: serial: punt unused serial_addr()
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-1609-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-2004-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:2005: x86: #ifdef out getenv_IPaddr()
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-2006-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-3745- The appropriate include/asm-$ARCH directory should already by symlinked
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:3746: to include/asm so using the whole "asm-$ARCH" path is unnecessary.
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-3747-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-7587- the volatile r12 is used so be sure to do GET_GOT in
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:7588: asm code when you need to access global data.
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-7589-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-8297-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:8298: Commit 6a45e384955262882375a2785426dc65aeb636c4 (Make getenv_IPaddr() global)
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-8299- inadvertently added ' #include "net.h" ' to the standalone programs, creating
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-8557-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:8558: Make getenv_IPaddr() global
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-8559-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-8567-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:8568: For this, make getenv_IPaddr() global. This fixes build error
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-8569-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-10747-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:10748: i386: Remove inline asm symbols from .dynsym
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-10749-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-10773-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:10774: i386: Fix global label in inline asm compile error
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-10775-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-17931-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:17932: i386: Change inline asm global symbols to local
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-17933-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:17934: gcc 4.3.2 optimiser creates multiple copies of inline asm (who knows why)
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-17935- Remove use of global names for labels to prevent 'symbol already defined'
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-29199-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:29200: Replace __asm references with __asm__
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-29201-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32396-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32397: powerpc: Only use eth_getenv_enetaddr() if networking is enabled
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32398-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32651-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32652: Also stop calling load_sernum_ethaddr() since all boards now implement
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32653- this as a stub.
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32661-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32662: boards: get mac address from env and move load_sernum_ethaddr() to board init
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32663-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32668- Rather than have common ppc code call a board-specific function like
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32669: load_sernum_ethaddr(), have each board call it in its own board-specific
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32670- misc_init_r() function.
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32690-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32691: Also rename load_sernum_ethaddr() to misc_init_r() so we don't need to
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32692- handle this board specially in common ARM code.
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32700-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32701: boards: move board_get_enetaddr() into board-specific init
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32702-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32707- Rather than have the common ppc code have board-specific hooks, move the
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32708: board_get_enetaddr() function into the board-specific init functions.
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32709-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32741-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32742: For the nx823, the serial number is moved out of load_sernum_ethaddr() and
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32743- into misc_init_r() as is the env setup. This lets us kill off the former
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32971-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32972: nvedit: do not update global bi_enetaddr and do not call eth_set_enetaddr()
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32973-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32974- Since the ethernet layer handles updating of device addresses itself from
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:32975: the environment, there is no point in calling eth_set_enetaddr().
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-32976-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-33068-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:33069: convert print_IPaddr() to %pI4
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-33070-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-33071- Now that our printf functions support the %pI4 modifier like the kernel,
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:33072: let's drop the inflexible print_IPaddr() function and covert over to the
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-33073- %pI4 modifier.
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-36930-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:36931: Move is_valid_ether_addr() to include/net.h
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-36932-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:36933: Import the is_valid_ether_addr() function from the Linux kernel.
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-36934-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-39882- The proper way to handle this is to use the virt_to_phys() and
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:39883: BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-39884- with the the virtual address the NAND code uses.
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-42636- the regions are contiguous and depend on being so. This cleans
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:42637: that up a bit. Also, add BR_PHYS_ADDR() macro to convert
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-42638- addresses into the proper format for BR registers.
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-43410- Renamed show_boot_progress in assembler init phase to
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:43411: show_boot_progress_asm to avoid link conflicts with C version
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-43412-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-63997-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:63998: [MIPS] asm headers' updates
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-63999-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:64000: Make some asm headers adjusted to the latest Linux kernel.
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-64001-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-68982- * Moved TLB/LAW and CCSR init into cpu_early_init_f()
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:68983: * Reworked initial asm code to do most of the core init before TLBs
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-68984-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-76796-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:76797: [MIPS] Remove inline asm string functions
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-76798-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-76799- Stop using inline string functions on MIPS as other ARCHs do so,
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:76800: since the optimized inline asm versions are not small.
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-76801-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-76812-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:76813: [MIPS] Update asm string header
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-76814-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-82898- i386.(File: cpu/i386/start.S)
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:82899: In the code, bss_start addr (starting addr of bss section) is put into
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-82900- the register %eax, but the code which clears the bss section refers to
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-83138- fix: interrupt handler
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:83139: remove asm code
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-83140-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-83144-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG:83145: fix: remove asm code
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-83146-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-before-U-Boot-1.1.5-1353-
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-before-U-Boot-1.1.5:1354:* Fix problem in ppc4xx eth-driver without ethaddr (only without
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-before-U-Boot-1.1.5-1355- CONFIG_NET_MULTI set)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-before-U-Boot-1.1.5-3172- Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-before-U-Boot-1.1.5:3173: load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
qemu-5.1+dfsg/roms/u-boot-sam460ex/CHANGELOG-before-U-Boot-1.1.5-3174- various changes to KUP4 board specific files
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c-139- if (ctx.flags & F_LINENO) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c:140: if ((line_info_from_addr ((Elf32_Word) ctx.virtual, filename,
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c-141- funcname, &line_no) == TRUE) &&
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c-156- if ((symname =
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c:157: symbol_name_from_addr ((Elf32_Word) ctx.virtual,
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c-158- TRUE, 0)) != 0) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c-163- ((symname =
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c:164: symbol_name_from_addr ((Elf32_Word) ctx.virtual,
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c-165- FALSE, &symoffset)) != 0)) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c-279- ((symname =
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c:280: symbol_name_from_addr (operand, 0, &offset)) != 0)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/bedbug.c-281- sprintf (&ctx->data[ctx->datalen], " <%s", symname);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ambapp.c-217- if (amba_membar_type(ahb->bars[j]) == AMBA_TYPE_AHBIO)
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ambapp.c:218: addr = AMBA_TYPE_AHBIO_ADDR(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ambapp.c-219- mask = amba_membar_mask(ahb->bars[j]) << 20;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c-117- * ====================================================================== */
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c:118:int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c-119-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c-159- return rcode;
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c:160:} /* do_bedbug_asm */
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c-161-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c-284- * Interpreter command to continue to the next instruction, stepping into
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c:285: * subroutines. Works by calling the find_next_addr() routine to compute
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c-286- * the address passes control to the CPU-specific set breakpoint routine
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c-315- * Interpreter command to continue to the next instruction, stepping over
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c:316: * subroutines. Works by calling the find_next_addr() routine to compute
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bedbug.c-317- * the address passes control to the CPU-specific set breakpoint routine
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bootm.c-312-
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bootm.c:313: set_working_fdt_addr(images.ft_addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_bootm.c-314-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_elf.c-133- tmp = (char *) CONFIG_SYS_NVRAM_BASE_ADDR + 0x500;
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_elf.c:134: eth_getenv_enetaddr("ethaddr", (uchar *)build_buf);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_elf.c-135- memcpy(tmp, &build_buf[3], 3);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_elf.c-137- tmp = (char *) CONFIG_SYS_VXWORKS_MAC_PTR;
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_elf.c:138: eth_getenv_enetaddr("ethaddr", (uchar *)build_buf);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_elf.c-139- memcpy(tmp, build_buf, 6);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_fdt.c-52-
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_fdt.c:53:void set_working_fdt_addr(void *addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_fdt.c-54-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_fdt.c-89- addr = simple_strtoul(argv[2], NULL, 16);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_fdt.c:90: set_working_fdt_addr((void *)addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_fdt.c-91-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c-111-#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c:112:#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c:113:#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c-114-#else /* single bus */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c-117-#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c:118:#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c:119:#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c-120-#endif /* CONFIG_MULTI_BUS */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c-590- for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c:591: if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c-592- skip = 1;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c-607- if (COMPARE_BUS(bus,k))
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c:608: printf(" %02X", NO_PROBE_ADDR(k));
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_i2c.c-609- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c-168-#ifndef CONFIG_SYS_ATA_PORT_ADDR
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c:169:#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c-170-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c-527- debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c:528: dev, port, val, (ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port)));
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c:529: outb(val, (ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port)));
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c-530-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c-537- uchar val;
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c:538: val = inb((ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port)));
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c-539- debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c:540: dev, port, (ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port)), val);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_ide.c-541- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_net.c-309- if (argc < 2) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_net.c:310: NetNtpServerIP = getenv_IPaddr ("ntpserverip");
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_net.c-311- if (NetNtpServerIP == 0) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_nvedit.c-183-
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_nvedit.c:184: uchar *env_data = env_get_addr(0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_nvedit.c-185-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_nvedit.c-257-#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_nvedit.c:258: && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_nvedit.c-259-#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_nvedit.c-557- continue;
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_nvedit.c:558: return ((char *)env_get_addr(val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/cmd_nvedit.c-559- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_common.c-198-
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_common.c:199:uchar *env_get_addr (int index)
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_common.c-200-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_common.c-287-
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_common.c:288: lval = (char *)env_get_addr(i);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_common.c-289- rval = strchr(lval, '=');
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_embedded.c-73-#if defined(__bfin__)
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_embedded.c:74:# define GEN_SET_VALUE(name, value) asm (".set " GEN_SYMNAME(name) ", " GEN_VALUE(value))
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_embedded.c-75-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_embedded.c:76:# define GEN_SET_VALUE(name, value) asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_embedded.c-77-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_embedded.c-80-#define GEN_ABS(name, value) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_embedded.c:81: asm (".globl " GEN_SYMNAME(name)); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/env_embedded.c-82- GEN_SET_VALUE(name, value)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/image.c-1253-
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/image.c:1254: set_working_fdt_addr(*of_flat_tree);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/image.c-1255- return 0;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/lynxkdi.c-36- parms->dramsz = kbd->bi_memsize;
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/lynxkdi.c:37: eth_getenv_enetaddr("ethaddr", parms->ethaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/common/lynxkdi.c-38- mtspr (SPRN_SPRG2, 0x0020);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.AMCC-eval-boards-cleanup-27- using defines in board configuration file. No board specific
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.AMCC-eval-boards-cleanup:28: asm file needed anymore.
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.AMCC-eval-boards-cleanup-29-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.drivers.eth-110- int ape_halt(struct eth_device *dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.drivers.eth:111: int ape_write_hwaddr(struct eth_device *dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.drivers.eth-112-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-72-
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr:73: * void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-74-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-77-uchar enetaddr[6];
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr:78:eth_parse_enetaddr(addr, enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-79-/* enetaddr now equals { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 } */
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-80-
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr:81: * int eth_getenv_enetaddr(char *name, uchar *enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-82-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-85-all cases, the enetaddr memory is initialized. If the env var is not found,
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr:86:then it is set to all zeros. The common function is_valid_ether_addr() is used
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-87-to determine address validity.
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-88-uchar enetaddr[6];
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr:89:if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-90- /* "ethaddr" is not set in the environment */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-94-
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr:95: * int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-96-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-99-uchar enetaddr[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 };
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr:100:eth_setenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.enetaddr-101-/* the "ethaddr" env var should now be set to "00:11:22:33:44:55" */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.phytec.pcm030-39-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.phytec.pcm030:40:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.phytec.pcm030-41-#define CONFIG_ENV_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.update-32- in environment variable 'loadaddr'. If this variable is not present, the
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.update:33: transfer is made to the address given in CONFIG_UPDATE_LOAD_ADDR (0x100000
qemu-5.1+dfsg/roms/u-boot-sam460ex/doc/README.update-34- by default).
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/atibios.c-123-****************************************************************************/
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/atibios.c:124:static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/atibios.c-125-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/atibios.c-197-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/atibios.c:198: BIOSImageBus = PCI_findBIOSAddr(pcidev, &BIOSImageBAR);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/atibios.c-199- if (BIOSImageBus == 0) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-75-****************************************************************************/
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c:76:static u8 *BE_memaddr(u32 addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-77-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-130- else {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c:131: u8 val = readb_le(BE_memaddr(addr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-132- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-151- else {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c:152: u8 *base = BE_memaddr(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-153- u16 val = readw_le(base);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-173- else {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c:174: u8 *base = BE_memaddr(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-175- u32 val = readl_le(base);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-191- if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c:192: writeb_le(BE_memaddr(addr), val);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-193- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-207- if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c:208: u8 *base = BE_memaddr(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-209- writew_le(base, val);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-225- if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c:226: u8 *base = BE_memaddr(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/besys.c-227- writel_le(base, val);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-52-u32 get_flags_asm(void);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:53:#pragma aux get_flags_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-54- "pushf" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-59-u16 aaa_word_asm(u32 * flags, u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:60:#pragma aux aaa_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-61- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-70-u16 aas_word_asm(u32 * flags, u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:71:#pragma aux aas_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-72- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-81-u16 aad_word_asm(u32 * flags, u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:82:#pragma aux aad_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-83- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-92-u16 aam_word_asm(u32 * flags, u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:93:#pragma aux aam_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-94- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-103-u8 adc_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:104:#pragma aux adc_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-105- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-114-u16 adc_word_asm(u32 * flags, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:115:#pragma aux adc_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-116- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-125-u32 adc_long_asm(u32 * flags, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:126:#pragma aux adc_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-127- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-136-u8 add_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:137:#pragma aux add_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-138- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-147-u16 add_word_asm(u32 * flags, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:148:#pragma aux add_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-149- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-158-u32 add_long_asm(u32 * flags, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:159:#pragma aux add_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-160- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-169-u8 and_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:170:#pragma aux and_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-171- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-180-u16 and_word_asm(u32 * flags, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:181:#pragma aux and_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-182- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-191-u32 and_long_asm(u32 * flags, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:192:#pragma aux and_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-193- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-202-u8 cmp_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:203:#pragma aux cmp_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-204- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-213-u16 cmp_word_asm(u32 * flags, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:214:#pragma aux cmp_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-215- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-224-u32 cmp_long_asm(u32 * flags, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:225:#pragma aux cmp_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-226- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-235-u8 daa_byte_asm(u32 * flags, u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:236:#pragma aux daa_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-237- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-246-u8 das_byte_asm(u32 * flags, u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:247:#pragma aux das_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-248- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-257-u8 dec_byte_asm(u32 * flags, u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:258:#pragma aux dec_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-259- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-268-u16 dec_word_asm(u32 * flags, u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:269:#pragma aux dec_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-270- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-279-u32 dec_long_asm(u32 * flags, u32 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:280:#pragma aux dec_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-281- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-290-u8 inc_byte_asm(u32 * flags, u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:291:#pragma aux inc_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-292- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-301-u16 inc_word_asm(u32 * flags, u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:302:#pragma aux inc_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-303- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-312-u32 inc_long_asm(u32 * flags, u32 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:313:#pragma aux inc_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-314- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-323-u8 or_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:324:#pragma aux or_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-325- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-334-u16 or_word_asm(u32 * flags, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:335:#pragma aux or_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-336- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-345-u32 or_long_asm(u32 * flags, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:346:#pragma aux or_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-347- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-356-u8 neg_byte_asm(u32 * flags, u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:357:#pragma aux neg_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-358- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-367-u16 neg_word_asm(u32 * flags, u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:368:#pragma aux neg_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-369- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-378-u32 neg_long_asm(u32 * flags, u32 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:379:#pragma aux neg_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-380- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-389-u8 not_byte_asm(u32 * flags, u8 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:390:#pragma aux not_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-391- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-400-u16 not_word_asm(u32 * flags, u16 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:401:#pragma aux not_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-402- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-411-u32 not_long_asm(u32 * flags, u32 d);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:412:#pragma aux not_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-413- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-422-u8 rcl_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:423:#pragma aux rcl_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-424- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-433-u16 rcl_word_asm(u32 * flags, u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:434:#pragma aux rcl_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-435- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-444-u32 rcl_long_asm(u32 * flags, u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:445:#pragma aux rcl_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-446- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-455-u8 rcr_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:456:#pragma aux rcr_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-457- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-466-u16 rcr_word_asm(u32 * flags, u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:467:#pragma aux rcr_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-468- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-477-u32 rcr_long_asm(u32 * flags, u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:478:#pragma aux rcr_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-479- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-488-u8 rol_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:489:#pragma aux rol_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-490- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-499-u16 rol_word_asm(u32 * flags, u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:500:#pragma aux rol_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-501- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-510-u32 rol_long_asm(u32 * flags, u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:511:#pragma aux rol_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-512- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-521-u8 ror_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:522:#pragma aux ror_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-523- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-532-u16 ror_word_asm(u32 * flags, u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:533:#pragma aux ror_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-534- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-543-u32 ror_long_asm(u32 * flags, u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:544:#pragma aux ror_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-545- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-554-u8 shl_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:555:#pragma aux shl_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-556- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-565-u16 shl_word_asm(u32 * flags, u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:566:#pragma aux shl_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-567- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-576-u32 shl_long_asm(u32 * flags, u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:577:#pragma aux shl_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-578- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-587-u8 shr_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:588:#pragma aux shr_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-589- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-598-u16 shr_word_asm(u32 * flags, u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:599:#pragma aux shr_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-600- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-609-u32 shr_long_asm(u32 * flags, u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:610:#pragma aux shr_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-611- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-620-u8 sar_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:621:#pragma aux sar_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-622- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-631-u16 sar_word_asm(u32 * flags, u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:632:#pragma aux sar_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-633- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-642-u32 sar_long_asm(u32 * flags, u32 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:643:#pragma aux sar_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-644- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-653-u16 shld_word_asm(u32 * flags, u16 d, u16 fill, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:654:#pragma aux shld_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-655- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-664-u32 shld_long_asm(u32 * flags, u32 d, u32 fill, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:665:#pragma aux shld_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-666- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-675-u16 shrd_word_asm(u32 * flags, u16 d, u16 fill, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:676:#pragma aux shrd_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-677- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-686-u32 shrd_long_asm(u32 * flags, u32 d, u32 fill, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:687:#pragma aux shrd_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-688- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-697-u8 sbb_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:698:#pragma aux sbb_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-699- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-708-u16 sbb_word_asm(u32 * flags, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:709:#pragma aux sbb_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-710- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-719-u32 sbb_long_asm(u32 * flags, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:720:#pragma aux sbb_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-721- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-730-u8 sub_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:731:#pragma aux sub_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-732- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-741-u16 sub_word_asm(u32 * flags, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:742:#pragma aux sub_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-743- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-752-u32 sub_long_asm(u32 * flags, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:753:#pragma aux sub_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-754- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-763-void test_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:764:#pragma aux test_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-765- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-773-void test_word_asm(u32 * flags, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:774:#pragma aux test_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-775- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-783-void test_long_asm(u32 * flags, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:784:#pragma aux test_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-785- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-793-u8 xor_byte_asm(u32 * flags, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:794:#pragma aux xor_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-795- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-804-u16 xor_word_asm(u32 * flags, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:805:#pragma aux xor_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-806- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-815-u32 xor_long_asm(u32 * flags, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:816:#pragma aux xor_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-817- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-826-void imul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:827:#pragma aux imul_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-828- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-837-void imul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:838:#pragma aux imul_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-839- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-849-void imul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:850:#pragma aux imul_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-851- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-861-void mul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:862:#pragma aux mul_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-863- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-872-void mul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:873:#pragma aux mul_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-874- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-884-void mul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:885:#pragma aux mul_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-886- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-896-void idiv_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:897:#pragma aux idiv_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-898- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-908-void idiv_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:909:#pragma aux idiv_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-910- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-920-void idiv_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:921:#pragma aux idiv_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-922- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-932-void div_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:933:#pragma aux div_byte_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-934- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-944-void div_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:945:#pragma aux div_word_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-946- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-956-void div_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h:957:#pragma aux div_long_asm = \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/include/x86emu/prim_asm.h-958- "push [edi]" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/x86emu/ops.c-909-****************************************************************************/
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/x86emu/ops.c:910:void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1))
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/bios_emulator/x86emu/ops.c-911-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c-261- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c:262: ATAPI_SET_DEV_ADDR(base, ata_reg);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c-263-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c-293- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c:294: ATAPI_SET_DEV_ADDR(base, ata_reg);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c-295-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c-336- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c:337: ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c-338-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c-381- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c:382: ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.c-383-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.h-91- bfin_read16(base + ATAPI_OFFSET_STATUS)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.h:92:#define ATAPI_GET_DEV_ADDR(base)\
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.h-93- bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.h:94:#define ATAPI_SET_DEV_ADDR(base, val)\
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/block/pata_bfin.h-95- bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/gpio/pca953x.c-29-#ifndef CONFIG_SYS_I2C_PCA953X_ADDR
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/gpio/pca953x.c:30:#define CONFIG_SYS_I2C_PCA953X_ADDR (~0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/gpio/pca953x.c-31-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c-316-static __inline__ int
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c:317:i2c_write_addr (u8 dev, u8 dir, int rsta)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c-318-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c-383- if (i2c_wait4bus() >= 0
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c:384: && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c-385- && __i2c_write(&a[4 - alen], alen) == alen)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c-388- if (length
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c:389: && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c-390- i = __i2c_read(data, length);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c-409- if (i2c_wait4bus() >= 0
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c:410: && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/fsl_i2c.c-411- && __i2c_write(&a[4 - alen], alen) == alen) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/mxc_i2c.c-134-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/mxc_i2c.c:135:static int i2c_addr(uchar chip, uint addr, int alen)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/mxc_i2c.c-136-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/mxc_i2c.c-155-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/mxc_i2c.c:156: if (i2c_addr(chip, addr, alen)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/mxc_i2c.c-157- printf("i2c_addr failed\n");
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/mxc_i2c.c-192-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/mxc_i2c.c:193: if (i2c_addr(chip, addr, alen))
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/mxc_i2c.c-194- return -1;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/pca9564_i2c.c-107- * addr: Memory (register) address within the chip
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/pca9564_i2c.c:108: * alen: Number of bytes to use for addr (typically 1, 2 for larger
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/pca9564_i2c.c-109- * memories, 0 for register type devices with only one
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/s3c44b0_i2c.c-86- * addr: Memory (register) address within the chip
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/s3c44b0_i2c.c:87: * alen: Number of bytes to use for addr (typically 1, 2 for larger
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/s3c44b0_i2c.c-88- * memories, 0 for register type devices with only one
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/tsi108_i2c.c-134- * byte_addr: Memory or register address within the chip
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/tsi108_i2c.c:135: * alen: Number of bytes to use for addr (typically 1, 2 for larger
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/tsi108_i2c.c-136- * memories, 0 for register type devices with only one
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/tsi108_i2c.c-240- * byte_addr: Memory or register address within the chip
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/tsi108_i2c.c:241: * alen: Number of bytes to use for addr (typically 1, 2 for larger
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/i2c/tsi108_i2c.c-242- * memories, 0 for register type devices with only one
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/misc/ds4510.c-30-#ifndef CONFIG_SYS_I2C_DS4510_ADDR
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/misc/ds4510.c:31:#define CONFIG_SYS_I2C_DS4510_ADDR (~0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/misc/ds4510.c-32-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mmc/bfin_sdh.c-120- /* configure DMA */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mmc/bfin_sdh.c:121: bfin_write_DMA_START_ADDR(data->dest);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mmc/bfin_sdh.c-122- bfin_write_DMA_X_COUNT(data->blocksize / 4);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/atmel_nand_ecc.h-29-#define ATMEL_ECC_PR 0x0c /* Parity register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/atmel_nand_ecc.h:30:#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/atmel_nand_ecc.h:31:#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/atmel_nand_ecc.h-32-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/bfin_nand.c-70- else
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/bfin_nand.c:71: bfin_write_NFC_ADDR(cmd);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/bfin_nand.c-72- SSYNC();
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-168- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:169:static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-170-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-317- out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:318: set_addr(mtd, 0, page_addr, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-319-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-332- out_be32(&lbc->fbcr, mtd->oobsize - column);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:333: set_addr(mtd, column, page_addr, 1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-334-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-355-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:356: set_addr(mtd, 0, 0, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-357- fsl_elbc_run_command(mtd);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-363- "page_addr: 0x%x.\n", page_addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:364: set_addr(mtd, 0, page_addr, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-365- return;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-432- out_be32(&lbc->fcr, fcr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:433: set_addr(mtd, column, page_addr, ctrl->oob);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-434- return;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-462- out_be32(&lbc->fbcr, 3);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:463: set_addr(mtd, 6, page_addr, 1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-464-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-486- out_be32(&lbc->fbcr, 1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:487: set_addr(mtd, 0, 0, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-488- ctrl->read_bytes = 1;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-647- out_be32(&lbc->fbcr, 1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:648: set_addr(mtd, 0, 0, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-649- ctrl->read_bytes = 1;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-745- if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c:746: (br & or & BR_BA) == BR_PHYS_ADDR(base_addr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/fsl_elbc_nand.c-747- break;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c-159-/* Invoke address cycle */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c:160:static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c-161-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c-229- if (column != -1) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c:230: mpc5121_nfc_send_addr(mtd, column);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c-231- if (mtd->writesize > 512)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c:232: mpc5121_nfc_send_addr(mtd, column >> 8);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c-233- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c-236- do {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c:237: mpc5121_nfc_send_addr(mtd, page & 0xFF);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mpc5121_nfc.c-238- page >>= 8;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c-340- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c:341:static void send_addr(struct mxc_nand_host *host, uint16_t addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c-342-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c:343: MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c-344-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c-1232- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c:1233: send_addr(host, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c-1234- if (host->pagesize_2k)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c-1235- /* another col addr cycle for 2k page */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c:1236: send_addr(host, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c-1237- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c-1242- do {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c:1243: send_addr(host, page_addr & 0xFF);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/nand/mxc_nand.c-1244- page_addr >>= 8;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-253- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c:254:static loff_t flexonenand_addr(struct onenand_chip *this, int block)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-255-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-272-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c:273:loff_t onenand_addr(struct onenand_chip *this, int block)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-274-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-276- return (loff_t) block << this->erase_shift;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c:277: return flexonenand_addr(this, block);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-278-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-357- page = (int) (addr
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c:358: - onenand_addr(this, block)) >> this->page_shift;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-359- page &= this->page_mask;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-2393- for (block = start; block <= end; block++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c:2394: addr = flexonenand_addr(this, block);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/onenand_base.c-2395- if (onenand_block_isbad_nolock(mtd, addr, 0))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-119-#if defined(CONFIG_S3C64XX)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c:120:static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-121-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-124-#elif defined(CONFIG_S5PC1XX)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c:125:static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-126-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-318-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c:319: mem_addr = onenand->mem_addr(fba, fpa, fsa);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-320-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-490- for (block = 0; block < end; block++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c:491: tmp = s3c_read_cmd(CMD_MAP_01(onenand->mem_addr(block, 0, 0)));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-492-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-506- start = ofs >> this->erase_shift;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c:507: start_mem_addr = onenand->mem_addr(start, 0, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-508- end = start + (len >> this->erase_shift) - 1;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c:509: end_mem_addr = onenand->mem_addr(end, 0, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/mtd/onenand/samsung.c-510-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/3c589.c-174-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/3c589.c:175:static void el_get_mac_addr( unsigned char *mac_addr )
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/3c589.c-176-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/3c589.c-264-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/3c589.c:265: if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/3c589.c:266: el_get_mac_addr(mac_addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/3c589.c:267: eth_setenv_enetaddr("ethaddr", mac_addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/3c589.c-268- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c-1938- case 0:
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c:1939: eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c-1940- hw_addr[eth_num] = 0x0;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c-1943- case 1:
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c:1944: eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c-1945- hw_addr[eth_num] = 0x100;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c-1949- case 2:
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c:1950: eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c-1951-#if defined(CONFIG_460GT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c-1959- case 3:
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c:1960: eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/4xx_enet.c-1961-#if defined(CONFIG_460GT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88180.c-637-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88180.c:638:static void ax88180_read_mac_addr (struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88180.c-639-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88180.c-720-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88180.c:721: ax88180_read_mac_addr (dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88180.c-722-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88796.c-96-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88796.c:97:static void ax88796_eep_setaddr(u16 addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88796.c-98-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88796.c-134- /* ADDRESS */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88796.c:135: ax88796_eep_setaddr(addr++);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ax88796.c-136- /* GET DATA */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-452-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c:453: eth_getenv_enetaddr("ethaddr", pDevice->NodeAddress);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-454- LM_SetMacAddress (pDevice);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-893- *pMemoryBlockVirt = (PLM_VOID) pvirt;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c:894: MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-895-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1307- *len = pPacket->PacketSize;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c:1308: MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1309-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1319- PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c:1320: MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1321-}
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1322-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c:1323:void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1324-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1333-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c:1334:void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1335-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1337-#if (BITS_PER_LONG == 64)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c:1338: set_64bit_addr (paddr, baddr & 0xffffffff, baddr >> 32);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1339-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c:1340: set_64bit_addr (paddr, baddr, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x.c-1341-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x_mm.h-130-/* Macro for setting 64bit address struct */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x_mm.h:131:#define set_64bit_addr(paddr, low, high) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x_mm.h-132- (paddr)->Low = low; \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x_mm.h-138-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x_mm.h:139:extern void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x_mm.h:140:extern void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bcm570x_mm.h-141-extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice,
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bfin_mac.c-306-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bfin_mac.c:307:static int bfin_EMAC_setup_addr(struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bfin_mac.c-308-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bfin_mac.c-334- /* Initialize EMAC address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bfin_mac.c:335: bfin_EMAC_setup_addr(dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bfin_mac.c-336-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bfin_mac.h-62-static int bfin_EMAC_recv(struct eth_device *dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bfin_mac.h:63:static int bfin_EMAC_setup_addr(struct eth_device *dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/bfin_mac.h-64-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/cs8900.c-131-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/cs8900.c:132:void cs8900_get_enetaddr(struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/cs8900.c-133-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/cs8900.c-330- /* Load MAC address from EEPROM */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/cs8900.c:331: cs8900_get_enetaddr(dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/cs8900.c-332-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/davinci_emac.c-73- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/davinci_emac.c:74:void davinci_eth_set_mac_addr(const u_int8_t *addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/davinci_emac.c-75-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c-172-static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c:173:static void read_hw_addr(struct eth_device* dev, bd_t * bis);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c-174-#endif /* CONFIG_TULIP_FIX_DAVICOM */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c-305-#ifndef CONFIG_TULIP_FIX_DAVICOM
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c:306: read_hw_addr(dev, bis);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c-307-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c-705-#ifndef CONFIG_TULIP_FIX_DAVICOM
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c:706:static void read_hw_addr(struct eth_device *dev, bd_t *bis)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c-707-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c-757- /* Ethernet Addr... */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c:758: if (!eth_getenv_enetaddr("ethaddr", enetaddr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dc2114x.c-759- return;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dm9000x.c-550-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dm9000x.c:551:static void dm9000_get_enetaddr(struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dm9000x.c-552-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dm9000x.c-623- /* Load MAC address from EEPROM */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dm9000x.c:624: dm9000_get_enetaddr(dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dm9000x.c-625-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dnet.c-203-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dnet.c:204:static void dnet_set_hwaddr(struct eth_device *netdev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dnet.c-205-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dnet.c-325- /* set hardware address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dnet.c:326: dnet_set_hwaddr(netdev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/dnet.c-327-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/e1000.c-1105-static int
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/e1000.c:1106:e1000_read_mac_addr(struct eth_device *nic)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/e1000.c-1107-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/e1000.c-5218-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/e1000.c:5219: e1000_read_mac_addr(nic);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/e1000.c-5220-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-241-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c:242:static void read_hw_addr (struct eth_device *dev, bd_t * bis);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-243-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-323- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c:324:static struct eth_device* verify_phyaddr (char *devname, unsigned char addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-325-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-357-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c:358: dev = verify_phyaddr(devname, addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-359- if (dev == NULL)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-374-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c:375: dev = verify_phyaddr(devname, addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-376- if (dev == NULL)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-476-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c:477: read_hw_addr (dev, bis);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-478- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-917-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c:918:static void read_hw_addr (struct eth_device *dev, bd_t * bis)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/eepro100.c-919-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/enc28j60.c-354- encReset ();
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/enc28j60.c:355: eth_getenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/enc28j60.c-356- encInit (enetaddr);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ethoc.c-108-#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ethoc.c:109:#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ethoc.c-110- MIIADDRESS_RGAD(reg))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c-312-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c:313:static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c-314-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c-327-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c:328: return !is_valid_ether_addr(mac);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c-329-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c-331-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c:332:static int fec_set_hwaddr(struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c-333-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c-751-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c:752: if (fec_get_hwaddr(edev, ethaddr) == 0) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fec_mxc.c-753- printf("got MAC address from EEPROM: %pM\n", ethaddr);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fsl_mcdmafec.c-326-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fsl_mcdmafec.c:327:static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fsl_mcdmafec.c-328-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fsl_mcdmafec.c-401- if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fsl_mcdmafec.c:402: eth_getenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fsl_mcdmafec.c-403- else
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fsl_mcdmafec.c:404: eth_getenv_enetaddr("eth1addr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fsl_mcdmafec.c:405: fec_set_hwaddr(fecp, enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/fsl_mcdmafec.c-406-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ftmac100.c-69-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ftmac100.c:70: eth_getenv_enetaddr ("ethaddr", dev->enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ftmac100.c-71-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/greth.c-557-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/greth.c:558:void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/greth.c-559-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/greth.c-658- /* set and remember MAC address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/greth.c:659: greth_set_hwaddr(greth, addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/greth.c-660-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-234- for (i = 0; i < NUM_RX_DESC; i++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:235: inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-236- memset(rx_desc, 0, sizeof(rx_ring[i]));
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-252- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:253: rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-254- } else {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-256- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:257: rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-258- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-259-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:260: rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-261- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-268- for (i = 0; i < NUM_TX_DESC; i++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:269: inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-270-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-282- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:283: tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-284- } else {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-286- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:287: tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-288- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-346- u32 regValue;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:347: inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-348-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-365- if (tx_old_hold >= 0) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:366: ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-367- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-376-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:377: ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-378-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-397-#if 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:398: for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-399- if (i >= TOUT_LOOP) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-423- for (;;) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:424: rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-425-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-456-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:457: NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-458- } else {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-464-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c:465: ((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/inca-ip_sw.c-466-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-316- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c:317:static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-318- int option)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-369- /* Accept frames of this address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c:370: port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-371-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-500-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c:501:static int kwgbe_write_hwaddr(struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-502-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-691-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c:692: while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-693- /* Generate Random Private MAC addr if not set */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-699- dev->enetaddr[5] = get_random_hex();
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c:700: eth_setenv_enetaddr(s, dev->enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.c-701- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.h-275-#define KWGBE_RX_FIRST_DESC (1 << 27)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.h:276:#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/kirkwood_egiga.h-277-#define KWGBE_RX_EN_INTERRUPT (1 << 29)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-127-*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c:128:static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-129-static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-142-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c:143:static void smc_set_mac_addr(const unsigned char *addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-144-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-501- /* set smc_mac_addr, and sync it with u-boot globals */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c:502: err = smc_get_ethaddr(bd, dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-503- if (err < 0)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-717-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c:718:static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-719-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-721-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c:722: if (!eth_getenv_enetaddr("ethaddr", v_mac)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-723- /* get ROM mac value if any */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-727- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c:728: eth_setenv_enetaddr("ethaddr", v_mac);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-729- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-730-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c:731: smc_set_mac_addr(v_mac); /* use old function to update smc default */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/lan91c96.c-732- PRINTK("Using MAC Address %pM\n", v_mac);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/macb.c-53-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/macb.c:54:#define barrier() asm volatile("" ::: "memory")
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/macb.c-55-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c-446- volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c:447: eth_getenv_enetaddr("eth1addr", ea);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c-448- fecp1->palr =
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c-451-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c:452: eth_getenv_enetaddr("ethaddr", ea);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c-453- fecp->palr =
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c-458- volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c:459: eth_getenv_enetaddr("ethaddr", ea);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c-460- fecp0->palr =
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c-464-#ifdef CONFIG_SYS_FEC1_IOBASE
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c:465: eth_getenv_enetaddr("eth1addr", ea);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mcffec.c-466- fecp->palr =
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc512x_fec.c-162-/********************************************************************/
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc512x_fec.c:163:static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc512x_fec.c-164-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc512x_fec.c-228-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc512x_fec.c:229: mpc512x_fec_set_hwaddr (fec, dev->enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc512x_fec.c-230- out_be32(&fec->eth->gaddr1, 0x00000000);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc5xxx_fec.c-184-/********************************************************************/
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc5xxx_fec.c:185:static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc5xxx_fec.c-186-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc5xxx_fec.c-321- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc5xxx_fec.c:322: mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc5xxx_fec.c-323-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc5xxx_fec.c-935- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc5xxx_fec.c:936: mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/mpc5xxx_fec.c-937- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-31-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:32:static void na_get_mac_addr (void)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-33-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-39-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:40: p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:41: p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:42: p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-43-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-59- mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:60: SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-61- /* Write value */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:62: SET_EADDR (NETARM_ETH_MII_WRITE, value);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-63- na_mii_poll_busy ();
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-71- mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:72: SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-73- /* do one management cycle */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:74: SET_EADDR (NETARM_ETH_MII_CMD,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:75: GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-76- na_mii_poll_busy ();
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-77- /* Return read value */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:78: val = GET_EADDR (NETARM_ETH_MII_READ);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-79- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-86- while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:87: if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-88- return 1;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-167-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:168: na_get_mac_addr ();
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-169- pt = na_mii_identify_phy ();
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-182- /* set the PCS reg */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:183: SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M |
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-184- NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-195- Do not enable special test modes. */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:196: SET_EADDR (NETARM_ETH_STL_CFG,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-197- (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN));
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-202- Gap Timer Register should be set to 0x00000C12 for the MII PHY. */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:203: SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:204: SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-205-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-210- NOTE: Multicast addressing is NOT enabled here currently. */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:211: SET_EADDR (NETARM_ETH_MAC_CFG,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-212- (NETARM_ETH_MACC_CRCEN |
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-213- NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:214: SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-215-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-216- /* enable fifos */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:217: SET_EADDR (NETARM_ETH_GEN_CTRL,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-218- (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX));
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-231-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:232: SET_EADDR (NETARM_ETH_GEN_CTRL, 0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-233-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-244- /* RXBR is 1, data block was received */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:245: if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-246- return 0;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-248- /* get status register and the length of received block */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:249: rxstatus = GET_EADDR (NETARM_ETH_RX_STAT);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-250- rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-255- /* clear RXBR to make fifo available */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:256: SET_EADDR (NETARM_ETH_GEN_STAT,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:257: GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-258-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-262- Fifo becomes readable. */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:263: SET_EADDR (NETARM_ETH_GEN_STAT,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:264: GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-265-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-270- for (i = 0; i < rxlen / 4; i++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:271: *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-272- addr++;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-274-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:275: if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-276- /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-277- lastrxlen =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:278: (GET_EADDR (NETARM_ETH_GEN_STAT) &
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-279- NETARM_ETH_GST_RXFDB) >> 28;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:280: *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-281- switch (lastrxlen) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-330- for (i = 0; i < length32; i++)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:331: SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-332-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-334- starts the transmission */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:335: SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-336-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-341- while (i < 50000) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c:342: if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.c-343- == NETARM_ETH_TXSTAT_TXOK)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.h-26-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.h:27:#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.h:28:#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE))
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netarm_eth.h-29-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netconsole.c-150-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netconsole.c:151: nc_ip = getenv_IPaddr ("ncip");
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netconsole.c-152- if (!nc_ip)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netconsole.c-158-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netconsole.c:159: our_ip = getenv_IPaddr ("ipaddr");
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netconsole.c:160: netmask = getenv_IPaddr ("netmask");
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/netconsole.c-161-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-144-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:145: *get_eth_reg_addr(NS7520_ETH_SA1) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-146- aucMACAddr[5] << 8 | aucMACAddr[4];
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:147: *get_eth_reg_addr(NS7520_ETH_SA2) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-148- aucMACAddr[3] << 8 | aucMACAddr[2];
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:149: *get_eth_reg_addr(NS7520_ETH_SA3) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-150- aucMACAddr[1] << 8 | aucMACAddr[0];
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-153-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:154: *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:155: *get_eth_reg_addr(NS7520_ETH_SUPP) = NS7520_ETH_SUPP_JABBER;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:156: *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-157-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-158- /* the linux kernel may give packets < 60 bytes, for example arp */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:159: *get_eth_reg_addr(NS7520_ETH_MAC2) = NS7520_ETH_MAC2_CRCEN |
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-160- NS7520_ETH_MAC2_PADEN | NS7520_ETH_MAC2_HUGE;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-163- /* Based on NS7520 errata documentation */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:164: *get_eth_reg_addr(NS7520_ETH_SAFR) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-165- NS7520_ETH_SAFR_BROAD | NS7520_ETH_SAFR_PRM;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-167- /* enable receive and transmit FIFO, use 10/100 Mbps MII */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:168: *get_eth_reg_addr(NS7520_ETH_EGCR) |=
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-169- NS7520_ETH_EGCR_ETXWM_75 |
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-211-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:212: while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-213- NS7520_ETH_EGSR_TXREGE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-218- for (i = 0; i < length32; i++)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:219: *get_eth_reg_addr(NS7520_ETH_FIFO) = pa32[i];
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-220-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-222- starts the transmission */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:223: *get_eth_reg_addr(NS7520_ETH_FIFOL) = lastp;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-224-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-225- /* Wait for it to be done */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:226: while ((*get_eth_reg_addr(NS7520_ETH_EGSR) & NS7520_ETH_EGSR_TXBC)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-227- == 0) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-228- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:229: status = (*get_eth_reg_addr(NS7520_ETH_ETSR));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:230: *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_TXBC; /* Clear it now */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-231-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-238- printf("Late collision error, %d collisions.\n",
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:239: (*get_eth_reg_addr(NS7520_ETH_ETSR)) &
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-240- NS7520_ETH_ETSR_TXCOLC);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-242- printf("Excessive collisions: %d\n",
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:243: (*get_eth_reg_addr(NS7520_ETH_ETSR)) &
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-244- NS7520_ETH_ETSR_TXCOLC);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-274- /* If RXBR is 1, data block was received */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:275: while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-276- NS7520_ETH_EGSR_RXBR) == NS7520_ETH_EGSR_RXBR) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-278- /* get status register and the length of received block */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:279: rxstatus = *get_eth_reg_addr(NS7520_ETH_ERSR);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-280- rxlen = (rxstatus & NS7520_ETH_ERSR_RXSIZE) >> 16;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-282- /* clear RXBR to make fifo available */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:283: *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_RXBR;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-284-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-286- printf("Receive overrun, resetting FIFO.\n");
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:287: *get_eth_reg_addr(NS7520_ETH_EGCR) &=
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-288- ~NS7520_ETH_EGCR_ERX;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-289- udelay(20);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:290: *get_eth_reg_addr(NS7520_ETH_EGCR) |=
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-291- NS7520_ETH_EGCR_ERX;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-302- for (i = 0; i < rxlen / 4; i++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:303: *addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-304- addr++;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-306-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:307: if ((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-308- NS7520_ETH_EGSR_RXREGR) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-310- lastrxlen =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:311: ((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-312- NS7520_ETH_EGSR_RXFDB_MA) >> 28;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:313: *addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-314- switch (lastrxlen) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-344-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:345: *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_RXEN;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:346: *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~(NS7520_ETH_EGCR_ERX |
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-347- NS7520_ETH_EGCR_ERXDMA |
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-365- /* Reset important registers */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:366: *get_eth_reg_addr(NS7520_ETH_EGCR) = 0; /* Null it out! */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:367: *get_eth_reg_addr(NS7520_ETH_MAC1) &= NS7520_ETH_MAC1_SRST;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:368: *get_eth_reg_addr(NS7520_ETH_MAC2) = 0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-369- /* Reset MAC */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:370: *get_eth_reg_addr(NS7520_ETH_EGCR) |= NS7520_ETH_EGCR_MAC_RES;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-371- udelay(5);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:372: *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~NS7520_ETH_EGCR_MAC_RES;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-373-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-375-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:376: *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_SRST;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-377-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-385-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:386: *get_eth_reg_addr(NS7520_ETH_MCFG) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-387- ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-404- /* now take the highest MDIO clock possible after detection */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:405: *get_eth_reg_addr(NS7520_ETH_MCFG) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-406- ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-483-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:484: unEGCR = *get_eth_reg_addr(NS7520_ETH_EGCR);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:485: unMAC2 = *get_eth_reg_addr(NS7520_ETH_MAC2);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-486- unIPGT =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:487: *get_eth_reg_addr(NS7520_ETH_IPGT) & ~NS7520_ETH_IPGT_IPGT;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-488-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-498-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:499: *get_eth_reg_addr(NS7520_ETH_MAC2) = unMAC2;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:500: *get_eth_reg_addr(NS7520_ETH_EGCR) = unEGCR;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:501: *get_eth_reg_addr(NS7520_ETH_IPGT) = unIPGT;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-502-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-623- /* write MII register to be read */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:624: *get_eth_reg_addr(NS7520_ETH_MADR) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-625- CONFIG_PHY_ADDR << 8 | uiRegister;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-626-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:627: *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-628-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-633-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:634: *get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-635-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:636: return (unsigned short) (*get_eth_reg_addr(NS7520_ETH_MRDD));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-637-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-652- /* write MII register to be written */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:653: *get_eth_reg_addr(NS7520_ETH_MADR) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-654- CONFIG_PHY_ADDR << 8 | uiRegister;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-655-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:656: *get_eth_reg_addr(NS7520_ETH_MWTD) = uiData;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-657-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-730-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:731: while (((*get_eth_reg_addr(NS7520_ETH_MIND) & NS7520_ETH_MIND_BUSY)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-732- == NS7520_ETH_MIND_BUSY) && unTimeout)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-787- /* write MII register to be read */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:788: *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-789-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:790: *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-791-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-796-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:797: *get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-798-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:799: *value = (*get_eth_reg_addr(NS7520_ETH_MRDD));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-800- ret = MII_STATUS_SUCCESS;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-826- /* write MII register to be written */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:827: *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-828-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c:829: *get_eth_reg_addr(NS7520_ETH_MWTD) = value;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns7520_eth.c-830-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-167-static tx_buffer_desc_t* pTxBufferDesc =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:168: (tx_buffer_desc_t*) get_eth_reg_addr( NS9750_ETH_TXBD );
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-169-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-205-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:206: *get_eth_reg_addr (NS9750_ETH_SA1) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-207- aucMACAddr[5] << 8 | aucMACAddr[4];
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:208: *get_eth_reg_addr (NS9750_ETH_SA2) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-209- aucMACAddr[3] << 8 | aucMACAddr[2];
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:210: *get_eth_reg_addr (NS9750_ETH_SA3) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-211- aucMACAddr[1] << 8 | aucMACAddr[0];
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-214-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:215: *get_eth_reg_addr (NS9750_ETH_MAC1) = NS9750_ETH_MAC1_RXEN;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-216-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-217- /* the linux kernel may give packets < 60 bytes, for example arp */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:218: *get_eth_reg_addr (NS9750_ETH_MAC2) = NS9750_ETH_MAC2_CRCEN |
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-219- NS9750_ETH_MAC2_PADEN | NS9750_ETH_MAC2_HUGE;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-221- /* enable receive and transmit FIFO, use 10/100 Mbps MII */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:222: *get_eth_reg_addr (NS9750_ETH_EGCR1) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-223- NS9750_ETH_EGCR1_ETXWM |
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-244-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:245: *get_eth_reg_addr (NS9750_ETH_RXAPTR) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-246- (unsigned int) &aRxBufferDesc[0];
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-248- /* [1] Tab. 221 states less than 5us */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:249: *get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_ERXINIT;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-250- while (!
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:251: (*get_eth_reg_addr (NS9750_ETH_EGSR) & NS9750_ETH_EGSR_RXINIT))
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-252- /* wait for finish */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-255- /* @TODO do we need to clear RXINIT? */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:256: *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_ERXINIT;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-257-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:258: *get_eth_reg_addr (NS9750_ETH_RXFREE) = 0x1;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-259-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-275- /* clear old status values */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:276: *get_eth_reg_addr (NS9750_ETH_EINTR) &=
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:277: *get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_TX_MA;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-278-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-286- /* pTxBufferDesc is the first possible buffer descriptor */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:287: *get_eth_reg_addr (NS9750_ETH_TXPTR) = 0x0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-288-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-290-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:291: *get_eth_reg_addr (NS9750_ETH_EGCR2) &= ~NS9750_ETH_EGCR2_TCLER;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:292: *get_eth_reg_addr (NS9750_ETH_EGCR2) |= NS9750_ETH_EGCR2_TCLER;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-293-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-298- while (!
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:299: (*get_eth_reg_addr (NS9750_ETH_EINTR) &
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-300- (NS9750_ETH_EINTR_TXDONE | NS9750_ETH_EINTR_TXERR))) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-324- unStatus =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:325: *get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_RX_MA;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-326-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-336- /* acknowledge status register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:337: *get_eth_reg_addr (NS9750_ETH_EINTR) = unStatus;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-338-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-342- /* Buffer A descriptor available again */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:343: *get_eth_reg_addr (NS9750_ETH_RXFREE) |= 0x1;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-344-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-362-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:363: *get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_RXEN;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:364: *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~(NS9750_ETH_EGCR1_ERX |
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-365- NS9750_ETH_EGCR1_ERXDMA |
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-381- /* Reset MAC */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:382: *get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_MAC_HRST;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-383- udelay (5); /* according to [1], p.322 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:384: *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_MAC_HRST;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-385-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-387-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:388: *get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_SRST;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-389-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-397-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:398: *get_eth_reg_addr (NS9750_ETH_MCFG) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-399- ns9750_mii_get_clock_divisor (nPhyMaxMdioClock);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-419- /* now take the highest MDIO clock possible after detection */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:420: *get_eth_reg_addr (NS9750_ETH_MCFG) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-421- ns9750_mii_get_clock_divisor (nPhyMaxMdioClock);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-540-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:541: unEGCR = *get_eth_reg_addr (NS9750_ETH_EGCR1);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:542: unMAC2 = *get_eth_reg_addr (NS9750_ETH_MAC2);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:543: unIPGT = *get_eth_reg_addr (NS9750_ETH_IPGT) & ~NS9750_ETH_IPGT_MA;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-544-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-552-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:553: *get_eth_reg_addr (NS9750_ETH_MAC2) = unMAC2;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:554: *get_eth_reg_addr (NS9750_ETH_EGCR1) = unEGCR;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:555: *get_eth_reg_addr (NS9750_ETH_IPGT) = unIPGT;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-556-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-675- /* write MII register to be read */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:676: *get_eth_reg_addr (NS9750_ETH_MADR) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-677- NS9750_ETH_PHY_ADDRESS << 8 | uiRegister;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-678-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:679: *get_eth_reg_addr (NS9750_ETH_MCMD) = NS9750_ETH_MCMD_READ;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-680-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-685-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:686: *get_eth_reg_addr (NS9750_ETH_MCMD) = 0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-687-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:688: return (unsigned short) (*get_eth_reg_addr (NS9750_ETH_MRDD));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-689-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-705- /* write MII register to be written */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:706: *get_eth_reg_addr (NS9750_ETH_MADR) =
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-707- NS9750_ETH_PHY_ADDRESS << 8 | uiRegister;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-708-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:709: *get_eth_reg_addr (NS9750_ETH_MWTD) = uiData;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-710-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-784-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c:785: while (((*get_eth_reg_addr (NS9750_ETH_MIND) & NS9750_ETH_MIND_BUSY)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/ns9750_eth.c-786- == NS9750_ETH_MIND_BUSY) && unTimeout)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-89-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c:90:static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c:91:static unsigned char * plb2800_get_mac_addr(void);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-92-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-132-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c:133: plb2800_set_mac_addr(dev, plb2800_get_mac_addr());
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-134-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-152-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c:153: plb2800_set_mac_addr(dev, dev->enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-154-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-311-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c:312:static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-313-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-374-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c:375:static unsigned char * plb2800_get_mac_addr(void)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/plb2800_eth.c-376-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/rtl8019.c-57-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/rtl8019.c:58:void rtl8019_get_enetaddr (uchar * addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/rtl8019.c-59-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/rtl8019.c-108- put_reg (RTL8019_COMMAND, RTL8019_PAGE1STOP);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/rtl8019.c:109: eth_getenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/rtl8019.c-110- put_reg (RTL8019_PHYSICALADDRESS0, enetaddr[0]);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/rtl8139.c-191-#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/rtl8139.c:192:static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/rtl8139.c-193-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/s3c4510b_eth.c-102- /* store our MAC address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/s3c4510b_eth.c:103: eth_getenv_enetaddr("ethaddr", eth->m_mac);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/s3c4510b_eth.c-104-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/sh_eth.c-665-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/sh_eth.c:666: if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/sh_eth.c-667- puts("Please set MAC address\n");
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/smc91111.h-51-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/smc91111.h:52:void smc_set_mac_addr (const unsigned char *addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/smc91111.h-53-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsec.c-68-#ifdef CONFIG_MCAST_TFTP
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsec.c:69:static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsec.c-70-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsec.c-1949-static int
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsec.c:1950:tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsec.c-1951-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-157-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c:158:#define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-159-#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-249-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c:250:#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-251-#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-474- printf ("TX diagnostics registers\n");
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c:475: reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-476- udelay (1000);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-481- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c:482: reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-483- udelay (1000);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-505- printf ("RX diagnostics registers\n");
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c:506: reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-507- udelay (1000);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-512- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c:513: reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/tsi108_eth.c-514- udelay (1000);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/uli526x.c-193-static void uli526x_disable(struct eth_device *);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/uli526x.c:194:static void set_mac_addr(struct eth_device *);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/uli526x.c-195-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/uli526x.c-315- /* SROM absent, so write MAC address to ID Table */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/uli526x.c:316: set_mac_addr(dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/uli526x.c-317- else { /*Exist SROM*/
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/uli526x.c-968-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/uli526x.c:969:static void set_mac_addr(struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/uli526x.c-970-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/xilinx_emaclite.c-52-/* define for programming the MAC address into the EMAC Lite */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/xilinx_emaclite.c:53:#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/xilinx_emaclite.c-54-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/xilinx_emaclite.c-149-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/xilinx_emaclite.c:150: if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/xilinx_emaclite.c-151- memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/xilinx_emaclite.c:152: eth_setenv_enetaddr("ethaddr", enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/net/xilinx_emaclite.c-153- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/qe.c-83-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/qe.c:84:void *qe_muram_addr(uint offset)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/qe.c-85-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/qe.h-286-uint qe_muram_alloc(uint size, uint align);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/qe.h:287:void *qe_muram_addr(uint offset);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/qe.h-288-int qe_get_snum(void);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uccf.c-206-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uccf.c:207:static uint ucc_get_reg_baseaddr(int ucc_num)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uccf.c-208-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uccf.c-295- uccf->uf_info = uf_info;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uccf.c:296: uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uccf.c-297-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-742- uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c:743: qe_muram_addr(uec->tx_glbl_pram_offset);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-744-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-757- uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c:758: qe_muram_addr(uec->send_q_mem_reg_offset);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-759- out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-794- uec->p_thread_data_tx = (uec_thread_data_tx_t *)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c:795: qe_muram_addr(uec->thread_dat_tx_offset);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-796- out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-808- uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c:809: qe_muram_addr(uec->rx_glbl_pram_offset);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-810-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-827- uec->p_thread_data_rx = (uec_thread_data_rx_t *)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c:828: qe_muram_addr(uec->thread_dat_rx_offset);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-829- out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-852- uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c:853: qe_muram_addr(uec->rx_bd_qs_tbl_offset);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-854-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-913- uec->p_init_enet_param = (uec_init_cmd_pram_t *)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c:914: qe_muram_addr(uec->init_enet_param_offset);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec.c-915-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec_phy.c-55- * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec_phy.c:56: * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/qe/uec_phy.c-57- * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/serial/s3c64xx.c-40-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/serial/s3c64xx.c:41:#define barrier() asm volatile("" ::: "memory")
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/serial/s3c64xx.c-42-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/serial/serial_ks8695.c-44-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/serial/serial_ks8695.c:45:#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/serial/serial_ks8695.c-46-#define KS8695_UART_CLK 25000000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/gadget/omap1510_udc.c-1207-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/gadget/omap1510_udc.c:1208: /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/gadget/omap1510_udc.c-1209- int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/gadget/omap1510_udc.c-1241-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/gadget/omap1510_udc.c:1242: /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/gadget/omap1510_udc.c-1243- int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/gadget/omap1510_udc.c-1369-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/gadget/omap1510_udc.c:1370: /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/gadget/omap1510_udc.c-1371- int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c-135-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c:136:static inline struct QH *qh_addr(struct QH *qh)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c-137-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c-150- while (1) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c:151: flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c-152- if ((u32)qh & QH_LINK_TYPE_QH)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c-153- break;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c:154: qh = qh_addr(qh);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c-155- qh = (struct QH *)qh->qh_link;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c-156- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c:157: qh = qh_addr(qh);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/ehci-hcd.c-158-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-354-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h:355:static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-356-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-414-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h:415: isp116x_write_addr(isp116x, reg);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-416- return isp116x_read_data16(isp116x);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-420-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h:421: isp116x_write_addr(isp116x, reg);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-422- return isp116x_read_data32(isp116x);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-427-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h:428: isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-429- isp116x_write_data16(isp116x, (u16) (val & 0xffff));
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-434-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h:435: isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x.h-436- isp116x_write_data32(isp116x, (u32) val);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x-hcd.c-469- isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x-hcd.c:470: isp116x_write_addr(isp116x, HCATLPORT | ISP116x_WRITE_OFFSET);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x-hcd.c-471-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x-hcd.c-501- isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x-hcd.c:502: isp116x_write_addr(isp116x, HCATLPORT);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/isp116x-hcd.c-503-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597.h-563-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597.h:564:#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597.h:565:#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597.h:566:#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597.h:567:#define get_devadd_addr(address) (DEVADD0 + address * 2)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597.h-568-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-65- u16 val, usbspd, upphub, hubport;
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:66: unsigned long devadd_reg = get_devadd_addr(r8a66597_address);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-67-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-200- for (i = 0; i <= 10; i++)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:201: r8a66597_write(r8a66597, 0, get_devadd_addr(i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-202- for (i = 1; i <= 5; i++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:203: r8a66597_write(r8a66597, 0, get_pipetre_addr(i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:204: r8a66597_write(r8a66597, 0, get_pipetrn_addr(i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-205- }
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-206- for (i = 1; i < R8A66597_MAX_NUM_PIPE; i++) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:207: r8a66597_write(r8a66597, 0, get_pipectr_addr(i));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-208- r8a66597_write(r8a66597, i, PIPESEL);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-255-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:256: r8a66597_bset(r8a66597, ACLRM, get_pipectr_addr(pipenum));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:257: r8a66597_bclr(r8a66597, ACLRM, get_pipectr_addr(pipenum));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-258- r8a66597_write(r8a66597, pipenum, PIPESEL);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-271- r8a66597_write(r8a66597, 0, PIPEPERI);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:272: r8a66597_write(r8a66597, SQCLR, get_pipectr_addr(pipenum));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-273-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-347- r8a66597_mdfy(r8a66597, PID_BUF, PID,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:348: get_pipectr_addr(BULK_OUT_PIPENUM));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-349-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-356- r8a66597_mdfy(r8a66597, PID_NAK, PID,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:357: get_pipectr_addr(BULK_OUT_PIPENUM));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-358-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-377- r8a66597_mdfy(r8a66597, PID_NAK, PID,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:378: get_pipectr_addr(pipenum));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-379- r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-380-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:381: r8a66597_write(r8a66597, TRCLR, get_pipetre_addr(pipenum));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-382- r8a66597_write(r8a66597,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-383- (transfer_len + maxpacket - 1) / maxpacket,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:384: get_pipetrn_addr(pipenum));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:385: r8a66597_bset(r8a66597, TRENB, get_pipetre_addr(pipenum));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-386-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-387- r8a66597_mdfy(r8a66597, PID_BUF, PID,
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c:388: get_pipectr_addr(pipenum));
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/host/r8a66597-hcd.c-389- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/musb/davinci.h-64-/* Integrated highspeed/otg PHY */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/musb/davinci.h:65:#define USBPHY_CTL_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x34)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/usb/musb/davinci.h-66-#define USBPHY_PHY24MHZ (1 << 13)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c-202-#define IPU_TASKS_STAT (0x1C + IPU_BASE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c:203:#define IPU_IMA_ADDR (0x20 + IPU_BASE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c-204-#define IPU_IMA_DATA (0x24 + IPU_BASE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c-617-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c:618:static uint32_t dma_param_addr(enum ipu_channel channel)
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c-619-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c-647-
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c:648: ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c-649-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c-703- /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c:704: reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
qemu-5.1+dfsg/roms/u-boot-sam460ex/drivers/video/mx3fb.c-705- reg_write((u32)buf, IPU_IMA_DATA);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/api/Makefile-64-
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/api/Makefile:65:gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/api/Makefile-66-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/82559_eeprom.c-244-
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/82559_eeprom.c:245:static unsigned char *gethwaddr(char *in, unsigned char *out)
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/82559_eeprom.c-246-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/82559_eeprom.c-320-
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/82559_eeprom.c:321: eth_addr = gethwaddr(argv[1], buf);
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/82559_eeprom.c-322- if (NULL == eth_addr) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/Makefile-70-
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/Makefile:71:gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/Makefile-72-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc91111_eeprom.c-48-int read_eeprom_reg (struct eth_device *dev, int reg);
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc91111_eeprom.c:49:void print_macaddr (struct eth_device *dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc91111_eeprom.c-50-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc91111_eeprom.c-236- case ('P'):
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc91111_eeprom.c:237: print_macaddr (&dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc91111_eeprom.c-238- break;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc91111_eeprom.c-265-
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc91111_eeprom.c:266:void print_macaddr (struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc91111_eeprom.c-267-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc911x_eeprom.c-209- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc911x_eeprom.c:210:static void print_macaddr(struct eth_device *dev)
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc911x_eeprom.c-211-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc911x_eeprom.c-368- case 'C': copy_from_eeprom(&dev); break;
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc911x_eeprom.c:369: case 'P': print_macaddr(&dev); break;
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/smc911x_eeprom.c-370- unknown_cmd:
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-18-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:19: asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-20-" .globl " #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-31-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:32: asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-33-" .globl " #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-45-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:46: asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-47-" .globl " #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-60-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:61: asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-62-" .globl " #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-72-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:73: asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-74-" .globl " #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-88-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:89: asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-90-" .globl " #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-103-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:104: asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-105-" .globl " #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-116-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:117: asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-118-" .globl _" #x "\n_" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-128-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:129: asm volatile( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-130- " .globl\t" #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-141-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:142: asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-143- " .align 2\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-159-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c:160: asm volatile( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/stubs.c-161-" .globl\t" #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/test_burst.c-241-
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/test_burst.c:242: asm volatile("mfmsr %0" : "=r" (msr) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/test_burst.c-243-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/timer.c-42-
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/timer.c:43: asm volatile("mfmsr %0" : "=r" (msr) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/timer.c-44- return msr;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/timer.c-48-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/timer.c:49: asm volatile("mtmsr %0" : : "r" (msr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/timer.c-50-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-16-#define LABEL(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c:17:asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-18-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-20-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c:21:asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-22-" .globl mon_" #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-29-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c:30:asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-31-" .globl mon_" #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-39-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c:40:asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-41-" .globl mon_" #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-47-#define EXPORT_FUNC(x) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c:48:asm volatile ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/examples/standalone/x86-testapp.c-49-" .globl mon_" #x "\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/4xx_i2c.h-45- defined(CONFIG_460EX) || defined(CONFIG_460GT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/4xx_i2c.h:46:#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/4xx_i2c.h-47-#elif defined(CONFIG_440) || defined(CONFIG_405EX)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/4xx_i2c.h-48-/* all remaining 440 variants */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/4xx_i2c.h:49:#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/4xx_i2c.h-50-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/4xx_i2c.h-51-/* all 405 variants */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/4xx_i2c.h:52:#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/4xx_i2c.h-53-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-91- unsigned long msr;
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h:92: asm volatile("mfmsr %0" : "=r" (msr) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-93- return msr;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-97-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h:98: asm volatile("mtmsr %0" : : "r" (msr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-99-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-103- unsigned long hid0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h:104: asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-105- return hid0;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-110- unsigned long hid1;
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h:111: asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-112- return hid1;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-116-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h:117: asm volatile("mtspr 1008, %0" : : "r" (hid0));
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-118-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-121-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h:122: asm volatile("mtspr 1009, %0" : : "r" (hid1));
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/74xx_7xx.h-123-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ambapp.h-138-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ambapp.h:139:#define AMBA_TYPE_AHBIO_ADDR(addr) (LEON3_IO_AREA | ((addr) >> 12))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ambapp.h-140-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/bedbug/regs.h-173-({ unsigned long __value = (val); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/bedbug/regs.h:174: asm volatile( str : : "r" (__value)); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/bedbug/regs.h-175- __value; })
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/bedbug/regs.h-178-({ unsigned long __value; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/bedbug/regs.h:179: asm volatile( str : "=r" (__value) : ); \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/bedbug/regs.h-180- __value; })
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/clps7111.h-37-#define PDDR (0x0003)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/clps7111.h:38:#define PADDR (0x0040)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/clps7111.h-39-#define PBDDR (0x0041)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/clps7111.h-73-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/clps7111.h:74:#define FBADDR (0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/clps7111.h-75-#define SYSCON2 (0x1100)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/common.h-415-void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn));
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/common.h:416:ulong get_endaddr (void);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/common.h-417-void trap_init (ulong);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/common.h-628-#include <net.h>
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/common.h:629:static inline IPaddr_t getenv_IPaddr (char *var)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/common.h-630-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/commproc.h-40-#define CPM_CR_RESTART_TX ((ushort)0x0006)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/commproc.h:41:#define CPM_CR_SET_GADDR ((ushort)0x0008)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/commproc.h-42-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/commproc.h-90-#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/commproc.h:91:#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/commproc.h-92-#else
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/acadia.h-127-#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/acadia.h:128:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/acadia.h-129-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/acadia.h-203-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/acadia.h:204:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/acadia.h-205-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux1.h-203-#define CONFIG_ENV_SIZE 0x2000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux1.h:204:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux1.h-205-#define CONFIG_SYS_USE_PPCENV 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux2.h-180-#define CONFIG_ENV_SIZE 0x2000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux2.h:181:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux2.h-182-#define CONFIG_SYS_USE_PPCENV 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux3.h-180-#define CONFIG_ENV_SIZE 0x2000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux3.h:181:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux3.h-182-#define CONFIG_SYS_USE_PPCENV 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux4.h-177-#define CONFIG_ENV_SIZE 0x1000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux4.h:178:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/actux4.h-179-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Adder.h-152-#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Adder.h:153:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Adder.h-154-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aev.h-235-#if !defined(CONFIG_SYS_LOWBOOT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aev.h:236:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aev.h-237-#else /* CONFIG_SYS_LOWBOOT */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aev.h:238:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aev.h-239-#endif /* CONFIG_SYS_LOWBOOT */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/afeb9260.h-148-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/afeb9260.h:149:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/afeb9260.h-150-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-209-#if defined (CONFIG_SYS_AMD_BOOT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h:210:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-211-#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-212-#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h:213:#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-214-#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-216-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h:217:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-218-#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-219-#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h:220:#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-221-#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-247-/* Use SRAM until RAM will be available */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h:248:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Alaska8220.h-249-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/alpr.h-56-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/alpr.h:57:#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/alpr.h-58-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/alpr.h-68-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/alpr.h:69:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/alpr.h-70-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/alpr.h-98-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/alpr.h:99:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/alpr.h-100-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/am3517_evm.h-209-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/am3517_evm.h:210:#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/am3517_evm.h-211- /* address */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/AmigaOneG3SE.h-287-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/AmigaOneG3SE.h:288:#define CONFIG_SYS_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/AmigaOneG3SE.h-289-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1F0
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ap325rxa.h-105-/* default load address for scripts ?!? */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ap325rxa.h:106:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ap325rxa.h-107-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ap325rxa.h-166-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ap325rxa.h:167:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ap325rxa.h-168-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/APC405.h-426-#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/APC405.h:427:#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/APC405.h-428-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/apollon.h-200-/* default load address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/apollon.h:201:#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/apollon.h-202-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aria.h-69-#define CONFIG_SYS_IMMR 0x80000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aria.h:70:#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aria.h-71-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aria.h-412-/* This has to be a multiple of the flash sector size */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aria.h:413:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/aria.h-414- CONFIG_SYS_MONITOR_LEN)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/armadillo.h-150-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/armadillo.h:151:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/armadillo.h-152-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/assabet.h-168-#define CONFIG_ENV_IN_OWN_SECTOR 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/assabet.h:169:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/assabet.h-170-#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91cap9adk.h-170-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91cap9adk.h:171:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91cap9adk.h-172-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91cap9adk.h-185-#define CONFIG_ENV_OFFSET 0x4000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91cap9adk.h:186:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91cap9adk.h-187-#define CONFIG_ENV_SIZE 0x4000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200dk.h-161-#define CONFIG_ENV_OFFSET 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200dk.h:162:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200dk.h-163-#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200dk.h-166-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200dk.h:167:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200dk.h-168-#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200dk.h-169-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200dk.h:170:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200dk.h-171-#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200ek.h-212- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200ek.h:213:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91rm9200ek.h-214-#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9260ek.h-162-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9260ek.h:163:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9260ek.h-164-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9260ek.h-176-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9260ek.h:177:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9260ek.h-178-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9261ek.h-180-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9261ek.h:181:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9261ek.h-182-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9261ek.h-194-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9261ek.h:195:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9261ek.h-196-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9263ek.h-130-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9263ek.h:131:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9263ek.h-132-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9263ek.h-303-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9263ek.h:304:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9263ek.h-305-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9m10g45ek.h-176-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9m10g45ek.h:177:#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9m10g45ek.h-178-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9rlek.h-141-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9rlek.h:142:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/at91sam9rlek.h-143-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atc.h-273-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atc.h:274:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atc.h-275-# define CONFIG_ENV_SIZE 0x10000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atngw100.h-157-#define CONFIG_ENV_SIZE 65536
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atngw100.h:158:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atngw100.h-159-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atngw100.h:160:#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atngw100.h-161-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atngw100.h-165-/* Allow 4MB for the kernel run-time image */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atngw100.h:166:#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atngw100.h-167-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1002.h-181-#define CONFIG_ENV_SIZE 65536
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1002.h:182:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1002.h-183-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1002.h:184:#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1002.h-185-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1002.h-189-/* Allow 4MB for the kernel run-time image */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1002.h:190:#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1002.h-191-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1003.h-164-#define CONFIG_ENV_SIZE 65536
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1003.h:165:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1003.h-166-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1003.h:167:#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1003.h-168-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1003.h-171-/* Allow 4MB for the kernel run-time image */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1003.h:172:#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1003.h-173-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1004.h-164-#define CONFIG_ENV_SIZE 65536
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1004.h:165:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1004.h-166-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1004.h:167:#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1004.h-168-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1004.h-171-/* Allow 2MB for the kernel run-time image */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1004.h:172:#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1004.h-173-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1006.h-181-#define CONFIG_ENV_SIZE 65536
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1006.h:182:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1006.h-183-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1006.h:184:#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1006.h-185-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1006.h-189-/* Allow 4MB for the kernel run-time image */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1006.h:190:#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/atstk1006.h-191-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ATUM8548.h-93-#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ATUM8548.h:94:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ATUM8548.h:95:#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ATUM8548.h:96:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ATUM8548.h-97-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ATUM8548.h-329-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ATUM8548.h:330:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ATUM8548.h-331-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/BAB7xx.h-252- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/BAB7xx.h:253:#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x800)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/BAB7xx.h:254:#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x400)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/BAB7xx.h-255-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bamboo.h-130-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bamboo.h:131:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bamboo.h-132-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bamboo.h-228-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bamboo.h:229:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bamboo.h-230-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/barco.h-148-#define CONFIG_SYS_RAMBOOT 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/barco.h:149:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/barco.h-150-#define CONFIG_SYS_INIT_RAM_END 0x10000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/BC3450.h-338-#if !defined(CONFIG_SYS_LOWBOOT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/BC3450.h:339:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/BC3450.h-340-#else /* CONFIG_SYS_LOWBOOT */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/BC3450.h:341:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/BC3450.h-342-#endif /* CONFIG_SYS_LOWBOOT */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf518f-ezbrd.h-107-#define CONFIG_ENV_OFFSET 0x4000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf518f-ezbrd.h:108:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf518f-ezbrd.h-109-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf526-ezbrd.h-124-#define CONFIG_ENV_OFFSET 0x4000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf526-ezbrd.h:125:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf526-ezbrd.h-126-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf527-ezkit.h-128-#define CONFIG_ENV_OFFSET 0x4000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf527-ezkit.h:129:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf527-ezkit.h-130-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf533-stamp.h-112-#define CONFIG_ENV_OFFSET 0x4000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf533-stamp.h:113:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf533-stamp.h-114-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf537-stamp.h-108-#define CONFIG_ENV_OFFSET 0x4000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf537-stamp.h:109:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf537-stamp.h-110-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf538f-ezkit.h-105-#define CONFIG_ENV_OFFSET 0x4000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf538f-ezkit.h:106:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bf538f-ezkit.h-107-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bubinga.h-198-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bubinga.h:199:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/bubinga.h-200-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/c2mon.h-274- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/c2mon.h:275:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/c2mon.h-276-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/c2mon.h:277:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/c2mon.h-278-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/c2mon.h:279:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/c2mon.h-280-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/c2mon.h:281:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/c2mon.h-282-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-91-#define CONFIG_SYS_FPGA_BASE 0xE1000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h:92:#define CONFIG_SYS_CPLD_ADDR (CONFIG_SYS_FPGA_BASE + 0x00080000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-93-#define CONFIG_SYS_CPLD_DATA (CONFIG_SYS_FPGA_BASE + 0x00080002)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-226-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h:227:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-228-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-327-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h:328:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-329-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-664-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h:665:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h:666:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h:667:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-668-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-738-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h:739:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h:740:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h:741:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/canyonlands.h-742-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cerf250.h-223-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cerf250.h:224:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cerf250.h-225-#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cm5200.h-272-#define CONFIG_ENV_SECT_SIZE 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cm5200.h:273:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cm5200.h-274-/* Configuration of redundant environment */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cmi_mpc5xx.h-128- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cmi_mpc5xx.h:129:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cmi_mpc5xx.h-130-#define CONFIG_SYS_INIT_RAM_END (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cogent_mpc8xx.h-282- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cogent_mpc8xx.h:283:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cogent_mpc8xx.h-284-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cogent_mpc8xx.h:285:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cogent_mpc8xx.h-286-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cogent_mpc8xx.h:287:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cogent_mpc8xx.h-288-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cogent_mpc8xx.h:289:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cogent_mpc8xx.h-290-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPC45.h-327-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPC45.h:328:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPC45.h-329-#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cpci5200.h-201-#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cpci5200.h:202:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cpci5200.h-203-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPCI750.h-579-#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPCI750.h:580:/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPCI750.h-581-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPU86.h-318-#ifdef CONFIG_BOOT_ROM
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPU86.h:319:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPU86.h-320-# define CONFIG_ENV_SIZE 0x10000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPU87.h-339-#ifdef CONFIG_BOOT_ROM
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPU87.h:340:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/CPU87.h-341-# define CONFIG_ENV_SIZE 0x10000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cpuat91.h-167-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cpuat91.h:168:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/cpuat91.h-169-#define CONFIG_ENV_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/csb226.h-495-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/csb226.h:496:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/csb226.h-497- /* Addr of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/csb637.h-170-#define CONFIG_ENV_OFFSET 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/csb637.h:171:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/csb637.h-172-#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/csb637.h-174-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/csb637.h:175:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/csb637.h-176-#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da830evm.h-171-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da830evm.h:172:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + 0x700000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da830evm.h-173-#define CONFIG_VERSION_VARIABLE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da830evm.h-184- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da830evm.h:185:#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da830evm.h-186-#define CONFIG_CMDLINE_TAG
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da850evm.h-89-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da850evm.h:90:#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da850evm.h-91-#define CONFIG_VERSION_VARIABLE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da850evm.h-102- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da850evm.h:103:#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/da850evm.h-104-#define CONFIG_CMDLINE_TAG
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DB64360.h-565-#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DB64360.h:566:/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DB64360.h-567-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DB64460.h-503-#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DB64460.h:504:/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DB64460.h-505-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/debris.h-198-#define CONFIG_SYS_RAMBOOT 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/debris.h:199:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/debris.h-200-#define CONFIG_SYS_INIT_RAM_END 0x10000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/delta.h-172-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/delta.h:173:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/delta.h-174-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/devkit8000.h-263-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/devkit8000.h:264:#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/devkit8000.h-265-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/dlvision.h-132-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/dlvision.h:133:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/dlvision.h-134-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/dnp1110.h-160-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/dnp1110.h:161:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xF80000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/dnp1110.h-162-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h-140-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h:141:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h-142-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h-253-#ifndef __ASSEMBLY__
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h:254:int du440_phy_addr(int devnum);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h-255-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h-259-#define CONFIG_MII 1 /* MII PHY management */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h:260:#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h-261-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h-269-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h:270:#define CONFIG_PHY1_ADDR du440_phy_addr(1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/DU440.h-271-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/eb_cpux9k2.h-330-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/eb_cpux9k2.h:331:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/eb_cpux9k2.h-332-#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ebony.h-67-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ebony.h:68:#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ebony.h-69-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ebony.h-122-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ebony.h:123:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ebony.h-124-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ebony.h-143-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ebony.h:144:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ebony.h-145-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/edb93xx.h-214-/* Default load address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/edb93xx.h:215:#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x01000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/edb93xx.h-216-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/edb93xx.h-217-/* Must match kernel config */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/edb93xx.h:218:#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/edb93xx.h-219-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ELPPC.h-225-#define CONFIG_ENV_MAP_ADRS 0xff000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ELPPC.h:226:#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ELPPC.h-227-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/eNET.h-253-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/eNET.h:254:#define PRINTIP asm ("call 0\n" \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/eNET.h-255- "0:\n" \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1C20.h-91-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1C20.h:92:#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1C20.h-93-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1C20.h-155- *----------------------------------------------------------------------*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1C20.h:156:#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1C20.h-157-#define CONFIG_NET_MULTI
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S10.h-89-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S10.h:90:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S10.h-91-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S10.h-149- *----------------------------------------------------------------------*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S10.h:150:#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S10.h-151-#define CONFIG_NET_MULTI
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S40.h-89-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S40.h:90:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S40.h-91-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S40.h-149- *----------------------------------------------------------------------*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S40.h:150:#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP1S40.h-151-#define CONFIG_NET_MULTI
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep7312.h-152-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep7312.h:153:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep7312.h-154-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8248.h-210-#define CONFIG_ENV_SECT_SIZE 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8248.h:211:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8248.h-212-#endif /* CONFIG_ENV_IS_IN_FLASH */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8260.h-479-# ifdef CONFIG_ENV_IN_OWN_SECT
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8260.h:480:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8260.h-481-# define CONFIG_ENV_SECT_SIZE 0x40000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8260.h-482-# else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8260.h:483:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8260.h-484-# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8260.h-488-# define CONFIG_ENV_IS_IN_NVRAM 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8260.h:489:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep8260.h-490-# define CONFIG_ENV_SIZE 0x200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep82xxm.h-212-#define CONFIG_ENV_SECT_SIZE 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep82xxm.h:213:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ep82xxm.h-214-#endif /* CONFIG_ENV_IS_IN_FLASH */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP88x.h-147-#define CONFIG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP88x.h:148:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EP88x.h-149-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ERIC.h-230-#define CONFIG_SYS_NVRAM_REG_BASE_ADDR 0xF0000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ERIC.h:231:#define CONFIG_SYS_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ERIC.h-232-#define CONFIG_SYS_ADC_REG_BASE_ADDR 0xF0100000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ERIC.h-310-#define CONFIG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ERIC.h:311:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ERIC.h:312:/* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE)*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ERIC.h-313-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/espt.h-81-/* U-boot setting */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/espt.h:82:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/espt.h-83-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/espt.h-108-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/espt.h:109:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/espt.h-110-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/espt.h-123-#define CONFIG_SH_ETHER_USE_PORT (1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/espt.h:124:#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/espt.h-125-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ESTEEM192E.h-221- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ESTEEM192E.h:222:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ESTEEM192E.h-223-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ESTEEM192E.h:224:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ESTEEM192E.h-225-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ESTEEM192E.h:226:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ESTEEM192E.h-227-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ESTEEM192E.h:228:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ESTEEM192E.h-229-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ETX094.h-262- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ETX094.h:263:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ETX094.h-264-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ETX094.h:265:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ETX094.h-266-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ETX094.h:267:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ETX094.h-268-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ETX094.h:269:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ETX094.h-270-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/evb4510.h-175-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/evb4510.h:176:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) /* environment start address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/evb4510.h-177-#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EVB64260.h-396-#define CONFIG_ENV_SECT_SIZE 0x10000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EVB64260.h:397:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/EVB64260.h-398-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS823.h-28-#define CONFIG_SYS_FLASH_BASE 0x02800000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS823.h:29:#define BCSR_ADDR ((uint) 0xff010000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS823.h-30-#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS823.h-56-#define CONFIG_VIDEO_SIZE (2*1024*1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS823.h:57:/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS823.h-58-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS850SAR.h-246-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS850SAR.h:247:#define BCSR_ADDR ((uint) 0x02100000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS850SAR.h-248-#define BCSR_SIZE ((uint)(64 * 1024))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS850SAR.h-309-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS850SAR.h:310:#define PCMCIA_MEM_ADDR ((uint)0xff020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FADS850SAR.h-311-#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/favr-32-ezkit.h-178-#define CONFIG_ENV_SIZE 65536
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/favr-32-ezkit.h:179:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/favr-32-ezkit.h-180-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/favr-32-ezkit.h:181:#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/favr-32-ezkit.h-182-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/favr-32-ezkit.h-186-/* Allow 4MB for the kernel run-time image */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/favr-32-ezkit.h:187:#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/favr-32-ezkit.h-188-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS850L.h-309- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS850L.h:310:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS850L.h-311-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS850L.h:312:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS850L.h-313-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS850L.h:314:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS850L.h-315-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS850L.h:316:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS850L.h-317-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS860L.h-309- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS860L.h:310:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS860L.h-311-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS860L.h:312:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS860L.h-313-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS860L.h:314:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS860L.h-315-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS860L.h:316:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/FPS860L.h-317-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/fx12mm.h-52-#define CONFIG_SYS_ENV_OFFSET 0xA0000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/fx12mm.h:53:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/fx12mm.h-54-#define CONFIG_ENV_OVERWRITE 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gcplus.h-183-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gcplus.h:184:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gcplus.h-185-#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gdppc440etx.h-111-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gdppc440etx.h:112:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gdppc440etx.h-113-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gr_cpci_ax2000.h-225-#define CONFIG_ENV_SECT_SIZE 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gr_cpci_ax2000.h:226:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gr_cpci_ax2000.h-227-#define CONFIG_ENV_OVERWRITE 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gr_ep2s60.h-213-#define CONFIG_ENV_SECT_SIZE 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gr_ep2s60.h:214:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gr_ep2s60.h-215-#define CONFIG_ENV_OVERWRITE 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/grsim.h-185-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/grsim.h:186:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/grsim.h-187-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/grsim_leon2.h-182-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/grsim_leon2.h:183:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/grsim_leon2.h-184-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gr_xc3s_1500.h-189-#define CONFIG_ENV_SECT_SIZE 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gr_xc3s_1500.h:190:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gr_xc3s_1500.h-191-#define CONFIG_ENV_OVERWRITE 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/GTH.h-343-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/GTH.h:344:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/GTH.h-345-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/GTH.h:346:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/GTH.h-347-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/GTH.h:348:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/GTH.h-349-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/GTH.h:350:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/GTH.h-351-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gw8260.h-215-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gw8260.h:216:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gw8260.h-217- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gw8260.h-473-#ifdef CONFIG_ENV_IN_OWN_SECT
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gw8260.h:474:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/gw8260.h-475-# define CONFIG_ENV_SECT_SIZE (256 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hammerhead.h-147-#define CONFIG_ENV_SIZE 65536
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hammerhead.h:148:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hammerhead.h-149-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hammerhead.h:150:#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hammerhead.h-151-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hammerhead.h-156-/* Allow 4MB for the kernel run-time image */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hammerhead.h:157:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hammerhead.h-158-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu4.h-130-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu4.h:131:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu4.h-132-#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu4.h-194-#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu4.h:195:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu4.h-196-#undef CONFIG_LOGBUFFER
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu5.h-118-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu5.h:119:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu5.h-120-#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu5.h-216-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu5.h:217:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hcu5.h-218-#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HIDDEN_DRAGON.h-125-#define CONFIG_SYS_RAMBOOT 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HIDDEN_DRAGON.h:126:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HIDDEN_DRAGON.h-127-#define CONFIG_SYS_INIT_RAM_END 0x10000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hmi1001.h-151-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hmi1001.h:152:#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hmi1001.h-153-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HMI10.h-329- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HMI10.h:330:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0100000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HMI10.h-331-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HMI10.h:332:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4100000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HMI10.h-333-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HMI10.h:334:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8100000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HMI10.h-335-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HMI10.h:336:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC100000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/HMI10.h-337-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h-95-# define MDIO_PORT 0 /* Port A */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h:96:# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h-97- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h-116-# define MDIO_PORT 0 /* Port A */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h:117:# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h-118- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h-137-# define MDIO_PORT 0 /* Port A */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h:138:# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h-139- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h-417-#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h:418:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/hymod.h-419-#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IAD210.h-300- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IAD210.h:301:#define PCMCIA_MEM_ADDR ((uint)0xff020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IAD210.h-302-#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-209-#if !defined(CONFIG_SYS_LOWBOOT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h:210:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-211-#else /* CONFIG_SYS_LOWBOOT */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-215-#if defined(CONFIG_SYS_LOWBOOT16)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h:216:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-217-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-222-#if !defined(CONFIG_SYS_LOWBOOT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h:223:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-224-#else /* CONFIG_SYS_LOWBOOT */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-225-#if defined(CONFIG_SYS_LOWBOOT08)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h:226:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-227-#endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-228-#if defined(CONFIG_SYS_LOWBOOT16)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h:229:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IceCube.h-230-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/icon.h-102- CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/icon.h:103:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/icon.h-104-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/icon.h-201-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/icon.h:202:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/icon.h-203-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ICU862.h-317- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ICU862.h:318:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ICU862.h-319-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ICU862.h:320:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ICU862.h-321-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ICU862.h:322:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ICU862.h-323-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ICU862.h:324:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ICU862.h-325-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IDS8247.h-252-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IDS8247.h:253:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IDS8247.h-254-#define CONFIG_ENV_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/impa7.h-154-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/impa7.h:155:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/impa7.h-156-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/imx31_litekit.h-157-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/imx31_litekit.h:158:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/imx31_litekit.h-159-#define CONFIG_ENV_IS_IN_FLASH 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/inka4x0.h-178-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/inka4x0.h:179:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/inka4x0.h-180-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/integratorap.h-178-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/integratorap.h:179:#define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/integratorap.h:180:#define PCI_ENET0_MEMADDR (PCI_MEM_BASE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/integratorap.h-181-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h-148-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h:149:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h-150-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h-227-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h:228:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h-229-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h-415-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h:416:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h:417:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h:418:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/intip.h-419-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ipek01.h-224-#define CONFIG_SYS_FLASH_SIZE 0x01000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ipek01.h:225:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ipek01.h-226- CONFIG_SYS_MONITOR_LEN)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IPHASE4539.h-212-#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IPHASE4539.h:213:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IPHASE4539.h-214-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ISPAN.h-86-#define MDIO_PORT 3 /* Port D */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ISPAN.h:87:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ISPAN.h-88- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ISPAN.h-194-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ISPAN.h:195:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ISPAN.h-196-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVML24.h-308- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVML24.h:309:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVML24.h-310-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVML24.h:311:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVML24.h-312-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVML24.h:313:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVML24.h-314-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVML24.h:315:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVML24.h-316-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVMS8.h-302- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVMS8.h:303:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVMS8.h-304-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVMS8.h:305:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVMS8.h-306-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVMS8.h:307:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVMS8.h-308-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVMS8.h:309:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/IVMS8.h-310-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ixdp425.h-196-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ixdp425.h:197:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ixdp425.h-198-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ixdpg425.h-229-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ixdpg425.h:230:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ixdpg425.h-231-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/jupiter.h-186-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/jupiter.h:187:#define CONFIG_ENV_ADDR (TEXT_BASE + 0x40000) /* third sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/jupiter.h-188-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KAREF.h-65-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KAREF.h:66:#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KAREF.h-67-#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KAREF.h-84-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KAREF.h:85:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KAREF.h-86-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KAREF.h-150-#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KAREF.h:151:#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KAREF.h-152-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/katmai.h-108-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/katmai.h:109:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/katmai.h-110-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/katmai.h-138-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/katmai.h:139:#define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/katmai.h-140-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/katmai.h-235-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/katmai.h:236:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/katmai.h-237-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-86-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h:87:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-88-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h:89:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-90-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-105-# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h:106:# define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-107-#else
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-109-# define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h:110:# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-111-# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-148-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h:149:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-150-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-574-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h:575:{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kilauea.h-576-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kmeter1.h-307-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kmeter1.h:308:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kmeter1.h-309-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kmeter1.h-318-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kmeter1.h:319:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/kmeter1.h-320-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-61-#define CONFIG_SYS_FLASH0_SIZE 0x01000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:62:#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-63-#define CONFIG_SYS_FLASH1_TOP 0xF8000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-64-#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:65:#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-66-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-131-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:132:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-133-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-160-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:161:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-162-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-308-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:309:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-310-#define CONFIG_LOGBUFFER
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-485-/* GPIO Core 0 */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:486:{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:487:{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:488:{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:489:{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:490:{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h:491:{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/korat.h-492-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4K.h-353-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4K.h:354:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4K.h-355-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4K.h:356:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4K.h-357-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4K.h:358:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4K.h-359-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4K.h:360:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4K.h-361-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4X.h-360-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4X.h:361:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4X.h-362-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4X.h:363:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4X.h-364-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4X.h:365:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4X.h-366-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4X.h:367:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/KUP4X.h-368-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lart.h-157-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lart.h:158:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lart.h-159-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/linkstation.h-257-#if 1 /* RAM is available when the first C function is called */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/linkstation.h:258:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/linkstation.h-259-#else
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/logodl.h-295-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/logodl.h:296:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/logodl.h-297-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lpc2292sodimm.h-150-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lpc2292sodimm.h:151:#define CONFIG_ENV_ADDR (0x0 + 0x3C000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lpc2292sodimm.h-152-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lpd7a400.h-114-/* Address and size of Primary Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lpd7a400.h:115:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xFC0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lpd7a400.h-116-#define CONFIG_ENV_SIZE 0x40000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lpd7a404.h-114-/* Address and size of Primary Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lpd7a404.h:115:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xFC0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lpd7a404.h-116-#define CONFIG_ENV_SIZE 0x40000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/luan.h-118-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/luan.h:119:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/luan.h-120-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/luan.h-139-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/luan.h:140:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/luan.h-141-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lubbock.h-129-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lubbock.h:130:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lubbock.h-131-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lubbock.h-240-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lubbock.h:241:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lubbock.h-242-#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-86-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:87:#define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-88- /* unused GPT0 COMP reg */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-94-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:95:#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:96:#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-97-#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-145-#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:146:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-147-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-251-/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:252:#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:253:#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-254-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-540-/* GPIO Core 0 */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:541:{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:542:{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:543:{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:544:{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:545:{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h:546:{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon5.h-547-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon.h-487- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon.h:488:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0x50000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon.h-489-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon.h:490:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0x54000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon.h-491-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon.h:492:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x58000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon.h-493-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon.h:494:#define CONFIG_SYS_PCMCIA_IO_ADDR (0x5C000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/lwmon.h-495-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/m501sk.h-191-#define CONFIG_ENV_OFFSET 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/m501sk.h:192:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/m501sk.h-193-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/m501sk.h-195-#define CONFIG_ENV_IS_IN_FLASH
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/m501sk.h:196:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/m501sk.h-197-#define CONFIG_ENV_SIZE 2048
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M52277EVB.h-193-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M52277EVB.h:194:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M52277EVB.h-195-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M52277EVB.h-270-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M52277EVB.h:271:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M52277EVB.h-272-# define CONFIG_ENV_SIZE 0x1000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5235EVB.h-152-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5235EVB.h:153:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5235EVB.h-154-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5253DEMO.h-49-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5253DEMO.h:50:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5253DEMO.h-51-# define CONFIG_ENV_SECT_SIZE 0x1000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5253DEMO.h-81-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5253DEMO.h:82:# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5253DEMO.h-83-# define CONFIG_SYS_ATA_IDE0_OFFSET 0
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5253EVBE.h-87-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5253EVBE.h:88:#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5253EVBE.h-89-#define CONFIG_SYS_ATA_IDE0_OFFSET 0
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5329EVB.h-153-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5329EVB.h:154:#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5329EVB.h-155-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5373EVB.h-153-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5373EVB.h:154:#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5373EVB.h-155-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54451EVB.h-206-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54451EVB.h:207:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54451EVB.h-208-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54451EVB.h-274-# define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54451EVB.h:275:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54451EVB.h-276-# define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54455EVB.h-265-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54455EVB.h:266:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54455EVB.h-267-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54455EVB.h-349-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54455EVB.h:350:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54455EVB.h-351-# define CONFIG_ENV_SECT_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54455EVB.h-356-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54455EVB.h:357:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M54455EVB.h-358-# define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5475EVB.h-201-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5475EVB.h:202:/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5475EVB.h-203-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5475EVB.h-214-#define CONFIG_SYS_INIT_RAM_CTRL 0x21
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5475EVB.h:215:#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5475EVB.h-216-#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5485EVB.h-187-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5485EVB.h:188:/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5485EVB.h-189-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5485EVB.h-200-#define CONFIG_SYS_INIT_RAM_CTRL 0x21
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5485EVB.h:201:#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/M5485EVB.h-202-#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-84-#if defined(CONFIG_SYS_INIT_DCACHE_CS)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h:85:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-86-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h:87:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-88-#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-103-# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h:104:# define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-105-#else
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-107-# define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h:108:# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-109-# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-141-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h:142:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-143-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-349-{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h:350:{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/makalu.h-351-{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/manroland/mpc5200-common.h-90-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/manroland/mpc5200-common.h:91:#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/manroland/mpc5200-common.h-92-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h-121-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h:122:#define CONFIG_SYS_HWINFO_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_SYS_HWINFO_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h-123-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h-148-#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h:149:#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h-150-#define CONFIG_ENV_SIZE 0x1000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h-233-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h:234:#define BCSR_ADDR ((uint) 0xFF010000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h-235-#define BCSR_SIZE ((uint)(64 * 1024))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h-296-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h:297:#define PCMCIA_MEM_ADDR ((uint)0xff020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX860T.h-298-#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h-196-#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h:197:#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h-198-#define CONFIG_ENV_SIZE 0x1000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h-264- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h:265:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h-266-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h:267:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h-268-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h:269:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h-270-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h:271:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MBX.h-272-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mcc200.h-232-#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mcc200.h:233:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mcc200.h-234-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mcu25.h-137-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mcu25.h:138:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mcu25.h-139-#define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mcu25.h-202-#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE}
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mcu25.h:203:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mcu25.h-204-#undef CONFIG_LOGBUFFER
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mecp5123.h-56-#define CONFIG_SYS_IMMR 0x80000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mecp5123.h:57:#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mecp5123.h-58-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mecp5200.h-173-#define CONFIG_SYS_FLASH_SIZE 0x00400000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mecp5200.h:174:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mecp5200.h-175-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/meesc.h-154-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/meesc.h:155:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/meesc.h-156- CONFIG_ENV_OFFSET)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/METROBOX.h-131-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/METROBOX.h:132:#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/METROBOX.h-133-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/METROBOX.h-146-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/METROBOX.h:147:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/METROBOX.h-148-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/METROBOX.h-212-#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/METROBOX.h:213:#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/METROBOX.h-214-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mgcoge.h-136-#define CONFIG_ENV_SECT_SIZE 0x20000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mgcoge.h:137:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mgcoge.h-138-#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MHPC.h-100-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MHPC.h:101:#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MHPC.h-102-#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/microblaze-generic.h-166- #define CONFIG_ENV_SIZE 0x1000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/microblaze-generic.h:167: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/microblaze-generic.h-168-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/microblaze-generic.h-171- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/microblaze-generic.h:172: #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/microblaze-generic.h-173- #define CONFIG_ENV_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/microblaze-generic.h-179- #define CONFIG_ENV_SIZE 0x1000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/microblaze-generic.h:180: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/microblaze-generic.h-181- #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MigoR.h-92-/* default load address for scripts ?!? */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MigoR.h:93:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MigoR.h-94-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MigoR.h-137-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MigoR.h:138:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MigoR.h-139-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mimc200.h-169-#define CONFIG_ENV_SIZE 65536
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mimc200.h:170:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mimc200.h-171-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mimc200.h:172:#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mimc200.h-173-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mimc200.h-177-/* Allow 4MB for the kernel run-time image */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mimc200.h:178:#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mimc200.h-179-#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MIP405.h-308-#ifdef CONFIG_POST /* reserve one word for POST Info */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MIP405.h:309:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MIP405.h-310-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MIP405.h-312-#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MIP405.h:313:#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MIP405.h-314-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ml507.h-33-#define CONFIG_ENV_OFFSET 0x340000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ml507.h:34:#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ml507.h-35-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/motionpro.h-359-/* This has to be a multiple of the Flash sector size */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/motionpro.h:360:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/motionpro.h-361-#define CONFIG_ENV_SIZE 0x1000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mp2usb.h-209-#define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mp2usb.h:210:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mp2usb.h-211-#define CONFIG_ENV_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpc5121ads.h-72-#define CONFIG_SYS_IMMR 0x80000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpc5121ads.h:73:#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpc5121ads.h-74-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpc5121ads.h-380-/* This has to be a multiple of the Flash sector size */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpc5121ads.h:381:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpc5121ads.h-382-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpc5121-common.h-32- CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpc5121-common.h:33:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpc5121-common.h-34-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8260ADS.h-152-#define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8260ADS.h:153:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8260ADS.h-154- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8260ADS.h-395-# define CONFIG_ENV_SECT_SIZE 0x40000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8260ADS.h:396:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8260ADS.h-397-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8260ADS.h-398-# define CONFIG_ENV_IS_IN_NVRAM 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8260ADS.h:399:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8260ADS.h-400-# define CONFIG_ENV_SIZE 0x200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8266ADS.h-98-#define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8266ADS.h:99:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8266ADS.h-100- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8266ADS.h-435-# define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8266ADS.h:436:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8266ADS.h-437-# define CONFIG_ENV_SECT_SIZE 0x40000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8266ADS.h-439-# define CONFIG_ENV_IS_IN_NVRAM 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8266ADS.h:440:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8266ADS.h-441-# define CONFIG_ENV_SIZE 0x200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8313ERDB.h-396- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8313ERDB.h:397: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8313ERDB.h-398- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8313ERDB.h-403- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8313ERDB.h:404: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8313ERDB.h-405- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8315ERDB.h-468- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8315ERDB.h:469: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8315ERDB.h-470- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8315ERDB.h-474- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8315ERDB.h:475: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8315ERDB.h-476- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8323ERDB.h-371- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8323ERDB.h:372: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8323ERDB.h-373- #define CONFIG_ENV_SECT_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8323ERDB.h-377- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8323ERDB.h:378: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8323ERDB.h-379- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC832XEMDS.h-386- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC832XEMDS.h:387: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC832XEMDS.h-388- #define CONFIG_ENV_SECT_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC832XEMDS.h-392- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC832XEMDS.h:393: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC832XEMDS.h-394- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349EMDS.h-428- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349EMDS.h:429: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349EMDS.h-430- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349EMDS.h-439- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349EMDS.h:440: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349EMDS.h-441- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349ITX.h-444- #define CONFIG_ENV_IS_IN_FLASH
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349ITX.h:445: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349ITX.h-446- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349ITX.h-451- #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349ITX.h:452: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8349ITX.h-453- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360EMDS.h-425- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360EMDS.h:426: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360EMDS.h-427- #define CONFIG_ENV_SECT_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360EMDS.h-431- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360EMDS.h:432: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360EMDS.h-433- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360ERDK.h-343-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360ERDK.h:344:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360ERDK.h-345-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360ERDK.h-349-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360ERDK.h:350:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8360ERDK.h-351-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XEMDS.h-460- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XEMDS.h:461: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XEMDS.h-462- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XEMDS.h-466- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XEMDS.h:467: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XEMDS.h-468- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XERDB.h-468- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XERDB.h:469: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XERDB.h-470- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XERDB.h-474- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XERDB.h:475: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC837XERDB.h-476- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-131-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:132:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:133:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:134:#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:135:#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-136-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-219-#define CONFIG_FLASH_BR_PRELIM \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:220: (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-221- | BR_PS_16 | BR_V)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-224-#define CONFIG_SYS_BR1_PRELIM \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:225: (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-226- | BR_PS_16 | BR_V)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-263-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:264:#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-265-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-356-#define CONFIG_NAND_BR_PRELIM \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:357: (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-358- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-383-#define CONFIG_SYS_BR4_PRELIM \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:384: (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-385- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-390-#define CONFIG_SYS_BR5_PRELIM \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:391: (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-392- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-398-#define CONFIG_SYS_BR6_PRELIM \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:399: (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-400- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-642- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:643: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-644- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-650- #else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h:651: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8536DS.h-652- #endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540ADS.h-350- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540ADS.h:351: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540ADS.h-352- #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540ADS.h-356- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540ADS.h:357: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540ADS.h-358- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540EVAL.h-257-#define CONFIG_ENV_IS_NOWHERE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540EVAL.h:258:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540EVAL.h-259-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540EVAL.h-261-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540EVAL.h:262:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540EVAL.h-263-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540EVAL.h-268-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540EVAL.h:269:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8540EVAL.h-270-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8541CDS.h-378-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8541CDS.h:379:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8541CDS.h-380-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8544DS.h-81-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8544DS.h:82:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8544DS.h:83:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8544DS.h:84:#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8544DS.h:85:#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8544DS.h-86-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8544DS.h-394-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8544DS.h:395:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8544DS.h-396-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8548CDS.h-82-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8548CDS.h:83:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8548CDS.h:84:#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8548CDS.h:85:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8548CDS.h-86-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8548CDS.h-437-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8548CDS.h:438:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8548CDS.h-439-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8555CDS.h-376-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8555CDS.h:377:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8555CDS.h-378-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8560ADS.h-362-#define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8560ADS.h:363:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8560ADS.h-364- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8560ADS.h-386- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8560ADS.h:387: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8560ADS.h-388- #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8560ADS.h-392- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8560ADS.h:393: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8560ADS.h-394- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8568MDS.h-77-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8568MDS.h:78:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8568MDS.h:79:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8568MDS.h-80-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8568MDS.h-395-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8568MDS.h:396:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8568MDS.h-397-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8569MDS.h-105-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8569MDS.h:106:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8569MDS.h:107:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8569MDS.h-108-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8569MDS.h-510-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8569MDS.h:511:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8569MDS.h-512-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-95-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:96:#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:97:#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:98:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-99-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-183-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:184:#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-185-#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-186-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:187:#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-188-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-216-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:217:#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-218-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-300-/* NAND flash config */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:301:#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-302- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-317-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:318:#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-319- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-323-#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:324:#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-325- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-330-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:331:#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-332- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-556-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h:557:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8572DS.h-558-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h-84-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h:85:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h:86:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h:87:#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h-88-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h:89:#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h-90-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h-448-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h:449:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h-450-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h-453-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h:454:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8610HPCD.h-455-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-124-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:125:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:126:#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-127-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-188-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:189:#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-190- | 0x00001001) /* port size 16bit */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-192-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:193:#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-194- | 0x00001001) /* port size 16bit */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-196-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:197:#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-198- | 0x00000801) /* port size 8bit */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-467-#ifdef CONFIG_PHYS_64BIT
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:468:#define BAT_PHYS_ADDR(x) ((unsigned long) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-469- ((x & 0x00000000ffffffffULL) | \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-472-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:473:#define BAT_PHYS_ADDR(x) (x)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-474-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-489- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:490:#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-491- | BATL_PP_RW | BATL_CACHEINHIBIT | \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-494- | BATU_VS | BATU_VP)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:495:#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-496- | BATL_PP_RW | BATL_MEMCOHERENCE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-504-#ifdef CONFIG_PCI
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:505:#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-506- | BATL_PP_RW | BATL_CACHEINHIBIT \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-509- | BATU_VS | BATU_VP)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:510:#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-511- | BATL_PP_RW | BATL_CACHEINHIBIT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-513-#else /* CONFIG_RIO */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:514:#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-515- | BATL_PP_RW | BATL_CACHEINHIBIT | \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-518- | BATU_VS | BATU_VP)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:519:#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-520- | BATL_PP_RW | BATL_CACHEINHIBIT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-560- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:561:#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-562- | BATL_PP_RW | BATL_CACHEINHIBIT \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-565- | BATU_VS | BATU_VP)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:566:#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-567- | BATL_PP_RW | BATL_CACHEINHIBIT)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-580- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:581:#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-582- | BATL_PP_RW | BATL_CACHEINHIBIT \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-585- | BATU_VP)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:586:#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-587- | BATL_PP_RW | BATL_MEMCOHERENCE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-610- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:611: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-612- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-614- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h:615: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MPC8641HPCN.h-616-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpr2.h-55-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpr2.h:56:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpr2.h-57-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpr2.h-78-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpr2.h:79:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mpr2.h-80-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7720se.h-74-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7720se.h:75:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7720se.h-76-#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7720se.h-97-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7720se.h:98:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7720se.h-99-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7722se.h-85-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7722se.h:86:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7722se.h-87-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7722se.h-124-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7722se.h:125:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7722se.h-126-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7750se.h-78-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7750se.h:79:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7750se.h-80-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7750se.h-97-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7750se.h:98:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ms7750se.h-99-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/muas3001.h-103-#define MDIO_PORT 0 /* Port A */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/muas3001.h:104:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/muas3001.h-105- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/muas3001.h-238-#define CONFIG_ENV_SECT_SIZE 0x10000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/muas3001.h:239:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/muas3001.h-240-#endif /* CONFIG_ENV_IS_IN_FLASH */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/munices.h-156-#define CONFIG_ENV_OFFSET 0x40000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/munices.h:157:#define CONFIG_ENV_ADDR (TEXT_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/munices.h-158-#define CONFIG_ENV_SECT_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MVS1.h-256- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MVS1.h:257:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MVS1.h-258-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MVS1.h:259:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MVS1.h-260-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MVS1.h:261:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MVS1.h-262-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MVS1.h:263:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/MVS1.h-264-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mx1ads.h-175-#define CONFIG_SYS_MAX_FLASH_SECT (16)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mx1ads.h:176:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mx1ads.h-177-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mx31ads.h-185- * Putting it at the top of flash we use only 32KiB. */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mx31ads.h:186:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/mx31ads.h-187-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/neo.h-144-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/neo.h:145:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/neo.h-146-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETPHONE.h-220-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETPHONE.h:221:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETPHONE.h-222-#define CONFIG_ENV_OFFSET 0
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/netstar.h-218-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/netstar.h:219:#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/netstar.h-220-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA2.h-221-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA2.h:222:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA2.h-223-#define CONFIG_ENV_OFFSET 0
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h-224-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h:225:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h-226-#define CONFIG_ENV_OFFSET 0
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h-630-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h:631:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h-632-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h:633:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h-634-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h:635:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h-636-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h:637:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETTA.h-638-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETVIA.h-192-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETVIA.h:193:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NETVIA.h-194-#define CONFIG_ENV_OFFSET 0
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/nhk8815.h-174-# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/nhk8815.h:175:# define CONFIG_ENV_ADDR (0x00280000 - CONFIG_ENV_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/nhk8815.h-176-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/nios2-generic.h-109-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/nios2-generic.h:110:#define CONFIG_ENV_ADDR ((CONFIG_SYS_RESET_ADDR + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/nios2-generic.h-111- CONFIG_SYS_MONITOR_LEN) | \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ns9750dev.h-172-#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ns9750dev.h:173:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ns9750dev.h-174-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ns9750dev.h-177-#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ns9750dev.h:178:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ns9750dev.h-179-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NSCU.h-307-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NSCU.h:308:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NSCU.h-309-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NSCU.h:310:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NSCU.h-311-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NSCU.h:312:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NSCU.h-313-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NSCU.h:314:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NSCU.h-315-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NX823.h-367-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NX823.h:368:#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/NX823.h-369-#define CONFIG_ETHADDR 00:10:20:30:40:50
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/o2dnt.h-190-#define CONFIG_SYS_FLASH_SIZE 0x01000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/o2dnt.h:191:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/o2dnt.h-192-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h-65-#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h:66:#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h-67-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h-77-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h:78:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h-79-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h-136-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h:137:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h-138-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h-157-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h:158:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ocotea.h-159-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1510.h-354-#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1510.h:355:#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1510.h-356-#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1510inn.h-171-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1510inn.h:172:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1510inn.h-173-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1610h2.h-182-/* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1610h2.h:183:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1610h2.h-184-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1610inn.h-187-/* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1610inn.h:188:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap1610inn.h-189-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap2420h4.h-181-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap2420h4.h:182:#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap2420h4.h-183-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap2420h4.h-235-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap2420h4.h:236:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap2420h4.h-237-#define CONFIG_ENV_IS_IN_FLASH 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_beagle.h-251-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_beagle.h:252:#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_beagle.h-253- /* load address */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_evm.h-255-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_evm.h:256:#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_evm.h-257- /* address */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_overo.h-221-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_overo.h:222:#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_overo.h-223- /* address */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_pandora.h-212-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_pandora.h:213:#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_pandora.h-214- /* address */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_sdp3430.h-171-#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_sdp3430.h:172:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_sdp3430.h-173-/*--------------------------------------------------------------------------*/
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_sdp3430.h-293-/* Default load address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_sdp3430.h:294:#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_sdp3430.h-295-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_zoom1.h-236-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_zoom1.h:237:#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_zoom1.h-238- /* load address */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_zoom2.h-206-/* The default load address is the start of memory */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_zoom2.h:207:#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap3_zoom2.h-208-/* everything, incl board info, in Hz */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap5912osk.h-197-/* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap5912osk.h:198:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap5912osk.h-199-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap730.h-101-#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap730.h:102:#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap730.h-103-#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap730p2.h-193-/* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap730p2.h:194:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/omap730p2.h-195-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/otc570.h-216-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/otc570.h:217:#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/otc570.h-218- CONFIG_ENV_OFFSET)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-128-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h:129:#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h:130:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-131-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-176-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h:177:#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-178- BR_PS_16 | BR_V)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-379-/* This macro is used by RTL8139 but not defined in PPC architecture */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h:380:#define KSEG1ADDR(x) (x)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-381-#define _IO_BASE 0x00000000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-448- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h:449: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-450- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-456- #else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h:457: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P1_P2_RDB.h-458- #endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-98-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:99:#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:100:#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:101:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-102-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-215-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:216:#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-217-#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-218-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:219:#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-220-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-250-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:251:#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-252-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-287-/* NAND flash config */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:288:#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-289- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-306-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:307:#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-308- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-312-#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:313:#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-314- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-319-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:320:#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-321- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-535-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h:536:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/P2020DS.h-537-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/p3mx.h-145-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/p3mx.h:146:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/p3mx.h-147-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/p3p440.h-301-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/p3p440.h:302:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/p3p440.h-303-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PATI.h-130- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PATI.h:131:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PATI.h-132-#define CONFIG_SYS_INIT_RAM_END (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PATI.h-134-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PATI.h:135:#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PATI.h-136-/*
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PCI5441.h-89-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PCI5441.h:90:#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PCI5441.h-91-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PCIPPC2.h-221-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PCIPPC2.h:222:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PCIPPC2.h-223-#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PCIPPC6.h-223-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PCIPPC6.h:224:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PCIPPC6.h-225-#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h-113-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h:114:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h-115-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h-144-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h:145:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa4>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h-146-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h-373-/* GPIO Core 0 */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h:374:{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h:375:{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h:376:{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h:377:{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h:378:{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h:379:{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pcs440ep.h-380-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pdm360ng.h-74-#define CONFIG_SYS_IMMR 0x80000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pdm360ng.h:75:#define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pdm360ng.h-76-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pdm360ng.h-363-/* This has to be a multiple of the Flash sector size */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pdm360ng.h:364:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pdm360ng.h-365- CONFIG_SYS_MONITOR_LEN)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pdnb3.h-248-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pdnb3.h:249:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pdnb3.h-250-#if defined(CONFIG_SCPU)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pf5200.h-190-#define CONFIG_SYS_FLASH_SIZE 0x02000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pf5200.h:191:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pf5200.h-192-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PK1C20.h-91-#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PK1C20.h:92:#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PK1C20.h-93-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PK1C20.h-155- *----------------------------------------------------------------------*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PK1C20.h:156:#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PK1C20.h-157-#define CONFIG_NET_MULTI
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pleb2.h-258-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pleb2.h:259:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pleb2.h-260-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM520.h-189-#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM520.h:190:#define CONFIG_ENV_ADDR (0xFDF00000 + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM520.h-191-#else
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM520.h-202-#define CONFIG_SYS_FLASH_SIZE 0x04000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM520.h:203:#define CONFIG_ENV_ADDR (0xFFF00000 + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM520.h-204-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM826.h-246-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM826.h:247:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM826.h-248-#define CONFIG_ENV_SIZE 0x40000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM828.h-240-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM828.h:241:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM828.h-242-#define CONFIG_ENV_SIZE 0x40000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM854.h-295- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM854.h:296: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM854.h-297- #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM854.h-301- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM854.h:302: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM854.h-303- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM856.h-295- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM856.h:296: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM856.h-297- #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM856.h-301- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM856.h:302: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PM856.h-303- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pm9263.h-307-#define CONFIG_ENV_OFFSET 0x4200
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pm9263.h:308:#define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pm9263.h-309-#define CONFIG_ENV_SIZE 0x4200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PMC440.h-142-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PMC440.h:143:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PMC440.h-144-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PMC440.h-375-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PMC440.h:376:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/PMC440.h-377-#define CONFIG_LOGBUFFER
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc7xx.h-303-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc7xx.h:304:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc7xx.h-305-#define CONFIG_SYS_INIT_RAM_END 0x4000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h-184-#define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h:185:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h-186- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h-470-# ifdef CONFIG_ENV_IN_OWN_SECT
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h:471:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h-472-# define CONFIG_ENV_SECT_SIZE 0x40000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h-473-# else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h:474:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h-475-# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h-480-# define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h:481:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ppmc8260.h-482-#define CONFIG_ENV_SIZE 0x1000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/purple.h-168- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/purple.h:169:#define CONFIG_SYS_SCONSOLE_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/purple.h-170- CONFIG_SYS_DCACHE_SIZE / 2)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pxa255_idp.h-358- /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pxa255_idp.h:359:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/pxa255_idp.h-360-#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/qemu-mips.h-96-#define CONFIG_SYS_ATA_REG_OFFSET (0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/qemu-mips.h:97:#define CONFIG_SYS_ATA_BASE_ADDR (0xb4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/qemu-mips.h-98-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/qemu-mips.h-152-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/qemu-mips.h:153:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/qemu-mips.h-154-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/qong.h-248-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/qong.h:249:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/qong.h-250-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quad100hd.h-204-/* the environment is located before u-boot */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quad100hd.h:205:#define CONFIG_ENV_ADDR (TEXT_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quad100hd.h-206-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h-214-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h:215:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h-216-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h-306- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h:307:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h-308-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h:309:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h-310-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h:311:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h-312-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h:313:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/quantum.h-314-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r2dplus.h-53-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r2dplus.h:54:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r2dplus.h-55-/* Address of u-boot image in Flash */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r2dplus.h-76-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r2dplus.h:77:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r2dplus.h-78-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/R360MPI.h-317- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/R360MPI.h:318:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/R360MPI.h-319-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/R360MPI.h:320:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/R360MPI.h-321-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/R360MPI.h:322:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/R360MPI.h-323-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/R360MPI.h:324:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/R360MPI.h-325-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r7780mp.h-95-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r7780mp.h:96:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r7780mp.h-97-/* Address of u-boot image in Flash */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r7780mp.h-117-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r7780mp.h:118:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/r7780mp.h-119-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Rattler.h-105-#define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Rattler.h:106:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Rattler.h-107- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Rattler.h-233-#define CONFIG_ENV_SECT_SIZE 0x10000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Rattler.h:234:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Rattler.h-235-#endif /* CONFIG_ENV_IS_IN_FLASH */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RBC823.h-292- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RBC823.h:293:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RBC823.h-294-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RBC823.h:295:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RBC823.h-296-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RBC823.h:297:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RBC823.h-298-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RBC823.h:299:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RBC823.h-300-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/redwood.h-89-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/redwood.h:90:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/redwood.h-91-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h-191-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h:192:#define CONFIG_ENV_ADDR ((TEXT_BASE) + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h-193-#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h-279- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h:280:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h-281-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h:282:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h-283-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h:284:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h-285-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h:286:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rmu.h-287-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h-303- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h:304:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h-305-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h:306:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h-307-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h:308:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h-309-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h:310:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h-311-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h-390-/* Global definitions for the ECCX board */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h:391:#define ECCX_CSR_ADDR (0xfac00000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXClassic.h-392-#define ECCX_CSR8_OFFSET (0x8)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite_DW.h-324- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite_DW.h:325:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite_DW.h-326-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite_DW.h:327:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite_DW.h-328-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite_DW.h:329:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite_DW.h-330-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite_DW.h:331:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite_DW.h-332-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h-159-#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h:160:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h-161-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h-238- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h:239:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h-240-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h:241:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h-242-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h:243:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h-244-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h:245:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXlite.h-246-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXsuper.h-306-# ifdef CONFIG_ENV_IN_OWN_SECT
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXsuper.h:307:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXsuper.h-308-# define CONFIG_ENV_SECT_SIZE 0x40000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXsuper.h-309-# else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXsuper.h:310:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXsuper.h-311-# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXsuper.h-315-# define CONFIG_ENV_IS_IN_NVRAM 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXsuper.h:316:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RPXsuper.h-317-# define CONFIG_ENV_SIZE 0x200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RRvision.h-318- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RRvision.h:319:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RRvision.h-320-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RRvision.h:321:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RRvision.h-322-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RRvision.h:323:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RRvision.h-324-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RRvision.h:325:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/RRvision.h-326-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rsdproto.h-294-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rsdproto.h:295:#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rsdproto.h-296-#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rsk7203.h-76-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rsk7203.h:77:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rsk7203.h-78-#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rsk7203.h-97-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rsk7203.h:98:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/rsk7203.h-99-#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/s5p_goni.h-183-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/s5p_goni.h:184:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/s5p_goni.h-185-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/s5p_goni.h-208-#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB, 0x40000 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/s5p_goni.h:209:#define CONFIG_ENV_ADDR (1 << 20) /* 1 MB, 0x100000 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/s5p_goni.h-210-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h-181-#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h:182:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h-183- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h-716-# ifdef CONFIG_ENV_IN_OWN_SECT
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h:717:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h-718-# define CONFIG_ENV_SECT_SIZE 0x10000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h-719-# else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h:720:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h-721-# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h-726-# define CONFIG_ENV_IS_IN_NVRAM 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h:727:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sacsng.h-728-# define CONFIG_ENV_SIZE 0x200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sam460ex.h-234-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sam460ex.h:235:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sam460ex.h-236-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sam460ex.h-587-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sam460ex.h:588:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sam460ex.h:589:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sam460ex.h:590:{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sam460ex.h-591-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sandpoint8240.h-153-#define CONFIG_SYS_RAMBOOT 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sandpoint8240.h:154:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sandpoint8240.h-155-#define CONFIG_SYS_INIT_RAM_END 0x10000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sandpoint8245.h-123-#define CONFIG_SYS_RAMBOOT 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sandpoint8245.h:124:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Sandpoint8245.h-125-#define CONFIG_SYS_INIT_RAM_END 0x10000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc2410x.h-181-#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc2410x.h:182:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc2410x.h-183-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc2410x.h-187-#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc2410x.h:188:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc2410x.h-189-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h-203-#define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h:204:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h-205- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h-612-# ifdef CONFIG_ENV_IN_OWN_SECT
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h:613:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h-614-# define CONFIG_ENV_SECT_SIZE 0x40000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h-615-# else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h:616:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h-617-# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h-622-# define CONFIG_ENV_IS_IN_NVRAM 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h:623:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8260.h-624-# define CONFIG_ENV_SIZE 0x200
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8349.h-398- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8349.h:399: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8349.h-400- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8349.h-409- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8349.h:410: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8349.h-411- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h-292- #define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h:293: #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h-294- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h-342- #define CONFIG_ENV_IS_NOWHERE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h:343: #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h-344- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h-347- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h:348: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h-349- #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h-353- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h:354: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SBC8540.h-355- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h-111-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h:112:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h:113:#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h:114:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h-115-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h-459-#if TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h:460:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h-461-#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h-462-#elif TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h:463:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8548.h-464-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h-295- #define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h:296: #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h-297- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h-345- #define CONFIG_ENV_IS_NOWHERE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h:346: #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h-347- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h-350- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h:351: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h-352- #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h-356- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h:357: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8560.h-358- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8641d.h-110-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8641d.h:111:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8641d.h:112:#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8641d.h-113-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8641d.h-496-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8641d.h:497:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sbc8641d.h-498-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sc520_spunk.h-158-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sc520_spunk.h:159:# define CONFIG_ENV_ADDR (0x387a0000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sc520_spunk.h-160-# define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector (or 0x10000) */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SCM.h-273-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SCM.h:274:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SCM.h-275-#define CONFIG_ENV_SIZE 0x40000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h-156-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h:157:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h-158-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h-240-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h:241:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h-242-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h-359-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h:360:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h-361-#define CONFIG_LOGBUFFER
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h-433-/* GPIO Core 0 */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h:434:{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h:435:{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h:436:{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h:437:{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h:438:{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h:439:{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sequoia.h-440-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7763rdp.h-81-/* U-boot setting */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7763rdp.h:82:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7763rdp.h-83-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7763rdp.h-108-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7763rdp.h:109:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7763rdp.h-110-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7763rdp.h-123-#define CONFIG_SH_ETHER_USE_PORT (1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7763rdp.h:124:#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7763rdp.h-125-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7785lcr.h-105-#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7785lcr.h:106:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7785lcr.h-107-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7785lcr.h-181-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7785lcr.h:182:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sh7785lcr.h-183-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h-164-/* we take the last sector, 128 KB in size, but we only use 4 KB of it for stack reasons */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h:165:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x003E0000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h-166-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h-167-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h:168:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h-169-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h-181-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h:182:#define CONFIG_SYS_PCMCIA_IO_ADDR (0x20000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h-183-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h:184:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0x24000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h-185-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h:186:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x2C000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h-187-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h:188:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0x28000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/shannon.h-189-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SIMPC8313.h-311- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SIMPC8313.h:312: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SIMPC8313.h-313- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SIMPC8313.h-318- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SIMPC8313.h:319: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SIMPC8313.h-320- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SM850.h-268- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SM850.h:269:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SM850.h-270-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SM850.h:271:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SM850.h-272-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SM850.h:273:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SM850.h-274-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SM850.h:275:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SM850.h-276-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdk2400.h-182-/* Address and size of Primary Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdk2400.h:183:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdk2400.h-184-#define CONFIG_ENV_SIZE 0x40000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdk2410.h-167-#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdk2410.h:168:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdk2410.h-169-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdk2410.h-172-#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdk2410.h:173:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdk2410.h-174-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdkc100.h-227-#define CONFIG_ENV_SIZE (128 << 10) /* 128KiB, 0x20000 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdkc100.h:228:#define CONFIG_ENV_ADDR (256 << 10) /* 256KiB, 0x40000 */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smdkc100.h-229-#define CONFIG_ENV_OFFSET (256 << 10) /* 256KiB, 0x40000 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smmaco4.h-206-#if !defined(CONFIG_SYS_LOWBOOT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smmaco4.h:207:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smmaco4.h-208-#else /* CONFIG_SYS_LOWBOOT */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smmaco4.h:209:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/smmaco4.h-210-#endif /* CONFIG_SYS_LOWBOOT */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SMN42.h-82-#define CONFIG_SYS_I2C_SLAVE 0xA0
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SMN42.h:83:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA0 >> 1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SMN42.h-84-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SMN42.h-192-#define CONFIG_ENV_OFFSET 0x3C000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SMN42.h:193:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SMN42.h-194-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/socrates.h-319-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/socrates.h:320:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/socrates.h-321-#define CONFIG_ENV_SIZE 0x4000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sorcery.h-200-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sorcery.h:201:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sorcery.h-202-#define CONFIG_ENV_SIZE 0x4000 /* 16K */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sorcery.h-229-/* Use SRAM until RAM will be available */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sorcery.h:230:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/sorcery.h-231-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spc1920.h-189-#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spc1920.h:190:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spc1920.h-191-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SPD823TS.h-293- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SPD823TS.h:294:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SPD823TS.h-295-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SPD823TS.h:296:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SPD823TS.h-297-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SPD823TS.h:298:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SPD823TS.h-299-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SPD823TS.h:300:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SPD823TS.h-301-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spear-common.h-145-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spear-common.h:146:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spear-common.h-147- CONFIG_SYS_MONITOR_LEN)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spieval.h-297-#if !defined(CONFIG_SYS_LOWBOOT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spieval.h:298:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spieval.h-299-#else /* CONFIG_SYS_LOWBOOT */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spieval.h:300:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/spieval.h-301-#endif /* CONFIG_SYS_LOWBOOT */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxgp3.h-290- #define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxgp3.h:291: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxgp3.h-292- #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxgp3.h-296- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxgp3.h:297: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxgp3.h-298- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxssa.h-322-# endif
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxssa.h:323:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxssa.h-324-# define CONFIG_ENV_SIZE 0x4000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxxtc.h-205-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxxtc.h:206:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/stxxtc.h-207-#define CONFIG_ENV_OFFSET 0
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/svm_sc8xx.h-347- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/svm_sc8xx.h:348:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/svm_sc8xx.h-349-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/svm_sc8xx.h:350:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/svm_sc8xx.h-351-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/svm_sc8xx.h:352:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/svm_sc8xx.h-353-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/svm_sc8xx.h:354:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/svm_sc8xx.h-355-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SX1.h-178-#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SX1.h:179:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/SX1.h-180-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/taihu.h-209-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/taihu.h:210:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/taihu.h-211-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/taishan.h-73-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/taishan.h:74:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/taishan.h-75-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/taishan.h-104-#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/taishan.h:105:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/taishan.h-106-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TB5200.h-265-#if !defined(CONFIG_SYS_LOWBOOT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TB5200.h:266:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TB5200.h-267-#else /* CONFIG_SYS_LOWBOOT */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TB5200.h-268-#if defined(CONFIG_TQM5200_B)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TB5200.h:269:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TB5200.h-270-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TB5200.h:271:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TB5200.h-272-#endif /* CONFIG_TQM5200_B */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/tcm-bf518.h-97-#define CONFIG_ENV_OFFSET 0x8000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/tcm-bf518.h:98:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/tcm-bf518.h-99-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TK885D.h-335- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TK885D.h:336:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TK885D.h-337-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TK885D.h:338:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TK885D.h-339-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TK885D.h:340:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TK885D.h-341-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TK885D.h:342:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TK885D.h-343-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/tnetv107x_evm.h-121- sizeof(CONFIG_SYS_PROMPT) + 16)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/tnetv107x_evm.h:122:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/tnetv107x_evm.h-123- 0x700000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/tnetv107x_evm.h:124:#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/tnetv107x_evm.h-125-#define CONFIG_CMDLINE_TAG
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TOP5200.h-235-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TOP5200.h:236:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TOP5200.h-237-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM5200.h-401-#if defined (CONFIG_CAM5200)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM5200.h:402:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM5200.h-403-#elif defined(CONFIG_TQM5200_B)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM5200.h:404:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM5200.h-405-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM5200.h:406:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM5200.h-407-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823L.h-327- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823L.h:328:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823L.h-329-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823L.h:330:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823L.h-331-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823L.h:332:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823L.h-333-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823L.h:334:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823L.h-335-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823M.h-323- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823M.h:324:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823M.h-325-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823M.h:326:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823M.h-327-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823M.h:328:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823M.h-329-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823M.h:330:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM823M.h-331-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8260.h-310-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8260.h:311:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8260.h-312-#define CONFIG_ENV_SIZE 0x08000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h-221-#define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h:222:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h-223- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h-386-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h:387:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h-388-#define CONFIG_ENV_SIZE 0x20000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h-394-#define MON_RES_LENGTH (0x0003FC00)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h:395:#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h-396-#define HWIB_INFO_LEN 512
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h:397:#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM8272.h-398-#define CIB_INFO_LEN 512
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM834x.h-281-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM834x.h:282:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM834x.h-283-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850L.h-312- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850L.h:313:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850L.h-314-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850L.h:315:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850L.h-316-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850L.h:317:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850L.h-318-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850L.h:319:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850L.h-320-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850M.h-312- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850M.h:313:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850M.h-314-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850M.h:315:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850M.h-316-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850M.h:317:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850M.h-318-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850M.h:319:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM850M.h-320-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855L.h-316- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855L.h:317:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855L.h-318-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855L.h:319:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855L.h-320-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855L.h:321:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855L.h-322-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855L.h:323:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855L.h-324-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855M.h-351- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855M.h:352:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855M.h-353-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855M.h:354:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855M.h-355-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855M.h:356:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855M.h-357-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855M.h:358:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM855M.h-359-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h-139-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h:140:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h:141:#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h:142:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h-143-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h-241-#define CONFIG_SYS_INIT_RAM_LOCK 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h:242:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h-243- + 0x04010000) /* Initial RAM address */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h-539-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h:540:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM85xx.h-541-#define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860L.h-315- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860L.h:316:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860L.h-317-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860L.h:318:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860L.h-319-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860L.h:320:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860L.h-321-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860L.h:322:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860L.h-323-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860M.h-316- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860M.h:317:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860M.h-318-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860M.h:319:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860M.h-320-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860M.h:321:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860M.h-322-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860M.h:323:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM860M.h-324-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862L.h-319- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862L.h:320:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862L.h-321-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862L.h:322:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862L.h-323-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862L.h:324:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862L.h-325-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862L.h:326:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862L.h-327-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862M.h-320- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862M.h:321:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862M.h-322-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862M.h:323:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862M.h-324-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862M.h:325:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862M.h-326-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862M.h:327:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM862M.h-328-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM866M.h-348- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM866M.h:349:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM866M.h-350-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM866M.h:351:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM866M.h-352-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM866M.h:353:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM866M.h-354-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM866M.h:355:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM866M.h-356-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM885D.h-333- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM885D.h:334:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM885D.h-335-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM885D.h:336:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM885D.h-337-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM885D.h:338:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM885D.h-339-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM885D.h:340:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/TQM885D.h-341-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/trab.h-401-#ifndef CONFIG_FLASH_8MB
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/trab.h:402:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/trab.h-403-#define CONFIG_ENV_SIZE 0x4000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/trab.h-405-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/trab.h:406:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/trab.h-407-#define CONFIG_ENV_SIZE 0x4000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/trizepsiv.h-335-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/trizepsiv.h:336:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/trizepsiv.h-337-#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h-244-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h:245:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h-246-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h-323- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h:324:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h-325-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h:326:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h-327-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h:328:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h-329-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h:330:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/uc100.h-331-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v37.h-281- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v37.h:282:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v37.h-283-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v37.h:284:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v37.h-285-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v37.h:286:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v37.h-287-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v37.h:288:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v37.h-289-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v38b.h-215-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v38b.h:216:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v38b.h-217-#define CONFIG_ENV_SIZE 0x10000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v5fx30teval.h-33-#define CONFIG_ENV_OFFSET 0x1A0000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v5fx30teval.h:34:#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/v5fx30teval.h-35-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VCMA9.h-227-#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VCMA9.h:228:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VCMA9.h-229-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VCMA9.h-232-#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VCMA9.h:233:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VCMA9.h-234-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vct.h-220-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vct.h:221:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vct.h-222-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vct.h-234-#define CONFIG_SYS_FLASH_BASE 0x00000000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vct.h:235:#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vct.h-236-#define CONFIG_ENV_SIZE (128 << 10) /* erase size */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/versatile.h-227-#define CONFIG_ENV_SIZE 8192
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/versatile.h:228:#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/versatile.h-229-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/virtlab2.h-321- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/virtlab2.h:322:#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/virtlab2.h-323-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/virtlab2.h:324:#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/virtlab2.h-325-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/virtlab2.h:326:#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/virtlab2.h-327-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/virtlab2.h:328:#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/virtlab2.h-329-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vme8349.h-329- #define CONFIG_ENV_IS_IN_FLASH
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vme8349.h:330: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vme8349.h-331- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vme8349.h-340- #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vme8349.h:341: #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/vme8349.h-342- #define CONFIG_ENV_SIZE 0x2000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/voiceblue.h-62-#define CONFIG_ENV_IS_IN_FLASH
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/voiceblue.h:63:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/voiceblue.h-64-#define CONFIG_ENV_SIZE (8 * 1024)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/voiceblue.h-208- (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/voiceblue.h:209:#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/voiceblue.h-210-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VoVPN-GW.h-127-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VoVPN-GW.h:128:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VoVPN-GW.h-129- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VoVPN-GW.h-267-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VoVPN-GW.h:268:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00020000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/VoVPN-GW.h-269-#define CONFIG_ENV_SIZE 0x00020000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/walnut.h-98-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/walnut.h:99:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/walnut.h-100-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/walnut.h-163-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/walnut.h:164:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/walnut.h-165-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xaeniax.h-181-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xaeniax.h:182:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xaeniax.h-183-#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xilinx-ppc405-generic.h-40-#define CONFIG_SYS_ENV_OFFSET 0x3F0000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xilinx-ppc405-generic.h:41:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xilinx-ppc405-generic.h-42-#define CONFIG_ENV_OVERWRITE 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xilinx-ppc440-generic.h-33-#define CONFIG_ENV_OFFSET 0x340000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xilinx-ppc440-generic.h:34:#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xilinx-ppc440-generic.h-35-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xm250.h-190-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xm250.h:191:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xm250.h-192-#define CONFIG_ENV_SIZE 0x4000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE1000.h-59-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE1000.h:60:#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE1000.h-61-#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE1000.h-105-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE1000.h:106:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE1000.h-107-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE1000.h-256-#define CONFIG_ENV_SIZE 0x8000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE1000.h:257:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE1000.h-258-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5170.h-99-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5170.h:100:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5170.h:101:#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5170.h-102-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5170.h-590-#define CONFIG_ENV_SIZE 0x8000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5170.h:591:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5170.h-592-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5200.h-83-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5200.h:84:#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5200.h-85-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5200.h-382-#define CONFIG_ENV_SIZE 0x8000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5200.h:383:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5200.h-384-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5370.h-100-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5370.h:101:#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5370.h:102:#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5370.h-103-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5370.h-439-#define CONFIG_ENV_SIZE 0x8000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5370.h:440:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/XPEDITE5370.h-441-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xsengine.h-83-#define CONFIG_ENV_IS_IN_FLASH 1
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xsengine.h:84:#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/xsengine.h-85-#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yosemite.h-122-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yosemite.h:123:#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yosemite.h-124-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yosemite.h-143-#define CONFIG_SYS_I2C_MULTI_EEPROMS
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yosemite.h:144:#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yosemite.h-145-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yucca.h-102-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yucca.h:103:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yucca.h-104-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yucca.h-194-#define CONFIG_ENV_ADDR 0xfffa0000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yucca.h:195:/* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/yucca.h-196-#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-209-#if defined (CONFIG_SYS_AMD_BOOT)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h:210:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-211-#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-212-#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h:213:#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-214-#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-216-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h:217:#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-218-#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-219-#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h:220:#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-221-#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-258-/* Use SRAM until RAM will be available */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h:259:#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/Yukon8220.h-260-#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/zeus.h-231-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/zeus.h:232:#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/zeus.h-233-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/zeus.h-257-/* extra data in OCM */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/zeus.h:258:#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/zeus.h-259-#define CONFIG_SYS_POST_MAGIC (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZPC1900.h-88-#define MDIO_PORT 2 /* Port C */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZPC1900.h:89:#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZPC1900.h-90- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZPC1900.h-232-# define CONFIG_ENV_SECT_SIZE 0x10000
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZPC1900.h:233:# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZPC1900.h-234-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZPC1900.h:235:# define CONFIG_ENV_ADDR (CONFIG_SYS_EEPROM + 0x400)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZPC1900.h-236-# define CONFIG_ENV_SIZE 0x1000
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZUMA.h-354-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZUMA.h:355:#define CONFIG_ENV_ADDR (0xfff80000 - CONFIG_ENV_SECT_SIZE)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/ZUMA.h-356-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/zylonite.h-145-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/zylonite.h:146:#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/configs/zylonite.h-147-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/environment.h-41-# ifndef CONFIG_ENV_ADDR
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/environment.h:42:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/environment.h-43-# endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/environment.h-143-/* Function that returns a pointer to a value from the environment */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/environment.h:144:unsigned char *env_get_addr(int);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/environment.h-145-unsigned char env_get_char_memory (int index);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/fdt_support.h-78-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/fdt_support.h:79:void set_working_fdt_addr(void *addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/fdt_support.h-80-int fdt_resize(void *blob);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/i2c.h-73-# if defined(CONFIG_MPC8260)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/i2c.h:74:# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/i2c.h-75-# elif defined(CONFIG_8xx)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/i2c.h-148- * addr: Memory (register) address within the chip
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/i2c.h:149: * alen: Number of bytes to use for addr (typically 1, 2 for larger
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/i2c.h-150- * memories, 0 for register type devices with only one
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ioports.h-28-#ifdef CONFIG_MPC85xx
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ioports.h:29:#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ioports.h-30-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ioports.h:31:#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ioports.h-32-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/linux/compiler-gcc4.h-42- * Mark a position in code as unreachable. This can be used to
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/linux/compiler-gcc4.h:43: * suppress control flow warnings after asm blocks that transfer
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/linux/compiler-gcc4.h-44- * control elsewhere.
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/linux/ioport.h-96-/* PnP I/O specific bits (IORESOURCE_BITS) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/linux/ioport.h:97:#define IORESOURCE_IO_16BIT_ADDR (1<<0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/linux/ioport.h-98-#define IORESOURCE_IO_FIXED (1<<1)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc824x.h-168-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc824x.h:169:#define CONFIG_ADDR (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc824x.h-170-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-56- unsigned long hid0;
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h:57: asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-58- return hid0;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-63- unsigned long hid1;
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h:64: asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-65- return hid1;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-69-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h:70: asm volatile("mtspr 1008, %0" : : "r" (hid0));
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-71-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-74-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h:75: asm volatile("mtspr 1009, %0" : : "r" (hid1));
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-76-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-81- unsigned long l2cr_val;
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h:82: asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/mpc86xx.h-83- return l2cr_val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-122-extern int eth_get_dev_index (void); /* get the device index */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h:123:extern void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h:124:extern int eth_getenv_enetaddr(char *name, uchar *enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h:125:extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-126-extern int eth_getenv_enetaddr_by_index(int index, uchar *enetaddr);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-330-extern uchar NetServerEther[6]; /* Boot server enet address */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h:331:extern IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h:332:extern IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-333-extern volatile uchar * NetTxPacket; /* THE transmit packet */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-466- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h:467:static inline int is_zero_ether_addr(const u8 *addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-468-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-478- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h:479:static inline int is_multicast_ether_addr(const u8 *addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-480-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-492- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h:493:static inline int is_valid_ether_addr(const u8 * addr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-494-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-496- * explicitly check for it here. */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h:497: return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/net.h-498-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/nios2.h-42- ({unsigned int val;\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/nios2.h:43: asm volatile( "rdctl %0, ctl" _str_(reg)\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/nios2.h-44- : "=r" (val) ); val;})
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/nios2.h-46-#define wrctl(reg,val)\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/nios2.h:47: asm volatile( "wrctl ctl" _str_(reg) ",%0"\
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/nios2.h-48- : : "r" (val))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns7520_eth.h-33-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns7520_eth.h:34:#define get_eth_reg_addr(c) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns7520_eth.h-35- ((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h-33-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h:34:#define get_bbus_reg_addr(c) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h-35- ((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c)))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h-38-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h:39:#define get_gpio_cfg_reg_addr(pin) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h:40: get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) )
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h-41-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h-45-#define set_gpio_cfg_reg_val(pin,cfg) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h:46: *get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_bbus.h-47- ~NS9750_GPIO_CFG_MASK((pin))) |\
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_eth.h-38-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_eth.h:39:#define get_eth_reg_addr(c) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_eth.h-40- ((volatile unsigned int*) ( NS9750_ETH_MODULE_BASE+(unsigned int) (c)))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_mem.h-32-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_mem.h:33:#define get_mem_reg_addr(c) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_mem.h-34- ((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c)))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_ser.h-31-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_ser.h:32:#define get_ser_reg_addr(c) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_ser.h-33- ((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_ser.h-35-#define get_ser_reg_addr_channel(reg,chan) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_ser.h:36: get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_ser.h-37-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_sys.h-32-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_sys.h:33:#define get_sys_reg_addr(c) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_sys.h-34- ((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c)))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_sys.h-47-#define NS9750_SYS_INT_CFG_BASE (0x0144)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_sys.h:48:#define NS9750_SYS_ISRADDR (0x0164)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ns9750_sys.h-49-#define NS9750_SYS_INT_STAT_ACTIVE (0x0168)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/onenand_uboot.h-43-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/onenand_uboot.h:44:extern loff_t onenand_addr(struct onenand_chip *this, int block);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/onenand_uboot.h-45-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/part.h-36-#ifdef CONFIG_LBA48
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/part.h:37: unsigned char lba48; /* device can use 48bit addr (ATA/ATAPI v7) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/part.h-38-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc440.h-644-#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc440.h:645:#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc440.h-646-#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc440.h-649-#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc440.h:650:#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc440.h-651-#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc440.h-1855- register */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc440.h:1856:#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc440.h-1857- register */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx_enet.h-503-#define EMAC_STACR_OP_MASK (0x00001800)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx_enet.h:504:#define EMAC_STACR_MDIO_ADDR (0x00000000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx_enet.h-505-#define EMAC_STACR_MDIO_WRITE (0x00000800)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-140-#define CPR0_DCR_BASE 0x0C
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h:141:#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-142-#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-144-#define SDR_DCR_BASE 0x0E
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h:145:#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-146-#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-148-#define SDRAM_DCR_BASE 0x10
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h:149:#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-150-#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-152-#define EBC_DCR_BASE 0x12
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h:153:#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-154-#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-208-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h:209: asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-210- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-214-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h:215: asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/ppc4xx.h-216-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/tsi108.h-57-
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/tsi108.h:58:#define HLP_B0_ADDR (0x000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/tsi108.h:59:#define HLP_B1_ADDR (0x010)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/tsi108.h:60:#define HLP_B2_ADDR (0x020)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/tsi108.h:61:#define HLP_B3_ADDR (0x030)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/tsi108.h-62-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/tsi108.h-148-#define I2C_CNTRL1_PAGE (0x00000700)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/tsi108.h:149:#define I2C_CNTRL1_BYTADDR (0x00ff0000)
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/tsi108.h-150-#define I2C_CNTRL1_I2CWRITE (0x01000000)
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/usb/omap1510_udc.h-145- */
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/usb/omap1510_udc.h:146:#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
qemu-5.1+dfsg/roms/u-boot-sam460ex/include/usb/omap1510_udc.h-147-#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/crc32.c-153-/* =========================================================================
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/crc32.c:154: * This function can be used by asm versions of crc32()
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/crc32.c-155- */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/lzma/import_lzmasdk.sh-17-
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/lzma/import_lzmasdk.sh:18:BASENAME=`basename $1 .tar.bz2`
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/lzma/import_lzmasdk.sh-19-TMPDIR=/tmp/tmp_lib_$BASENAME
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/lzma/import_lzmasdk.sh-30-for i in $FILES; do
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/lzma/import_lzmasdk.sh:31: echo Copying $TMPDIR/$i \-\> `basename $i`
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/lzma/import_lzmasdk.sh-32- cp $TMPDIR/$i .
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/lzma/import_lzmasdk.sh:33: chmod -x `basename $i`
qemu-5.1+dfsg/roms/u-boot-sam460ex/lib/lzma/import_lzmasdk.sh-34-done
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/MAKEALL-1018- )
qemu-5.1+dfsg/roms/u-boot-sam460ex/MAKEALL:1019: for target in `eval echo '$LIST_'${arg}`
qemu-5.1+dfsg/roms/u-boot-sam460ex/MAKEALL-1020- do
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/Makefile-260-else
qemu-5.1+dfsg/roms/u-boot-sam460ex/Makefile:261:PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
qemu-5.1+dfsg/roms/u-boot-sam460ex/Makefile-262-endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/Makefile-3761-backup:
qemu-5.1+dfsg/roms/u-boot-sam460ex/Makefile:3762: F=`basename $(TOPDIR)` ; cd .. ; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/Makefile:3763: gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
qemu-5.1+dfsg/roms/u-boot-sam460ex/Makefile-3764-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig-19- -n) shift ; BOARD_NAME="${1%%_config}" ; shift ;;
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig:20: -t) shift ; TARGETS="`echo $1 | sed 's:_: :g'` ${TARGETS}" ; shift ;;
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig-21- *) break ;;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig-44- rm -f asm
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig:45: ln -s ${SRCTREE}/arch/$2/include/asm asm
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig-46- LNPREFIX=${SRCTREE}/arch/$2/include/asm/
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig-48- rm -f asm
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig:49: ln -s ${SRCTREE}/arch/$2/include/asm asm
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig-50-else
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig-52- rm -f asm
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig:53: ln -s ../arch/$2/include/asm asm
qemu-5.1+dfsg/roms/u-boot-sam460ex/mkconfig-54-fi
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/bootp.c-559- /* get our mac */
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/bootp.c:560: eth_getenv_enetaddr("ethaddr", bi_enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/bootp.c-561-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-28-
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c:29:void eth_parse_enetaddr(const char *addr, uchar *enetaddr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-30-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-40-
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c:41:int eth_getenv_enetaddr(char *name, uchar *enetaddr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-42-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c:43: eth_parse_enetaddr(getenv(name), enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c:44: return is_valid_ether_addr(enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-45-}
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-46-
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c:47:int eth_setenv_enetaddr(char *name, const uchar *enetaddr)
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-48-{
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-59- sprintf(enetvar, index ? "eth%daddr" : "ethaddr", index);
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c:60: return eth_getenv_enetaddr(enetvar, enetaddr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-61-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-254- !eth_mac_skip(eth_number) &&
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c:255: is_valid_ether_addr(dev->enetaddr)) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c:256: dev->write_hwaddr(dev);
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/eth.c-257- }
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-136- { 0, 0, 0, 0, 0, 0 };
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c:137:IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c:138:IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-139-volatile uchar *NetRxPacket; /* Current receive packet */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-286- NetCopyIP(&NetOurIP, &bd->bi_ip_addr);
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c:287: NetOurGatewayIP = getenv_IPaddr ("gatewayip");
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c:288: NetOurSubnetMask= getenv_IPaddr ("netmask");
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c:289: NetServerIP = getenv_IPaddr ("serverip");
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-290- NetOurNativeVLAN = getenv_VLAN("nvlan");
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-292-#if defined(CONFIG_CMD_DNS)
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c:293: NetOurDNSIP = getenv_IPaddr("dnsip");
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-294-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-355-#else
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c:356: eth_getenv_enetaddr("ethaddr", NetOurEther);
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-357-#endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-1463-
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c:1464: debug("Got ARP REPLY, set server/gtwy eth addr (%pM)\n",
qemu-5.1+dfsg/roms/u-boot-sam460ex/net/net.c-1465- arp->ar_data);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/cpu/mpc8xx/ether.c-305-
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/cpu/mpc8xx/ether.c:306: eth_getenv_enetaddr("ethaddr", ea);
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/cpu/mpc8xx/ether.c-307- pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/cpu/mpc8xx/watchdog.c-44-
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/cpu/mpc8xx/watchdog.c:45: asm ("mftbl %0":"=r" (r));
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/cpu/mpc8xx/watchdog.c-46-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/cpu/ppc4xx/spr.c-182-
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/cpu/ppc4xx/spr.c:183: asm volatile ("isync");
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/cpu/ppc4xx/spr.c-184-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/drivers/memory.c-189-#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/drivers/memory.c:190: asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/drivers/memory.c-191- "stfd 0, 0(4)" /* *dest = fpr0 */
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/asm.S-325-
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/asm.S:326:/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/asm.S-327- .global cpu_post_complex_1_asm
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/asm.S-342-
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/asm.S:343:/* int cpu_post_complex_2_asm (int x, int n); */
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/asm.S-344- .global cpu_post_complex_2_asm
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/complex.c-38-
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/complex.c:39:extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n);
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/complex.c:40:extern int cpu_post_complex_2_asm (int x, int n);
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/complex.c-41-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/cr.c-252-
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/cr.c:253: asm ( "mfcr %0" : "=r" (cr_sav) : );
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/cr.c-254-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/cr.c-348-
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/cr.c:349: asm ( "mtcr %0" : : "r" (cr_sav));
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/lib_powerpc/cr.c-350-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/Makefile-51- @for lib in $(SPLIB-y) ; do \
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/Makefile:52: $(MAKE) -C `dirname $$lib` all ; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/post/Makefile-53- done
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/README.u-boot-3992- is a volatile register so r12 needs to be reset when
qemu-5.1+dfsg/roms/u-boot-sam460ex/README.u-boot:3993: going back and forth between asm and C)
qemu-5.1+dfsg/roms/u-boot-sam460ex/README.u-boot-3994-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/rules.mk-30- @for f in $(SRCS); do \
qemu-5.1+dfsg/roms/u-boot-sam460ex/rules.mk:31: g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/rules.mk-32- $(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/rules.mk-34- @for f in $(HOSTSRCS); do \
qemu-5.1+dfsg/roms/u-boot-sam460ex/rules.mk:35: g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
qemu-5.1+dfsg/roms/u-boot-sam460ex/rules.mk-36- $(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/brlog.php-33-<?php
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/brlog.php:34: $r=mysql_query("select * from boards where serno=$serno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/brlog.php-35-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/brlog.php-60- $offset=abs(isset($_REQUEST['offset'])?$_REQUEST['offset']:0);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/brlog.php:61: $lr=mysql_query("select count(*) as n from log where serno=$serno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/brlog.php-62- $lrow=mysql_fetch_array($lr);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/brlog.php-80-<?php
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/brlog.php:81: $r=mysql_query("select * from log where serno=$serno order by logno limit $offset,$limit");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/brlog.php-82-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/browse.php-90-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/browse.php:91: $r = mysql_query($query);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/browse.php-92-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/defs.php-205- $x .= ');';
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/defs.php:206: eval($x);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/defs.php-207- $l = strlen($s);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/defs.php-498-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/defs.php:499: function gen_eth_addr($serno) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/defs.php-500-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/dodelete.php-16-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/dodelete.php:17: mysql_query("delete from boards where serno=$serno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/dodelete.php-18-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/dodelete.php-34- . " successfully deleted\n";
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/dodelete.php:35: mysql_query("delete from log where serno=$serno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/dodelete.php-36- if (mysql_errno()) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/dodellog.php-20-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/dodellog.php:21: mysql_query("delete from log where serno=$serno and logno=$logno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/dodellog.php-22-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedit.php-141-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedit.php:142: $query.=" where serno=$serno";
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedit.php-143-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedit.php:144: mysql_query($query);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedit.php-145- if(mysql_errno()) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedlog.php-41-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedlog.php:42: $query.=" where serno=$serno and logno=$logno";
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedlog.php-43-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedlog.php:44: mysql_query($query);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/doedlog.php-45- if(mysql_errno()) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donewlog.php-50- else {
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donewlog.php:51: mysql_query($query . " where logno=$logno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donewlog.php-52- if (mysql_errno())
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donew.php-122-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donew.php:123: mysql_query($query . " where serno=$serno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donew.php-124- if (mysql_errno()) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donew.php-132-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donew.php:133: $ethaddr = gen_eth_addr($serno);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donew.php-134-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donew.php-135- mysql_query("update boards set ethaddr='$ethaddr'" .
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donew.php:136: " where serno=$serno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/donew.php-137- if (mysql_errno()) {
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/edit.php-27-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/edit.php:28: $r=mysql_query("select * from boards where serno=$serno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/edit.php-29- $row=mysql_fetch_array($r);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/edlog.php-34-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/edlog.php:35: $r=mysql_query("select * from log where serno=$serno and logno=$logno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/edlog.php-36- $row=mysql_fetch_array($r);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/new.php-19- if ($serno != 0) {
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/new.php:20: $r=mysql_query("select * from boards where serno=$serno");
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/bddb/new.php-21- $row=mysql_fetch_array($r);
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/envcrc.c-39-# ifndef CONFIG_ENV_ADDR
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/envcrc.c:40:# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/envcrc.c-41-# endif
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/img2brec.sh-63-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/img2brec.sh:64:FILESIZE=`filesize $INFILE`
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/img2brec.sh-65-
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/Makefile-84- $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/Makefile:85: -e `$(NM) $(obj)multiplier | grep _main | cut --bytes=1-8` \
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/Makefile-86- -n "Multiplier" -d /tmp/tempimage $(obj)multiplier.image
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-39- int x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:40: asm volatile ("lbz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-41- return (uint8)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-46-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:47: asm volatile ("stb %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-48-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-52- int x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:53: asm volatile ("lhbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m" (*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-54- return (uint16)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-59- int x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:60: asm volatile ("lhz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-61- return (uint16)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-65-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:66: asm volatile ("sthbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-67-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-70-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:71: asm volatile ("sth %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-72-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-76- unsigned long x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:77: asm volatile ("lwbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m"(*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-78- return (uint32)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-83- unsigned long x;
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:84: asm volatile ("lwz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-85- return (uint32)x;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-89-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:90: asm volatile ("stwbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-91-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-94-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:95: asm volatile ("stw %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-96-}
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-97-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:98:#define CONFIG_ADDR(bus, devfn, offset) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-99- write_long_big((uint32 *)0xEEC00000, \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-104-/*
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h:105:#define CONFIG_ADDR(bus, devfn, offset) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/memio.h-106- write_long_big((uint32 *)0xFEC00CF8, \
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c-10-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c:11: asm volatile("mfmsr %0" : "=r" (msr) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c-12- return msr;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c-17-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c:18: asm volatile("mtmsr %0" : : "r" (msr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c-19-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c-25-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c:26: asm volatile("mfdec %0" : "=r" (val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c-27- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c-33-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c:34: asm volatile("mtdec %0" : : "r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/multiplier/utils.c-35-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/setlocalversion-27- if git config --get svn-remote.svn.url >/dev/null; then
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/setlocalversion:28: printf -- '-svn%s' "`git svn find-rev $head`"
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/setlocalversion-29- fi
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/setlocalversion-33-if rev=`svn info 2>/dev/null` ; then
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/setlocalversion:34: rev=`echo "${rev}" | grep '^Revision' | awk '{print $NF}'`
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/setlocalversion-35- printf -- '-svn%s' $rev
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/Makefile-77- $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/Makefile:78: -e `$(NM) $(obj)updater | grep _main | cut --bytes=1-8` \
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/Makefile-79- -n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c-10-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c:11: asm volatile("mfmsr %0" : "=r" (msr) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c-12- return msr;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c-17-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c:18: asm volatile("mtmsr %0" : : "r" (msr));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c-19-}
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c-25-
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c:26: asm volatile("mfdec %0" : "=r" (val) :);
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c-27- return val;
##############################################
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c-33-{
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c:34: asm volatile("mtdec %0" : : "r" (val));
qemu-5.1+dfsg/roms/u-boot-sam460ex/tools/updater/utils.c-35-}
##############################################
qemu-5.1+dfsg/scripts/checkpatch.pl-2088- if ($prefix !~ /$Type\s+$/ &&
qemu-5.1+dfsg/scripts/checkpatch.pl:2089: ($where != 0 || $prefix !~ /^.\s+$/) &&
qemu-5.1+dfsg/scripts/checkpatch.pl-2090- $prefix !~ /\#\s*define[^(]*\([^)]*\)\s+$/ &&
##############################################
qemu-5.1+dfsg/scripts/get_maintainer.pl-1220-
qemu-5.1+dfsg/scripts/get_maintainer.pl:1221: my $output = `$cmd`;
qemu-5.1+dfsg/scripts/get_maintainer.pl-1222- $output =~ s/^\s*//gm;
##############################################
qemu-5.1+dfsg/scripts/get_maintainer.pl-1231-
qemu-5.1+dfsg/scripts/get_maintainer.pl:1232: my $output = `$cmd`;
qemu-5.1+dfsg/scripts/get_maintainer.pl-1233- @lines = split("\n", $output);
##############################################
qemu-5.1+dfsg/scripts/hxtool-conv.pl-106- # :ref:`anchorname`
qemu-5.1+dfsg/scripts/hxtool-conv.pl:107: $rst =~ s/\`[^<`]+\<\#([^>]+)\>\`__/:ref:`$1`/gm;
qemu-5.1+dfsg/scripts/hxtool-conv.pl-108- print $rst;
##############################################
qemu-5.1+dfsg/scripts/kernel-doc-247-my @highlights_rst = (
qemu-5.1+dfsg/scripts/kernel-doc:248: [$type_constant, "``\$1``"],
qemu-5.1+dfsg/scripts/kernel-doc:249: [$type_constant2, "``\$1``"],
qemu-5.1+dfsg/scripts/kernel-doc-250- # Note: need to escape () to avoid func matching later
qemu-5.1+dfsg/scripts/kernel-doc:251: [$type_member_func, "\\:c\\:type\\:`\$1\$2\$3\\\\(\\\\) <\$1>`"],
qemu-5.1+dfsg/scripts/kernel-doc:252: [$type_member, "\\:c\\:type\\:`\$1\$2\$3 <\$1>`"],
qemu-5.1+dfsg/scripts/kernel-doc-253- [$type_fp_param, "**\$1\\\\(\\\\)**"],
qemu-5.1+dfsg/scripts/kernel-doc-254- [$type_func, "\$1()"],
qemu-5.1+dfsg/scripts/kernel-doc:255: [$type_enum, "\\:c\\:type\\:`\$1 <\$2>`"],
qemu-5.1+dfsg/scripts/kernel-doc:256: [$type_struct, "\\:c\\:type\\:`\$1 <\$2>`"],
qemu-5.1+dfsg/scripts/kernel-doc:257: [$type_typedef, "\\:c\\:type\\:`\$1 <\$2>`"],
qemu-5.1+dfsg/scripts/kernel-doc:258: [$type_union, "\\:c\\:type\\:`\$1 <\$2>`"],
qemu-5.1+dfsg/scripts/kernel-doc-259- # in rst this can refer to any type
qemu-5.1+dfsg/scripts/kernel-doc:260: [$type_fallback, "\\:c\\:type\\:`\$1`"],
qemu-5.1+dfsg/scripts/kernel-doc-261- [$type_param, "**\$1**"]
##############################################
qemu-5.1+dfsg/scripts/kernel-doc-296-if (defined($ENV{'KBUILD_BUILD_TIMESTAMP'}) &&
qemu-5.1+dfsg/scripts/kernel-doc:297: (my $seconds = `date -d"${ENV{'KBUILD_BUILD_TIMESTAMP'}}" +%s`) ne '') {
qemu-5.1+dfsg/scripts/kernel-doc-298- @build_time = gmtime($seconds);
##############################################
qemu-5.1+dfsg/scripts/kernel-doc-883- if ($type ne "") {
qemu-5.1+dfsg/scripts/kernel-doc:884: print "``$type $parameter``\n";
qemu-5.1+dfsg/scripts/kernel-doc-885- } else {
qemu-5.1+dfsg/scripts/kernel-doc:886: print "``$parameter``\n";
qemu-5.1+dfsg/scripts/kernel-doc-887- }
##############################################
qemu-5.1+dfsg/scripts/kernel-doc-935- foreach $parameter (@{$args{'parameterlist'}}) {
qemu-5.1+dfsg/scripts/kernel-doc:936: print "``$parameter``\n";
qemu-5.1+dfsg/scripts/kernel-doc-937- if ($args{'parameterdescs'}{$parameter} ne $undescribed) {
##############################################
qemu-5.1+dfsg/scripts/kernel-doc-1002- print_lineno($parameterdesc_start_lines{$parameter_name});
qemu-5.1+dfsg/scripts/kernel-doc:1003: print "``" . $parameter . "``\n";
qemu-5.1+dfsg/scripts/kernel-doc-1004- output_highlight_rst($args{'parameterdescs'}{$parameter_name});
##############################################
qemu-5.1+dfsg/scripts/qemugdb/coroutine.py-19- # %rsp - 120 is scratch space according to the SystemV ABI
qemu-5.1+dfsg/scripts/qemugdb/coroutine.py:20: old = gdb.parse_and_eval('*(uint64_t*)($rsp - 120)')
qemu-5.1+dfsg/scripts/qemugdb/coroutine.py-21- gdb.execute('call (int)arch_prctl(0x1003, $rsp - 120)', False, True)
qemu-5.1+dfsg/scripts/qemugdb/coroutine.py:22: fs_base = gdb.parse_and_eval('*(uint64_t*)($rsp - 120)')
qemu-5.1+dfsg/scripts/qemugdb/coroutine.py-23- gdb.execute('set *(uint64_t*)($rsp - 120) = %s' % old, False, True)
##############################################
qemu-5.1+dfsg/scripts/qemugdb/coroutine.py-73- for i in regs:
qemu-5.1+dfsg/scripts/qemugdb/coroutine.py:74: old[i] = gdb.parse_and_eval('(uint64_t)$%s' % i)
qemu-5.1+dfsg/scripts/qemugdb/coroutine.py-75-
##############################################
qemu-5.1+dfsg/scripts/switch-timer-api-56- {
qemu-5.1+dfsg/scripts/switch-timer-api:57: @files = split(/\s+/, `$getfiles`);
qemu-5.1+dfsg/scripts/switch-timer-api-58- }
##############################################
qemu-5.1+dfsg/softmmu/memory.c-401-
qemu-5.1+dfsg/softmmu/memory.c:402:static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
qemu-5.1+dfsg/softmmu/memory.c-403-{
##############################################
qemu-5.1+dfsg/softmmu/memory.c-437- } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
qemu-5.1+dfsg/softmmu/memory.c:438: hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
qemu-5.1+dfsg/softmmu/memory.c-439- trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
##############################################
qemu-5.1+dfsg/softmmu/memory.c-459- } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
qemu-5.1+dfsg/softmmu/memory.c:460: hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
qemu-5.1+dfsg/softmmu/memory.c-461- trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
##############################################
qemu-5.1+dfsg/softmmu/memory.c-479- } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
qemu-5.1+dfsg/softmmu/memory.c:480: hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
qemu-5.1+dfsg/softmmu/memory.c-481- trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
##############################################
qemu-5.1+dfsg/softmmu/memory.c-499- } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
qemu-5.1+dfsg/softmmu/memory.c:500: hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
qemu-5.1+dfsg/softmmu/memory.c-501- trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
##############################################
qemu-5.1+dfsg/softmmu/memory.c-1992- assert(mr->ram_block);
qemu-5.1+dfsg/softmmu/memory.c:1993: cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
qemu-5.1+dfsg/softmmu/memory.c-1994- size,
##############################################
qemu-5.1+dfsg/softmmu/memory.c-2094- return cpu_physical_memory_snapshot_get_dirty(snap,
qemu-5.1+dfsg/softmmu/memory.c:2095: memory_region_get_ram_addr(mr) + addr, size);
qemu-5.1+dfsg/softmmu/memory.c-2096-}
##############################################
qemu-5.1+dfsg/softmmu/memory.c-2132- cpu_physical_memory_test_and_clear_dirty(
qemu-5.1+dfsg/softmmu/memory.c:2133: memory_region_get_ram_addr(mr) + addr, size, client);
qemu-5.1+dfsg/softmmu/memory.c-2134-}
##############################################
qemu-5.1+dfsg/softmmu/memory.c-2176-
qemu-5.1+dfsg/softmmu/memory.c:2177:ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
qemu-5.1+dfsg/softmmu/memory.c-2178-{
##############################################
qemu-5.1+dfsg/softmmu/memory.c-2491-
qemu-5.1+dfsg/softmmu/memory.c:2492:static int cmp_flatrange_addr(const void *addr_, const void *fr_)
qemu-5.1+dfsg/softmmu/memory.c-2493-{
##############################################
qemu-5.1+dfsg/stubs/ram-block.c-4-
qemu-5.1+dfsg/stubs/ram-block.c:5:void *qemu_ram_get_host_addr(RAMBlock *rb)
qemu-5.1+dfsg/stubs/ram-block.c-6-{
##############################################
qemu-5.1+dfsg/target/alpha/cpu.h-328- PTE_FOE = 0x0008, /* used for page protection (fault on exec) */
qemu-5.1+dfsg/target/alpha/cpu.h:329: PTE_ASM = 0x0010,
qemu-5.1+dfsg/target/alpha/cpu.h-330- PTE_KRE = 0x0100,
##############################################
qemu-5.1+dfsg/target/arm/helper-a64.c-557-
qemu-5.1+dfsg/target/arm/helper-a64.c:558: set_helper_retaddr(ra);
qemu-5.1+dfsg/target/arm/helper-a64.c-559- o0 = ldq_le_p(haddr + 0);
##############################################
qemu-5.1+dfsg/target/arm/helper-a64.c-567- }
qemu-5.1+dfsg/target/arm/helper-a64.c:568: clear_helper_retaddr();
qemu-5.1+dfsg/target/arm/helper-a64.c-569-#else
##############################################
qemu-5.1+dfsg/target/arm/helper-a64.c-627-
qemu-5.1+dfsg/target/arm/helper-a64.c:628: set_helper_retaddr(ra);
qemu-5.1+dfsg/target/arm/helper-a64.c-629- o1 = ldq_be_p(haddr + 0);
##############################################
qemu-5.1+dfsg/target/arm/helper-a64.c-637- }
qemu-5.1+dfsg/target/arm/helper-a64.c:638: clear_helper_retaddr();
qemu-5.1+dfsg/target/arm/helper-a64.c-639-#else
##############################################
qemu-5.1+dfsg/target/arm/helper.c-3375-#ifndef CONFIG_USER_ONLY
qemu-5.1+dfsg/target/arm/helper.c:3376:/* get_phys_addr() isn't present for user-mode-only targets */
qemu-5.1+dfsg/target/arm/helper.c-3377-
##############################################
qemu-5.1+dfsg/target/arm/helper.c-3410-
qemu-5.1+dfsg/target/arm/helper.c:3411: ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
qemu-5.1+dfsg/target/arm/helper.c-3412- &prot, &page_size, &fi, &cacheattrs);
##############################################
qemu-5.1+dfsg/target/arm/helper.c-12014- */
qemu-5.1+dfsg/target/arm/helper.c:12015:bool get_phys_addr(CPUARMState *env, target_ulong address,
qemu-5.1+dfsg/target/arm/helper.c-12016- MMUAccessType access_type, ARMMMUIdx mmu_idx,
##############################################
qemu-5.1+dfsg/target/arm/helper.c-12032-
qemu-5.1+dfsg/target/arm/helper.c:12033: ret = get_phys_addr(env, address, access_type,
qemu-5.1+dfsg/target/arm/helper.c-12034- stage_1_mmu_idx(mmu_idx), &ipa, attrs,
##############################################
qemu-5.1+dfsg/target/arm/helper.c-12224-
qemu-5.1+dfsg/target/arm/helper.c:12225: ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
qemu-5.1+dfsg/target/arm/helper.c-12226- attrs, &prot, &page_size, &fi, &cacheattrs);
##############################################
qemu-5.1+dfsg/target/arm/internals.h-83- * M profile cores don't have A/R format FSRs, but currently our
qemu-5.1+dfsg/target/arm/internals.h:84: * get_phys_addr() code assumes A/R profile and reports failures via
qemu-5.1+dfsg/target/arm/internals.h-85- * an A/R format FSR value. We then translate that into the proper
##############################################
qemu-5.1+dfsg/target/arm/internals.h-1292-
qemu-5.1+dfsg/target/arm/internals.h:1293:bool get_phys_addr(CPUARMState *env, target_ulong address,
qemu-5.1+dfsg/target/arm/internals.h-1294- MMUAccessType access_type, ARMMMUIdx mmu_idx,
##############################################
qemu-5.1+dfsg/target/arm/internals.h-1333-
qemu-5.1+dfsg/target/arm/internals.h:1334:static inline int allocation_tag_from_addr(uint64_t ptr)
qemu-5.1+dfsg/target/arm/internals.h-1335-{
##############################################
qemu-5.1+dfsg/target/arm/kvm.c-318-
qemu-5.1+dfsg/target/arm/kvm.c:319:static void kvm_arm_set_device_addr(KVMDevice *kd)
qemu-5.1+dfsg/target/arm/kvm.c-320-{
##############################################
qemu-5.1+dfsg/target/arm/kvm.c-349- if (kd->kda.addr != -1) {
qemu-5.1+dfsg/target/arm/kvm.c:350: kvm_arm_set_device_addr(kd);
qemu-5.1+dfsg/target/arm/kvm.c-351- }
##############################################
qemu-5.1+dfsg/target/arm/m_helper.c-194-
qemu-5.1+dfsg/target/arm/m_helper.c:195: if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr,
qemu-5.1+dfsg/target/arm/m_helper.c-196- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
##############################################
qemu-5.1+dfsg/target/arm/m_helper.c-288-
qemu-5.1+dfsg/target/arm/m_helper.c:289: if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
qemu-5.1+dfsg/target/arm/m_helper.c-290- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
##############################################
qemu-5.1+dfsg/target/arm/m_helper.c-674- /*
qemu-5.1+dfsg/target/arm/m_helper.c:675: * We don't do a get_phys_addr() here because the rules for vector
qemu-5.1+dfsg/target/arm/m_helper.c-676- * loads are special: they always use the default memory map, and
##############################################
qemu-5.1+dfsg/target/arm/m_helper.c-1950- }
qemu-5.1+dfsg/target/arm/m_helper.c:1951: if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr,
qemu-5.1+dfsg/target/arm/m_helper.c-1952- &attrs, &prot, &page_size, &fi, &cacheattrs)) {
##############################################
qemu-5.1+dfsg/target/arm/mte_helper.c-205- if (tag_access == MMU_DATA_STORE) {
qemu-5.1+dfsg/target/arm/mte_helper.c:206: ram_addr_t tag_ra = memory_region_get_ram_addr(mr) + xlat;
qemu-5.1+dfsg/target/arm/mte_helper.c-207- cpu_physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION);
##############################################
qemu-5.1+dfsg/target/arm/mte_helper.c-264-{
qemu-5.1+dfsg/target/arm/mte_helper.c:265: int start_tag = allocation_tag_from_addr(ptr);
qemu-5.1+dfsg/target/arm/mte_helper.c-266- uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16);
##############################################
qemu-5.1+dfsg/target/arm/mte_helper.c-343- if (mem) {
qemu-5.1+dfsg/target/arm/mte_helper.c:344: store1(ptr, mem, allocation_tag_from_addr(xt));
qemu-5.1+dfsg/target/arm/mte_helper.c-345- }
##############################################
qemu-5.1+dfsg/target/arm/mte_helper.c-370- int mmu_idx = cpu_mmu_index(env, false);
qemu-5.1+dfsg/target/arm/mte_helper.c:371: int tag = allocation_tag_from_addr(xt);
qemu-5.1+dfsg/target/arm/mte_helper.c-372- uint8_t *mem1, *mem2;
##############################################
qemu-5.1+dfsg/target/arm/mte_helper.c-592-
qemu-5.1+dfsg/target/arm/mte_helper.c:593: ptr_tag = allocation_tag_from_addr(ptr);
qemu-5.1+dfsg/target/arm/mte_helper.c-594-
##############################################
qemu-5.1+dfsg/target/arm/mte_helper.c-737-
qemu-5.1+dfsg/target/arm/mte_helper.c:738: ptr_tag = allocation_tag_from_addr(ptr);
qemu-5.1+dfsg/target/arm/mte_helper.c-739-
##############################################
qemu-5.1+dfsg/target/arm/mte_helper.c-843-
qemu-5.1+dfsg/target/arm/mte_helper.c:844: ptr_tag = allocation_tag_from_addr(ptr);
qemu-5.1+dfsg/target/arm/mte_helper.c-845-
##############################################
qemu-5.1+dfsg/target/arm/sve_helper.c-4645- if (!tbi_check(desc, bit55) ||
qemu-5.1+dfsg/target/arm/sve_helper.c:4646: tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
qemu-5.1+dfsg/target/arm/sve_helper.c-4647- mtedesc = 0;
##############################################
qemu-5.1+dfsg/target/arm/sve_helper.c-5002- if (!tbi_check(desc, bit55) ||
qemu-5.1+dfsg/target/arm/sve_helper.c:5003: tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
qemu-5.1+dfsg/target/arm/sve_helper.c-5004- mtedesc = 0;
##############################################
qemu-5.1+dfsg/target/arm/sve_helper.c-5257- if (!tbi_check(desc, bit55) ||
qemu-5.1+dfsg/target/arm/sve_helper.c:5258: tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
qemu-5.1+dfsg/target/arm/sve_helper.c-5259- mtedesc = 0;
##############################################
qemu-5.1+dfsg/target/arm/tlb_helper.c-176- */
qemu-5.1+dfsg/target/arm/tlb_helper.c:177: ret = get_phys_addr(&cpu->env, address, access_type,
qemu-5.1+dfsg/target/arm/tlb_helper.c-178- core_to_arm_mmu_idx(&cpu->env, mmu_idx),
##############################################
qemu-5.1+dfsg/target/arm/translate.c-886-
qemu-5.1+dfsg/target/arm/translate.c:887:static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
qemu-5.1+dfsg/target/arm/translate.c-888-{
##############################################
qemu-5.1+dfsg/target/arm/translate.c-908-
qemu-5.1+dfsg/target/arm/translate.c:909: addr = gen_aa32_addr(s, a32, opc);
qemu-5.1+dfsg/target/arm/translate.c-910- tcg_gen_qemu_ld_i32(val, addr, index, opc);
##############################################
qemu-5.1+dfsg/target/arm/translate.c-923-
qemu-5.1+dfsg/target/arm/translate.c:924: addr = gen_aa32_addr(s, a32, opc);
qemu-5.1+dfsg/target/arm/translate.c-925- tcg_gen_qemu_st_i32(val, addr, index, opc);
##############################################
qemu-5.1+dfsg/target/arm/translate.c-953-{
qemu-5.1+dfsg/target/arm/translate.c:954: TCGv addr = gen_aa32_addr(s, a32, opc);
qemu-5.1+dfsg/target/arm/translate.c-955- tcg_gen_qemu_ld_i64(val, addr, index, opc);
##############################################
qemu-5.1+dfsg/target/arm/translate.c-968-{
qemu-5.1+dfsg/target/arm/translate.c:969: TCGv addr = gen_aa32_addr(s, a32, opc);
qemu-5.1+dfsg/target/arm/translate.c-970-
##############################################
qemu-5.1+dfsg/target/arm/translate.c-4892- */
qemu-5.1+dfsg/target/arm/translate.c:4893: TCGv taddr = gen_aa32_addr(s, addr, opc);
qemu-5.1+dfsg/target/arm/translate.c-4894-
##############################################
qemu-5.1+dfsg/target/arm/translate.c-4942-
qemu-5.1+dfsg/target/arm/translate.c:4943: taddr = gen_aa32_addr(s, addr, opc);
qemu-5.1+dfsg/target/arm/translate.c-4944- t0 = tcg_temp_new_i32();
##############################################
qemu-5.1+dfsg/target/arm/translate.c-6606- addr = load_reg(s, a->rn);
qemu-5.1+dfsg/target/arm/translate.c:6607: taddr = gen_aa32_addr(s, addr, opc);
qemu-5.1+dfsg/target/arm/translate.c-6608- tcg_temp_free_i32(addr);
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1549- */
qemu-5.1+dfsg/target/avr/translate.c:1550:static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L)
qemu-5.1+dfsg/target/avr/translate.c-1551-{
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1560-
qemu-5.1+dfsg/target/avr/translate.c:1561:static void gen_set_xaddr(TCGv addr)
qemu-5.1+dfsg/target/avr/translate.c-1562-{
qemu-5.1+dfsg/target/avr/translate.c:1563: gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]);
qemu-5.1+dfsg/target/avr/translate.c-1564-}
qemu-5.1+dfsg/target/avr/translate.c-1565-
qemu-5.1+dfsg/target/avr/translate.c:1566:static void gen_set_yaddr(TCGv addr)
qemu-5.1+dfsg/target/avr/translate.c-1567-{
qemu-5.1+dfsg/target/avr/translate.c:1568: gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]);
qemu-5.1+dfsg/target/avr/translate.c-1569-}
qemu-5.1+dfsg/target/avr/translate.c-1570-
qemu-5.1+dfsg/target/avr/translate.c:1571:static void gen_set_zaddr(TCGv addr)
qemu-5.1+dfsg/target/avr/translate.c-1572-{
qemu-5.1+dfsg/target/avr/translate.c:1573: gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]);
qemu-5.1+dfsg/target/avr/translate.c-1574-}
qemu-5.1+dfsg/target/avr/translate.c-1575-
qemu-5.1+dfsg/target/avr/translate.c:1576:static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L)
qemu-5.1+dfsg/target/avr/translate.c-1577-{
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1585-
qemu-5.1+dfsg/target/avr/translate.c:1586:static TCGv gen_get_xaddr(void)
qemu-5.1+dfsg/target/avr/translate.c-1587-{
qemu-5.1+dfsg/target/avr/translate.c:1588: return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]);
qemu-5.1+dfsg/target/avr/translate.c-1589-}
qemu-5.1+dfsg/target/avr/translate.c-1590-
qemu-5.1+dfsg/target/avr/translate.c:1591:static TCGv gen_get_yaddr(void)
qemu-5.1+dfsg/target/avr/translate.c-1592-{
qemu-5.1+dfsg/target/avr/translate.c:1593: return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]);
qemu-5.1+dfsg/target/avr/translate.c-1594-}
qemu-5.1+dfsg/target/avr/translate.c-1595-
qemu-5.1+dfsg/target/avr/translate.c:1596:static TCGv gen_get_zaddr(void)
qemu-5.1+dfsg/target/avr/translate.c-1597-{
qemu-5.1+dfsg/target/avr/translate.c:1598: return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]);
qemu-5.1+dfsg/target/avr/translate.c-1599-}
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1738- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:1739: TCGv addr = gen_get_xaddr();
qemu-5.1+dfsg/target/avr/translate.c-1740-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1750- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:1751: TCGv addr = gen_get_xaddr();
qemu-5.1+dfsg/target/avr/translate.c-1752-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1755-
qemu-5.1+dfsg/target/avr/translate.c:1756: gen_set_xaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-1757-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1765- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:1766: TCGv addr = gen_get_xaddr();
qemu-5.1+dfsg/target/avr/translate.c-1767-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1769- gen_data_load(ctx, Rd, addr);
qemu-5.1+dfsg/target/avr/translate.c:1770: gen_set_xaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-1771-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1804- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:1805: TCGv addr = gen_get_yaddr();
qemu-5.1+dfsg/target/avr/translate.c-1806-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1809-
qemu-5.1+dfsg/target/avr/translate.c:1810: gen_set_yaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-1811-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1819- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:1820: TCGv addr = gen_get_yaddr();
qemu-5.1+dfsg/target/avr/translate.c-1821-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1823- gen_data_load(ctx, Rd, addr);
qemu-5.1+dfsg/target/avr/translate.c:1824: gen_set_yaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-1825-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1833- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:1834: TCGv addr = gen_get_yaddr();
qemu-5.1+dfsg/target/avr/translate.c-1835-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1875- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:1876: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-1877-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1880-
qemu-5.1+dfsg/target/avr/translate.c:1881: gen_set_zaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-1882-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1890- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:1891: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-1892-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1895-
qemu-5.1+dfsg/target/avr/translate.c:1896: gen_set_zaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-1897-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1905- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:1906: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-1907-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1968- TCGv Rd = cpu_r[a->rr];
qemu-5.1+dfsg/target/avr/translate.c:1969: TCGv addr = gen_get_xaddr();
qemu-5.1+dfsg/target/avr/translate.c-1970-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1980- TCGv Rd = cpu_r[a->rr];
qemu-5.1+dfsg/target/avr/translate.c:1981: TCGv addr = gen_get_xaddr();
qemu-5.1+dfsg/target/avr/translate.c-1982-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1984- tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
qemu-5.1+dfsg/target/avr/translate.c:1985: gen_set_xaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-1986-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1994- TCGv Rd = cpu_r[a->rr];
qemu-5.1+dfsg/target/avr/translate.c:1995: TCGv addr = gen_get_xaddr();
qemu-5.1+dfsg/target/avr/translate.c-1996-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-1998- gen_data_store(ctx, Rd, addr);
qemu-5.1+dfsg/target/avr/translate.c:1999: gen_set_xaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-2000-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2031- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2032: TCGv addr = gen_get_yaddr();
qemu-5.1+dfsg/target/avr/translate.c-2033-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2035- tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
qemu-5.1+dfsg/target/avr/translate.c:2036: gen_set_yaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-2037-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2045- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2046: TCGv addr = gen_get_yaddr();
qemu-5.1+dfsg/target/avr/translate.c-2047-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2049- gen_data_store(ctx, Rd, addr);
qemu-5.1+dfsg/target/avr/translate.c:2050: gen_set_yaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-2051-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2059- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2060: TCGv addr = gen_get_yaddr();
qemu-5.1+dfsg/target/avr/translate.c-2061-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2095- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2096: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2097-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2100-
qemu-5.1+dfsg/target/avr/translate.c:2101: gen_set_zaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-2102-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2110- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2111: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2112-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2115-
qemu-5.1+dfsg/target/avr/translate.c:2116: gen_set_zaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-2117-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2125- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2126: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2127-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2235- TCGv Rd = cpu_r[0];
qemu-5.1+dfsg/target/avr/translate.c:2236: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2237-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2251- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2252: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2253-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2267- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2268: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2269-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2271- tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
qemu-5.1+dfsg/target/avr/translate.c:2272: gen_set_zaddr(addr);
qemu-5.1+dfsg/target/avr/translate.c-2273-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2409- TCGv t0 = tcg_temp_new_i32();
qemu-5.1+dfsg/target/avr/translate.c:2410: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2411-
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2439- TCGv Rr = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2440: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2441- TCGv t0 = tcg_temp_new_i32();
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2474- TCGv Rr = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2475: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2476- TCGv t0 = tcg_temp_new_i32();
##############################################
qemu-5.1+dfsg/target/avr/translate.c-2509- TCGv Rd = cpu_r[a->rd];
qemu-5.1+dfsg/target/avr/translate.c:2510: TCGv addr = gen_get_zaddr();
qemu-5.1+dfsg/target/avr/translate.c-2511- TCGv t0 = tcg_temp_new_i32();
##############################################
qemu-5.1+dfsg/target/cris/mmu.c-68-
qemu-5.1+dfsg/target/cris/mmu.c:69:static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
qemu-5.1+dfsg/target/cris/mmu.c-70-{
##############################################
qemu-5.1+dfsg/target/cris/mmu.c-341- seg = vaddr >> 28;
qemu-5.1+dfsg/target/cris/mmu.c:342: if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) {
qemu-5.1+dfsg/target/cris/mmu.c-343- uint32_t base;
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-137-
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:138:static void crisv10_prepare_memaddr(DisasContext *dc,
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-139- TCGv addr, unsigned int size)
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-147-
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:148:static unsigned int crisv10_post_memaddr(DisasContext *dc, unsigned int size)
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-149-{
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-210- cris_flush_cc_state(dc);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:211: crisv10_prepare_memaddr(dc, addr, memsize);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-212- gen_load(dc, dst, addr, memsize, 0);
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-216- t_gen_zext(dst, dst, memsize);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:217: insn_len += crisv10_post_memaddr(dc, memsize);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-218- tcg_temp_free(addr);
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-776- addr = tcg_temp_new();
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:777: crisv10_prepare_memaddr(dc, addr, size);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-778- gen_store_v10(dc, addr, cpu_R[dc->dst], size);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:779: insn_len += crisv10_post_memaddr(dc, size);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-780-
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-816- addr = tcg_temp_new();
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:817: crisv10_prepare_memaddr(dc, addr, size);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-818- if (dc->dst == PR_CCS) {
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-827- t0 = tcg_temp_new();
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:828: insn_len += crisv10_post_memaddr(dc, size);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-829- cris_lock_irq(dc);
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-843- t0 = tcg_temp_new();
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:844: crisv10_prepare_memaddr(dc, addr, 4);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-845- tcg_gen_mov_tl(t0, addr);
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-875- t0 = tcg_temp_new();
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:876: crisv10_prepare_memaddr(dc, addr, 4);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-877- tcg_gen_mov_tl(t0, addr);
##############################################
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-1160- t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:1161: crisv10_prepare_memaddr(dc, t[0], size);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-1162- gen_load(dc, env_btarget, t[0], 4, 0);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c:1163: insn_len += crisv10_post_memaddr(dc, size);
qemu-5.1+dfsg/target/cris/translate_v10.inc.c-1164- cris_prepare_jmp(dc, JMP_INDIRECT);
##############################################
qemu-5.1+dfsg/target/i386/cpu.c-1545-#ifdef __x86_64__
qemu-5.1+dfsg/target/i386/cpu.c:1546: asm volatile("cpuid"
qemu-5.1+dfsg/target/i386/cpu.c-1547- : "=a"(vec[0]), "=b"(vec[1]),
##############################################
qemu-5.1+dfsg/target/i386/cpu.c-1550-#elif defined(__i386__)
qemu-5.1+dfsg/target/i386/cpu.c:1551: asm volatile("pusha \n\t"
qemu-5.1+dfsg/target/i386/cpu.c-1552- "cpuid \n\t"
##############################################
qemu-5.1+dfsg/target/i386/cpu.h-895-#define MSR_VMX_EPT_INVVPID (1ULL << 32)
qemu-5.1+dfsg/target/i386/cpu.h:896:#define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
qemu-5.1+dfsg/target/i386/cpu.h-897-#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86.c-161-
qemu-5.1+dfsg/target/i386/hvf/x86.c:162:target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, X86Seg seg)
qemu-5.1+dfsg/target/i386/hvf/x86.c-163-{
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86.c-179- }
qemu-5.1+dfsg/target/i386/hvf/x86.c:180: return linear_addr(cpu, addr, seg);
qemu-5.1+dfsg/target/i386/hvf/x86.c-181-}
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86.c-184-{
qemu-5.1+dfsg/target/i386/hvf/x86.c:185: return linear_addr(cpu, rip, R_CS);
qemu-5.1+dfsg/target/i386/hvf/x86.c-186-}
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c-1683- } else {
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c:1684: op->ptr = decode_linear_addr(env, decode, (uint16_t)ptr, seg);
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c-1685- }
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c-1785- } else {
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c:1786: op->ptr = decode_linear_addr(env, decode, (uint32_t)ptr, seg);
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c-1787- }
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c-1815- } else {
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c:1816: op->ptr = decode_linear_addr(env, decode, ptr, seg);
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c-1817- }
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c-2170-
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c:2171:target_ulong decode_linear_addr(CPUX86State *env, struct x86_decode *decode,
qemu-5.1+dfsg/target/i386/hvf/x86_decode.c-2172- target_ulong addr, X86Seg seg)
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_decode.h-311- struct x86_decode_op *op);
qemu-5.1+dfsg/target/i386/hvf/x86_decode.h:312:target_ulong decode_linear_addr(CPUX86State *env, struct x86_decode *decode,
qemu-5.1+dfsg/target/i386/hvf/x86_decode.h-313- target_ulong addr, enum X86Seg seg);
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-249- case X86_VAR_OFFSET:
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c:250: decode->op[i].ptr = decode_linear_addr(env, decode,
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-251- decode->op[i].ptr,
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-512-{
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c:513: target_ulong addr = decode_linear_addr(env, decode, RSI(env), R_DS);
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-514-
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-539-
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c:540: src_addr = decode_linear_addr(env, decode, RSI(env), R_DS);
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-541- dst_addr = linear_addr_size(env_cpu(env), RDI(env),
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-566-
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c:567: src_addr = decode_linear_addr(env, decode, RSI(env), R_DS);
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-568- dst_addr = linear_addr_size(env_cpu(env), RDI(env),
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-648-
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c:649: addr = decode_linear_addr(env, decode, RSI(env), R_DS);
qemu-5.1+dfsg/target/i386/hvf/x86_emu.c-650- vmx_read_mem(env_cpu(env), &val, addr, decode->operand_size);
##############################################
qemu-5.1+dfsg/target/i386/hvf/x86.h-304-enum X86Seg;
qemu-5.1+dfsg/target/i386/hvf/x86.h:305:target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, enum X86Seg seg);
qemu-5.1+dfsg/target/i386/hvf/x86.h-306-target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size,
##############################################
qemu-5.1+dfsg/target/microblaze/translate.c-846-
qemu-5.1+dfsg/target/microblaze/translate.c:847:static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t)
qemu-5.1+dfsg/target/microblaze/translate.c-848-{
##############################################
qemu-5.1+dfsg/target/microblaze/translate.c-950- addr = tcg_temp_new();
qemu-5.1+dfsg/target/microblaze/translate.c:951: compute_ldst_addr(dc, ea, addr);
qemu-5.1+dfsg/target/microblaze/translate.c-952- /* Extended addressing bypasses the MMU. */
##############################################
qemu-5.1+dfsg/target/microblaze/translate.c-1063- addr = ex ? tcg_temp_local_new() : tcg_temp_new();
qemu-5.1+dfsg/target/microblaze/translate.c:1064: compute_ldst_addr(dc, ea, addr);
qemu-5.1+dfsg/target/microblaze/translate.c-1065- /* Extended addressing bypasses the MMU. */
##############################################
qemu-5.1+dfsg/target/mips/cp0_helper.c-390-
qemu-5.1+dfsg/target/mips/cp0_helper.c:391:target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
qemu-5.1+dfsg/target/mips/cp0_helper.c-392-{
##############################################
qemu-5.1+dfsg/target/mips/cp0_helper.c-473-
qemu-5.1+dfsg/target/mips/cp0_helper.c:474:target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
qemu-5.1+dfsg/target/mips/cp0_helper.c-475-{
##############################################
qemu-5.1+dfsg/target/mips/cp0_helper.c-1308-
qemu-5.1+dfsg/target/mips/cp0_helper.c:1309:void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
qemu-5.1+dfsg/target/mips/cp0_helper.c-1310-{
##############################################
qemu-5.1+dfsg/target/mips/kvm.c-836- if (err < 0) {
qemu-5.1+dfsg/target/mips/kvm.c:837: DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
qemu-5.1+dfsg/target/mips/kvm.c-838- ret = err;
##############################################
qemu-5.1+dfsg/target/mips/kvm.c-1057- if (err < 0) {
qemu-5.1+dfsg/target/mips/kvm.c:1058: DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
qemu-5.1+dfsg/target/mips/kvm.c-1059- ret = err;
##############################################
qemu-5.1+dfsg/target/mips/translate.c-3389-
qemu-5.1+dfsg/target/mips/translate.c:3390:static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
qemu-5.1+dfsg/target/mips/translate.c-3391- int base, int offset)
##############################################
qemu-5.1+dfsg/target/mips/translate.c-3434- t0 = tcg_temp_new();
qemu-5.1+dfsg/target/mips/translate.c:3435: gen_base_offset_addr(ctx, t0, base, offset);
qemu-5.1+dfsg/target/mips/translate.c-3436-
##############################################
qemu-5.1+dfsg/target/mips/translate.c-3632-
qemu-5.1+dfsg/target/mips/translate.c:3633: gen_base_offset_addr(ctx, taddr, base, offset);
qemu-5.1+dfsg/target/mips/translate.c-3634- tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-3657-
qemu-5.1+dfsg/target/mips/translate.c:3658: gen_base_offset_addr(ctx, t0, base, offset);
qemu-5.1+dfsg/target/mips/translate.c-3659- gen_load_gpr(t1, rt);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-3721- /* compare the address against that of the preceeding LL */
qemu-5.1+dfsg/target/mips/translate.c:3722: gen_base_offset_addr(ctx, addr, base, offset);
qemu-5.1+dfsg/target/mips/translate.c-3723- tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-3756-
qemu-5.1+dfsg/target/mips/translate.c:3757: gen_base_offset_addr(ctx, taddr, base, offset);
qemu-5.1+dfsg/target/mips/translate.c-3758-
##############################################
qemu-5.1+dfsg/target/mips/translate.c-3853- default:
qemu-5.1+dfsg/target/mips/translate.c:3854: gen_base_offset_addr(ctx, t0, rs, imm);
qemu-5.1+dfsg/target/mips/translate.c-3855- gen_flt_ldst(ctx, op, rt, t0);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-7462- case CP0_REG17__LLADDR:
qemu-5.1+dfsg/target/mips/translate.c:7463: gen_helper_mfc0_lladdr(arg, cpu_env);
qemu-5.1+dfsg/target/mips/translate.c-7464- register_name = "LLAddr";
##############################################
qemu-5.1+dfsg/target/mips/translate.c-8208- case CP0_REG17__LLADDR:
qemu-5.1+dfsg/target/mips/translate.c:8209: gen_helper_mtc0_lladdr(cpu_env, arg);
qemu-5.1+dfsg/target/mips/translate.c-8210- register_name = "LLAddr";
##############################################
qemu-5.1+dfsg/target/mips/translate.c-8962- case CP0_REG17__LLADDR:
qemu-5.1+dfsg/target/mips/translate.c:8963: gen_helper_dmfc0_lladdr(arg, cpu_env);
qemu-5.1+dfsg/target/mips/translate.c-8964- register_name = "LLAddr";
##############################################
qemu-5.1+dfsg/target/mips/translate.c-9692- case CP0_REG17__LLADDR:
qemu-5.1+dfsg/target/mips/translate.c:9693: gen_helper_mtc0_lladdr(cpu_env, arg);
qemu-5.1+dfsg/target/mips/translate.c-9694- register_name = "LLAddr";
##############################################
qemu-5.1+dfsg/target/mips/translate.c-13572- case 4:
qemu-5.1+dfsg/target/mips/translate.c:13573: gen_base_offset_addr(ctx, t0, 29, 12);
qemu-5.1+dfsg/target/mips/translate.c-13574- gen_load_gpr(t1, 7);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-13577- case 3:
qemu-5.1+dfsg/target/mips/translate.c:13578: gen_base_offset_addr(ctx, t0, 29, 8);
qemu-5.1+dfsg/target/mips/translate.c-13579- gen_load_gpr(t1, 6);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-13582- case 2:
qemu-5.1+dfsg/target/mips/translate.c:13583: gen_base_offset_addr(ctx, t0, 29, 4);
qemu-5.1+dfsg/target/mips/translate.c-13584- gen_load_gpr(t1, 5);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-13587- case 1:
qemu-5.1+dfsg/target/mips/translate.c:13588: gen_base_offset_addr(ctx, t0, 29, 0);
qemu-5.1+dfsg/target/mips/translate.c-13589- gen_load_gpr(t1, 4);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-13819- TCGv t1 = tcg_temp_new();
qemu-5.1+dfsg/target/mips/translate.c:13820: gen_base_offset_addr(ctx, t1, base, offset);
qemu-5.1+dfsg/target/mips/translate.c-13821- gen_helper_cache(cpu_env, t1, t0);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-15268-
qemu-5.1+dfsg/target/mips/translate.c:15269: gen_base_offset_addr(ctx, t0, base, offset);
qemu-5.1+dfsg/target/mips/translate.c-15270-
##############################################
qemu-5.1+dfsg/target/mips/translate.c-15567-
qemu-5.1+dfsg/target/mips/translate.c:15568: gen_base_offset_addr(ctx, t0, base, offset);
qemu-5.1+dfsg/target/mips/translate.c-15569-
##############################################
qemu-5.1+dfsg/target/mips/translate.c-18875- int this_offset = -((counter + 1) << 2);
qemu-5.1+dfsg/target/mips/translate.c:18876: gen_base_offset_addr(ctx, va, 29, this_offset);
qemu-5.1+dfsg/target/mips/translate.c-18877- gen_load_gpr(t0, this_rt);
##############################################
qemu-5.1+dfsg/target/mips/translate.c-18900- int this_offset = u - ((counter + 1) << 2);
qemu-5.1+dfsg/target/mips/translate.c:18901: gen_base_offset_addr(ctx, va, 29, this_offset);
qemu-5.1+dfsg/target/mips/translate.c-18902- tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL |
##############################################
qemu-5.1+dfsg/target/mips/translate.c-21892-
qemu-5.1+dfsg/target/mips/translate.c:21893: gen_base_offset_addr(ctx, t0, rs, s);
qemu-5.1+dfsg/target/mips/translate.c-21894-
##############################################
qemu-5.1+dfsg/target/mips/translate.c-22064-
qemu-5.1+dfsg/target/mips/translate.c:22065: gen_base_offset_addr(ctx, va, rs, this_offset);
qemu-5.1+dfsg/target/mips/translate.c-22066-
##############################################
qemu-5.1+dfsg/target/mips/translate.c-30175- TCGv taddr = tcg_temp_new();
qemu-5.1+dfsg/target/mips/translate.c:30176: gen_base_offset_addr(ctx, taddr, rs, s10 << df);
qemu-5.1+dfsg/target/mips/translate.c-30177-
##############################################
qemu-5.1+dfsg/target/mips/translate_init.inc.c-39-
qemu-5.1+dfsg/target/mips/translate_init.inc.c:40:/* No config4, no DSP ASE, no large physaddr (PABITS),
qemu-5.1+dfsg/target/mips/translate_init.inc.c-41- no external interrupt controller, no vectored interrupts,
##############################################
qemu-5.1+dfsg/target/nios2/cpu.h-103-#define CR_EXCEPTION (CR_BASE + 7)
qemu-5.1+dfsg/target/nios2/cpu.h:104:#define CR_PTEADDR (CR_BASE + 8)
qemu-5.1+dfsg/target/nios2/cpu.h-105-#define CR_PTEADDR_PTBASE_SHIFT 22
##############################################
qemu-5.1+dfsg/target/nios2/cpu.h-129-#define CR_ENCINJ (CR_BASE + 11)
qemu-5.1+dfsg/target/nios2/cpu.h:130:#define CR_BADADDR (CR_BASE + 12)
qemu-5.1+dfsg/target/nios2/cpu.h-131-#define CR_CONFIG (CR_BASE + 13)
##############################################
qemu-5.1+dfsg/target/ppc/cpu.h-1208- void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
qemu-5.1+dfsg/target/ppc/cpu.h:1209: hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
qemu-5.1+dfsg/target/ppc/cpu.h-1210- const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
##############################################
qemu-5.1+dfsg/target/ppc/kvm.c-2300-
qemu-5.1+dfsg/target/ppc/kvm.c:2301: asm ("mfpvr %0"
qemu-5.1+dfsg/target/ppc/kvm.c-2302- : "=r"(pvr));
##############################################
qemu-5.1+dfsg/target/ppc/kvm_ppc.h-444- if (kvm_enabled()) { \
qemu-5.1+dfsg/target/ppc/kvm_ppc.h:445: asm volatile("eieio" : : : "memory"); \
qemu-5.1+dfsg/target/ppc/kvm_ppc.h-446- } \
##############################################
qemu-5.1+dfsg/target/ppc/kvm_ppc.h-454- for (p = addr; p < addr + len; p += cpu->env.dcache_line_size) {
qemu-5.1+dfsg/target/ppc/kvm_ppc.h:455: asm volatile("dcbst 0,%0" : : "r"(p) : "memory");
qemu-5.1+dfsg/target/ppc/kvm_ppc.h-456- }
##############################################
qemu-5.1+dfsg/target/ppc/kvm_ppc.h-464- for (p = addr; p < addr + len; p += cpu->env.icache_line_size) {
qemu-5.1+dfsg/target/ppc/kvm_ppc.h:465: asm volatile("icbi 0,%0" : : "r"(p));
qemu-5.1+dfsg/target/ppc/kvm_ppc.h-466- }
##############################################
qemu-5.1+dfsg/target/ppc/mmu-hash32.c-405-
qemu-5.1+dfsg/target/ppc/mmu-hash32.c:406:static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
qemu-5.1+dfsg/target/ppc/mmu-hash32.c-407- target_ulong eaddr)
##############################################
qemu-5.1+dfsg/target/ppc/mmu-hash32.c-555-
qemu-5.1+dfsg/target/ppc/mmu-hash32.c:556: raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
qemu-5.1+dfsg/target/ppc/mmu-hash32.c-557-
##############################################
qemu-5.1+dfsg/target/ppc/mmu-hash32.c-595-
qemu-5.1+dfsg/target/ppc/mmu-hash32.c:596: return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
qemu-5.1+dfsg/target/ppc/mmu-hash32.c-597-}
##############################################
qemu-5.1+dfsg/target/ppc/mmu-radix64.c-30-
qemu-5.1+dfsg/target/ppc/mmu-radix64.c:31:static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env,
qemu-5.1+dfsg/target/ppc/mmu-radix64.c-32- vaddr eaddr,
##############################################
qemu-5.1+dfsg/target/ppc/mmu-radix64.c-451- /* Virtual Mode Access - get the fully qualified address */
qemu-5.1+dfsg/target/ppc/mmu-radix64.c:452: if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) {
qemu-5.1+dfsg/target/ppc/mmu-radix64.c-453- if (guest_visible) {
##############################################
qemu-5.1+dfsg/target/ppc/mmu-radix64.c-569-
qemu-5.1+dfsg/target/ppc/mmu-radix64.c:570: /* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
qemu-5.1+dfsg/target/ppc/mmu-radix64.c-571- if (ppc_radix64_xlate(cpu, eaddr, rwx, relocation, &raddr,
##############################################
qemu-5.1+dfsg/target/riscv/csr.c-625-
qemu-5.1+dfsg/target/riscv/csr.c:626:static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
qemu-5.1+dfsg/target/riscv/csr.c-627-{
##############################################
qemu-5.1+dfsg/target/riscv/csr.c-631-
qemu-5.1+dfsg/target/riscv/csr.c:632:static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
qemu-5.1+dfsg/target/riscv/csr.c-633-{
##############################################
qemu-5.1+dfsg/target/riscv/csr.c-765-
qemu-5.1+dfsg/target/riscv/csr.c:766:static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
qemu-5.1+dfsg/target/riscv/csr.c-767-{
##############################################
qemu-5.1+dfsg/target/riscv/csr.c-771-
qemu-5.1+dfsg/target/riscv/csr.c:772:static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
qemu-5.1+dfsg/target/riscv/csr.c-773-{
##############################################
qemu-5.1+dfsg/target/riscv/csr.c-1132-
qemu-5.1+dfsg/target/riscv/csr.c:1133:static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
qemu-5.1+dfsg/target/riscv/csr.c-1134-{
##############################################
qemu-5.1+dfsg/target/riscv/csr.c-1138-
qemu-5.1+dfsg/target/riscv/csr.c:1139:static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
qemu-5.1+dfsg/target/riscv/csr.c-1140-{
##############################################
qemu-5.1+dfsg/target/riscv/translate.c-101-
qemu-5.1+dfsg/target/riscv/translate.c:102:static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
qemu-5.1+dfsg/target/riscv/translate.c-103-{
##############################################
qemu-5.1+dfsg/target/riscv/translate.c-145-{
qemu-5.1+dfsg/target/riscv/translate.c:146: generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
qemu-5.1+dfsg/target/riscv/translate.c-147-}
##############################################
qemu-5.1+dfsg/target/riscv/vector_helper.c-481- */
qemu-5.1+dfsg/target/riscv/vector_helper.c:482:typedef target_ulong vext_get_index_addr(target_ulong base,
qemu-5.1+dfsg/target/riscv/vector_helper.c-483- uint32_t idx, void *vs2);
qemu-5.1+dfsg/target/riscv/vector_helper.c-484-
qemu-5.1+dfsg/target/riscv/vector_helper.c:485:#define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \
qemu-5.1+dfsg/target/riscv/vector_helper.c-486-static target_ulong NAME(target_ulong base, \
##############################################
qemu-5.1+dfsg/target/riscv/vector_helper.c-491-
qemu-5.1+dfsg/target/riscv/vector_helper.c:492:GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
qemu-5.1+dfsg/target/riscv/vector_helper.c:493:GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
qemu-5.1+dfsg/target/riscv/vector_helper.c:494:GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
qemu-5.1+dfsg/target/riscv/vector_helper.c:495:GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
qemu-5.1+dfsg/target/riscv/vector_helper.c-496-
##############################################
qemu-5.1+dfsg/target/riscv/vector_helper.c-516- }
qemu-5.1+dfsg/target/riscv/vector_helper.c:517: probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
qemu-5.1+dfsg/target/riscv/vector_helper.c-518- access_type);
##############################################
qemu-5.1+dfsg/target/riscv/vector_helper.c-526- while (k < nf) {
qemu-5.1+dfsg/target/riscv/vector_helper.c:527: abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
qemu-5.1+dfsg/target/riscv/vector_helper.c-528- ldst_elem(env, addr, i + k * vlmax, vd, ra);
##############################################
qemu-5.1+dfsg/target/riscv/vector_helper.c-793- }
qemu-5.1+dfsg/target/riscv/vector_helper.c:794: probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
qemu-5.1+dfsg/target/riscv/vector_helper.c:795: probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
qemu-5.1+dfsg/target/riscv/vector_helper.c-796- }
##############################################
qemu-5.1+dfsg/target/riscv/vector_helper.c-800- }
qemu-5.1+dfsg/target/riscv/vector_helper.c:801: addr = get_index_addr(base, i, vs2);
qemu-5.1+dfsg/target/riscv/vector_helper.c-802- noatomic_op(vs3, addr, wd, i, env, ra);
##############################################
qemu-5.1+dfsg/target/rx/disas.c-139-
qemu-5.1+dfsg/target/rx/disas.c:140:static void rx_index_addr(DisasContext *ctx, char out[8], int ld, int mi)
qemu-5.1+dfsg/target/rx/disas.c-141-{
##############################################
qemu-5.1+dfsg/target/rx/disas.c-178- if (ld < 3) {
qemu-5.1+dfsg/target/rx/disas.c:179: rx_index_addr(ctx, dsp, ld, mi);
qemu-5.1+dfsg/target/rx/disas.c-180- prt("%s\t%s[r%d]%s, r%d", insn, dsp, rs, sizes[mi], rd);
##############################################
qemu-5.1+dfsg/target/rx/disas.c-270- } else if (a->lds == 3) {
qemu-5.1+dfsg/target/rx/disas.c:271: rx_index_addr(ctx, dspd, a->ldd, a->sz);
qemu-5.1+dfsg/target/rx/disas.c-272- prt("mov.%c\tr%d, %s[r%d]", szc, a->rs, dspd, a->rd);
qemu-5.1+dfsg/target/rx/disas.c-273- } else if (a->ldd == 3) {
qemu-5.1+dfsg/target/rx/disas.c:274: rx_index_addr(ctx, dsps, a->lds, a->sz);
qemu-5.1+dfsg/target/rx/disas.c-275- prt("mov.%c\t%s[r%d], r%d", szc, dsps, a->rs, a->rd);
qemu-5.1+dfsg/target/rx/disas.c-276- } else {
qemu-5.1+dfsg/target/rx/disas.c:277: rx_index_addr(ctx, dsps, a->lds, a->sz);
qemu-5.1+dfsg/target/rx/disas.c:278: rx_index_addr(ctx, dspd, a->ldd, a->sz);
qemu-5.1+dfsg/target/rx/disas.c-279- prt("mov.%c\t%s[r%d], %s[r%d]", szc, dsps, a->rs, dspd, a->rd);
##############################################
qemu-5.1+dfsg/target/rx/disas.c-378-
qemu-5.1+dfsg/target/rx/disas.c:379: rx_index_addr(ctx, dsp, a->ld, a->sz);
qemu-5.1+dfsg/target/rx/disas.c-380- prt("push\t%s[r%d]", dsp, a->rs);
##############################################
qemu-5.1+dfsg/target/rx/disas.c-557-
qemu-5.1+dfsg/target/rx/disas.c:558: rx_index_addr(ctx, dsp, a->ld, 2);
qemu-5.1+dfsg/target/rx/disas.c-559- prt("adc\t%s[r%d], r%d", dsp, a->rs, a->rd);
##############################################
qemu-5.1+dfsg/target/rx/disas.c-1198- char dsp[8]; \
qemu-5.1+dfsg/target/rx/disas.c:1199: rx_index_addr(ctx, dsp, a->ld, RX_MEMORY_BYTE); \
qemu-5.1+dfsg/target/rx/disas.c-1200- prt("b%s\t#%d, %s[r%d]", #name, a->imm, dsp, reg); \
##############################################
qemu-5.1+dfsg/target/rx/disas.c-1206- char dsp[8]; \
qemu-5.1+dfsg/target/rx/disas.c:1207: rx_index_addr(ctx, dsp, a->ld, RX_MEMORY_BYTE); \
qemu-5.1+dfsg/target/rx/disas.c-1208- prt("b%s\tr%d, %s[r%d]", #name, a->rd, dsp, a->rs); \
##############################################
qemu-5.1+dfsg/target/rx/disas.c-1320-
qemu-5.1+dfsg/target/rx/disas.c:1321: rx_index_addr(ctx, dsp, a->ld, RX_MEMORY_BYTE);
qemu-5.1+dfsg/target/rx/disas.c-1322- prt("bm%s\t#%d, %s[r%d]", cond[a->cd], a->imm, dsp, a->rd);
##############################################
qemu-5.1+dfsg/target/rx/disas.c-1415- char dsp[8];
qemu-5.1+dfsg/target/rx/disas.c:1416: rx_index_addr(ctx, dsp, a->sz, a->ld);
qemu-5.1+dfsg/target/rx/disas.c-1417- prt("sc%s.%c\t%s[r%d]", cond[a->cd], size[a->sz], dsp, a->rd);
##############################################
qemu-5.1+dfsg/target/rx/translate.c-198-/* dsp[reg] */
qemu-5.1+dfsg/target/rx/translate.c:199:static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem,
qemu-5.1+dfsg/target/rx/translate.c-200- int ld, int size, int reg)
##############################################
qemu-5.1+dfsg/target/rx/translate.c-236- mop = mi_to_mop(mi);
qemu-5.1+dfsg/target/rx/translate.c:237: addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs);
qemu-5.1+dfsg/target/rx/translate.c-238- tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE);
##############################################
qemu-5.1+dfsg/target/rx/translate.c-515- /* mov.<bwl> rs,dsp[rd] */
qemu-5.1+dfsg/target/rx/translate.c:516: addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs);
qemu-5.1+dfsg/target/rx/translate.c-517- rx_gen_st(a->sz, cpu_regs[a->rd], addr);
##############################################
qemu-5.1+dfsg/target/rx/translate.c-519- /* mov.<bwl> dsp[rs],rd */
qemu-5.1+dfsg/target/rx/translate.c:520: addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs);
qemu-5.1+dfsg/target/rx/translate.c-521- rx_gen_ld(a->sz, cpu_regs[a->rd], addr);
##############################################
qemu-5.1+dfsg/target/rx/translate.c-524- tmp = tcg_temp_new();
qemu-5.1+dfsg/target/rx/translate.c:525: addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs);
qemu-5.1+dfsg/target/rx/translate.c-526- rx_gen_ld(a->sz, tmp, addr);
qemu-5.1+dfsg/target/rx/translate.c:527: addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd);
qemu-5.1+dfsg/target/rx/translate.c-528- rx_gen_st(a->sz, tmp, addr);
##############################################
qemu-5.1+dfsg/target/rx/translate.c-684- val = tcg_temp_new();
qemu-5.1+dfsg/target/rx/translate.c:685: addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs);
qemu-5.1+dfsg/target/rx/translate.c-686- rx_gen_ld(a->sz, val, addr);
##############################################
qemu-5.1+dfsg/target/rx/translate.c-741- case 2: /* dsp[rs].l */
qemu-5.1+dfsg/target/rx/translate.c:742: addr = rx_index_addr(ctx, mem, a->ld, a->mi, a->rs);
qemu-5.1+dfsg/target/rx/translate.c-743- break;
##############################################
qemu-5.1+dfsg/target/rx/translate.c-745- case 4: /* dsp[rs].ub */
qemu-5.1+dfsg/target/rx/translate.c:746: addr = rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs);
qemu-5.1+dfsg/target/rx/translate.c-747- break;
##############################################
qemu-5.1+dfsg/target/rx/translate.c-794- tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0);
qemu-5.1+dfsg/target/rx/translate.c:795: addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd);
qemu-5.1+dfsg/target/rx/translate.c-796- rx_gen_st(a->sz, val, addr);
##############################################
qemu-5.1+dfsg/target/rx/translate.c-2054- mask = tcg_const_i32(1 << a->imm); \
qemu-5.1+dfsg/target/rx/translate.c:2055: addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
qemu-5.1+dfsg/target/rx/translate.c-2056- cat3(rx_, op, m)(addr, mask); \
##############################################
qemu-5.1+dfsg/target/rx/translate.c-2091- mem = tcg_temp_new(); \
qemu-5.1+dfsg/target/rx/translate.c:2092: addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
qemu-5.1+dfsg/target/rx/translate.c-2093- cat3(rx_, op, m)(addr, mask); \
##############################################
qemu-5.1+dfsg/target/rx/translate.c-2124- mem = tcg_temp_new();
qemu-5.1+dfsg/target/rx/translate.c:2125: addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd);
qemu-5.1+dfsg/target/rx/translate.c-2126- rx_gen_ld(MO_8, val, addr);
##############################################
qemu-5.1+dfsg/target/s390x/translate.c-338-
qemu-5.1+dfsg/target/s390x/translate.c:339:static void update_psw_addr(DisasContext *s)
qemu-5.1+dfsg/target/s390x/translate.c-340-{
##############################################
qemu-5.1+dfsg/target/s390x/translate.c-445- /* update the psw */
qemu-5.1+dfsg/target/s390x/translate.c:446: update_psw_addr(s);
qemu-5.1+dfsg/target/s390x/translate.c-447-
##############################################
qemu-5.1+dfsg/target/s390x/translate.c-2505-
qemu-5.1+dfsg/target/s390x/translate.c:2506: update_psw_addr(s);
qemu-5.1+dfsg/target/s390x/translate.c-2507- update_cc_op(s);
##############################################
qemu-5.1+dfsg/target/s390x/translate.c-3239- if (tb_cflags(s->base.tb) & CF_PARALLEL) {
qemu-5.1+dfsg/target/s390x/translate.c:3240: update_psw_addr(s);
qemu-5.1+dfsg/target/s390x/translate.c-3241- update_cc_op(s);
##############################################
qemu-5.1+dfsg/target/s390x/translate.c-4508- if (s->base.tb->flags & FLAG_MASK_PER) {
qemu-5.1+dfsg/target/s390x/translate.c:4509: update_psw_addr(s);
qemu-5.1+dfsg/target/s390x/translate.c-4510- gen_helper_per_store_real(cpu_env);
##############################################
qemu-5.1+dfsg/target/s390x/translate.c-4728-
qemu-5.1+dfsg/target/s390x/translate.c:4729: update_psw_addr(s);
qemu-5.1+dfsg/target/s390x/translate.c-4730- update_cc_op(s);
##############################################
qemu-5.1+dfsg/target/s390x/translate.c-6511- case DISAS_PC_STALE_NOCHAIN:
qemu-5.1+dfsg/target/s390x/translate.c:6512: update_psw_addr(dc);
qemu-5.1+dfsg/target/s390x/translate.c-6513- /* FALLTHRU */
##############################################
qemu-5.1+dfsg/target/sh4/cpu.h-226-void cpu_sh4_invalidate_tlb(CPUSH4State *s);
qemu-5.1+dfsg/target/sh4/cpu.h:227:uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
qemu-5.1+dfsg/target/sh4/cpu.h-228- hwaddr addr);
qemu-5.1+dfsg/target/sh4/cpu.h:229:void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
qemu-5.1+dfsg/target/sh4/cpu.h-230- uint32_t mem_value);
##############################################
qemu-5.1+dfsg/target/sh4/cpu.h-234- uint32_t mem_value);
qemu-5.1+dfsg/target/sh4/cpu.h:235:uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
qemu-5.1+dfsg/target/sh4/cpu.h-236- hwaddr addr);
qemu-5.1+dfsg/target/sh4/cpu.h:237:void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
qemu-5.1+dfsg/target/sh4/cpu.h-238- uint32_t mem_value);
##############################################
qemu-5.1+dfsg/target/sh4/helper.c-509-
qemu-5.1+dfsg/target/sh4/helper.c:510:uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
qemu-5.1+dfsg/target/sh4/helper.c-511- hwaddr addr)
##############################################
qemu-5.1+dfsg/target/sh4/helper.c-520-
qemu-5.1+dfsg/target/sh4/helper.c:521:void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
qemu-5.1+dfsg/target/sh4/helper.c-522- uint32_t mem_value)
##############################################
qemu-5.1+dfsg/target/sh4/helper.c-590-
qemu-5.1+dfsg/target/sh4/helper.c:591:uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
qemu-5.1+dfsg/target/sh4/helper.c-592- hwaddr addr)
##############################################
qemu-5.1+dfsg/target/sh4/helper.c-603-
qemu-5.1+dfsg/target/sh4/helper.c:604:void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
qemu-5.1+dfsg/target/sh4/helper.c-605- uint32_t mem_value)
##############################################
qemu-5.1+dfsg/target/sparc/translate.c-3113-
qemu-5.1+dfsg/target/sparc/translate.c:3114:static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
qemu-5.1+dfsg/target/sparc/translate.c-3115-{
##############################################
qemu-5.1+dfsg/target/sparc/translate.c-4919- cpu_src2 = gen_load_gpr(dc, rs2);
qemu-5.1+dfsg/target/sparc/translate.c:4920: gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
qemu-5.1+dfsg/target/sparc/translate.c-4921- gen_store_gpr(dc, rd, cpu_dst);
##############################################
qemu-5.1+dfsg/target/sparc/translate.c-4926- cpu_src2 = gen_load_gpr(dc, rs2);
qemu-5.1+dfsg/target/sparc/translate.c:4927: gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
qemu-5.1+dfsg/target/sparc/translate.c-4928- gen_store_gpr(dc, rd, cpu_dst);
##############################################
qemu-5.1+dfsg/target/xtensa/cpu.h-673-#ifndef CONFIG_USER_ONLY
qemu-5.1+dfsg/target/xtensa/cpu.h:674:int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
qemu-5.1+dfsg/target/xtensa/cpu.h-675- uint32_t vaddr, int is_write, int mmu_idx,
##############################################
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-35-
qemu-5.1+dfsg/target/xtensa/dbg_helper.c:36:static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-37-{
##############################################
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-40- unsigned access;
qemu-5.1+dfsg/target/xtensa/dbg_helper.c:41: int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-42- &paddr, &page_size, &access);
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-43- if (ret == 0) {
qemu-5.1+dfsg/target/xtensa/dbg_helper.c:44: tb_invalidate_phys_addr(&address_space_memory, paddr,
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-45- MEMTXATTRS_UNSPECIFIED);
##############################################
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-55- if (change & (1 << i)) {
qemu-5.1+dfsg/target/xtensa/dbg_helper.c:56: tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-57- }
##############################################
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-64- if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
qemu-5.1+dfsg/target/xtensa/dbg_helper.c:65: tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
qemu-5.1+dfsg/target/xtensa/dbg_helper.c:66: tb_invalidate_virtual_addr(env, v);
qemu-5.1+dfsg/target/xtensa/dbg_helper.c-67- }
##############################################
qemu-5.1+dfsg/target/xtensa/helper.c-288- unsigned access;
qemu-5.1+dfsg/target/xtensa/helper.c:289: int ret = xtensa_get_physical_addr(env, true, address, access_type,
qemu-5.1+dfsg/target/xtensa/helper.c-290- mmu_idx, &paddr, &page_size, &access);
##############################################
qemu-5.1+dfsg/target/xtensa/mmu_helper.c-309-
qemu-5.1+dfsg/target/xtensa/mmu_helper.c:310: if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
qemu-5.1+dfsg/target/xtensa/mmu_helper.c-311- &paddr, &page_size, &access) == 0) {
##############################################
qemu-5.1+dfsg/target/xtensa/mmu_helper.c-313- }
qemu-5.1+dfsg/target/xtensa/mmu_helper.c:314: if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
qemu-5.1+dfsg/target/xtensa/mmu_helper.c-315- &paddr, &page_size, &access) == 0) {
##############################################
qemu-5.1+dfsg/target/xtensa/mmu_helper.c-1031- */
qemu-5.1+dfsg/target/xtensa/mmu_helper.c:1032:int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
qemu-5.1+dfsg/target/xtensa/mmu_helper.c-1033- uint32_t vaddr, int is_write, int mmu_idx,
##############################################
qemu-5.1+dfsg/target/xtensa/op_helper.c-83- uint32_t atomctl = env->sregs[ATOMCTL];
qemu-5.1+dfsg/target/xtensa/op_helper.c:84: int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
qemu-5.1+dfsg/target/xtensa/op_helper.c-85- xtensa_get_cring(env), &paddr, &page_size, &access);
##############################################
qemu-5.1+dfsg/target/xtensa/op_helper.c-137- uint32_t atomctl = env->sregs[ATOMCTL];
qemu-5.1+dfsg/target/xtensa/op_helper.c:138: int rc = xtensa_get_physical_addr(env, true, vaddr, is_write,
qemu-5.1+dfsg/target/xtensa/op_helper.c-139- xtensa_get_cring(env), &paddr,
##############################################
qemu-5.1+dfsg/target/xtensa/translate.c-312-
qemu-5.1+dfsg/target/xtensa/translate.c:313:static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
qemu-5.1+dfsg/target/xtensa/translate.c-314- TCGv_i32 vaddr)
##############################################
qemu-5.1+dfsg/target/xtensa/translate.c-317- TCGv_i32 tcause = tcg_const_i32(cause);
qemu-5.1+dfsg/target/xtensa/translate.c:318: gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
qemu-5.1+dfsg/target/xtensa/translate.c-319- tcg_temp_free(tpc);
##############################################
qemu-5.1+dfsg/target/xtensa/translate.c-525- tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
qemu-5.1+dfsg/target/xtensa/translate.c:526: gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
qemu-5.1+dfsg/target/xtensa/translate.c-527- gen_set_label(label);
##############################################
qemu-5.1+dfsg/target/xtensa/translate.c-2209-
qemu-5.1+dfsg/target/xtensa/translate.c:2210:static void translate_rsr_ptevaddr(DisasContext *dc, const OpcodeArg arg[],
qemu-5.1+dfsg/target/xtensa/translate.c-2211- const uint32_t par[])
##############################################
qemu-5.1+dfsg/tcg/mips/tcg-target.inc.c-2395- got_sigill = 0;
qemu-5.1+dfsg/tcg/mips/tcg-target.inc.c:2396: asm volatile(".set push\n"
qemu-5.1+dfsg/tcg/mips/tcg-target.inc.c-2397- ".set mips32\n"
##############################################
qemu-5.1+dfsg/tcg/mips/tcg-target.inc.c-2409- got_sigill = 0;
qemu-5.1+dfsg/tcg/mips/tcg-target.inc.c:2410: asm volatile(".set push\n"
qemu-5.1+dfsg/tcg/mips/tcg-target.inc.c-2411- ".set mips32\n"
##############################################
qemu-5.1+dfsg/tcg/mips/tcg-target.inc.c-2423- got_sigill = 0;
qemu-5.1+dfsg/tcg/mips/tcg-target.inc.c:2424: asm volatile(".set push\n"
qemu-5.1+dfsg/tcg/mips/tcg-target.inc.c-2425- ".set mips32r2\n"
##############################################
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c-3872- for (p = start1; p < stop1; p += dsize) {
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c:3873: asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c-3874- }
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c:3875: asm volatile ("sync" : : : "memory");
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c-3876-
##############################################
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c-3879- for (p = start1; p < stop1; p += isize) {
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c:3880: asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c-3881- }
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c:3882: asm volatile ("sync" : : : "memory");
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c:3883: asm volatile ("isync" : : : "memory");
qemu-5.1+dfsg/tcg/ppc/tcg-target.inc.c-3884-}
##############################################
qemu-5.1+dfsg/tcg/s390/tcg-target.inc.c-2496- r1 = &s390_facilities;
qemu-5.1+dfsg/tcg/s390/tcg-target.inc.c:2497: asm volatile(".word 0xb2b0,0x1000"
qemu-5.1+dfsg/tcg/s390/tcg-target.inc.c-2498- : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc");
##############################################
qemu-5.1+dfsg/tests/crypto-tls-x509-helpers.c-161-static void
qemu-5.1+dfsg/tests/crypto-tls-x509-helpers.c:162:test_tls_get_ipaddr(const char *addrstr,
qemu-5.1+dfsg/tests/crypto-tls-x509-helpers.c-163- char **data,
##############################################
qemu-5.1+dfsg/tests/crypto-tls-x509-helpers.c-282-
qemu-5.1+dfsg/tests/crypto-tls-x509-helpers.c:283: test_tls_get_ipaddr(req->ipaddr1, &data, &len);
qemu-5.1+dfsg/tests/crypto-tls-x509-helpers.c-284-
##############################################
qemu-5.1+dfsg/tests/crypto-tls-x509-helpers.c-298-
qemu-5.1+dfsg/tests/crypto-tls-x509-helpers.c:299: test_tls_get_ipaddr(req->ipaddr2, &data, &len);
qemu-5.1+dfsg/tests/crypto-tls-x509-helpers.c-300-
##############################################
qemu-5.1+dfsg/tests/data/acpi/rebuild-expected-aml.sh-33-
qemu-5.1+dfsg/tests/data/acpi/rebuild-expected-aml.sh:34:old_allowed_dif=`grep -v -e 'List of comma-separated changed AML files to ignore' ${SRC_PATH}/tests/qtest/bios-tables-test-allowed-diff.h`
qemu-5.1+dfsg/tests/data/acpi/rebuild-expected-aml.sh-35-
##############################################
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-23- "Step an instruction, check it moved."
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py:24: start_pc = gdb.parse_and_eval('$pc')
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-25- gdb.execute("si")
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py:26: end_pc = gdb.parse_and_eval('$pc')
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-27-
##############################################
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-38- # hopefully we came back
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py:39: end_pc = gdb.parse_and_eval('$pc')
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-40- print ("%s == %s %d" % (end_pc, sym.value(), bp.hit_count))
##############################################
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-54- # hopefully we came back
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py:55: end_pc = gdb.parse_and_eval('$pc')
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-56- print ("%s == %s" % (end_pc, sym.value()))
##############################################
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-80- def stop(self):
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py:81: end_pc = gdb.parse_and_eval('$pc')
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-82- print ("HIT WP @ %s" % (end_pc))
##############################################
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-117- def stop(self):
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py:118: end_pc = gdb.parse_and_eval('$pc')
qemu-5.1+dfsg/tests/guest-debug/test-gdbstub.py-119- print ("CB: %s == %s" % (end_pc, self.sym.value()))
##############################################
qemu-5.1+dfsg/tests/multiboot/libc.h-52-{
qemu-5.1+dfsg/tests/multiboot/libc.h:53: asm volatile ("outb %0, %1" : : "a" (data), "Nd" (port));
qemu-5.1+dfsg/tests/multiboot/libc.h-54-}
##############################################
qemu-5.1+dfsg/tests/multiboot/link.ld-5- . = 0x100000;
qemu-5.1+dfsg/tests/multiboot/link.ld:6: .text : AT(ADDR(.text)) {
qemu-5.1+dfsg/tests/multiboot/link.ld-7- *(multiboot)
##############################################
qemu-5.1+dfsg/tests/multiboot/link.ld-9- }
qemu-5.1+dfsg/tests/multiboot/link.ld:10: .data ALIGN(4096) : AT(ADDR(.data)) {
qemu-5.1+dfsg/tests/multiboot/link.ld-11- *(.data)
qemu-5.1+dfsg/tests/multiboot/link.ld-12- }
qemu-5.1+dfsg/tests/multiboot/link.ld:13: .rodata ALIGN(4096) : AT(ADDR(.rodata)) {
qemu-5.1+dfsg/tests/multiboot/link.ld-14- *(.rodata)
##############################################
qemu-5.1+dfsg/tests/plugin/hotblocks.c-103- ExecCount *cnt;
qemu-5.1+dfsg/tests/plugin/hotblocks.c:104: uint64_t pc = qemu_plugin_tb_vaddr(tb);
qemu-5.1+dfsg/tests/plugin/hotblocks.c-105- unsigned long insns = qemu_plugin_tb_n_insns(tb);
##############################################
qemu-5.1+dfsg/tests/plugin/hotpages.c-108-
qemu-5.1+dfsg/tests/plugin/hotpages.c:109:static void vcpu_haddr(unsigned int cpu_index, qemu_plugin_meminfo_t meminfo,
qemu-5.1+dfsg/tests/plugin/hotpages.c-110- uint64_t vaddr, void *udata)
qemu-5.1+dfsg/tests/plugin/hotpages.c-111-{
qemu-5.1+dfsg/tests/plugin/hotpages.c:112: struct qemu_plugin_hwaddr *hwaddr = qemu_plugin_get_hwaddr(meminfo, vaddr);
qemu-5.1+dfsg/tests/plugin/hotpages.c-113- uint64_t page;
##############################################
qemu-5.1+dfsg/tests/plugin/lockstep.c-223- BlockInfo *bi = g_new0(BlockInfo, 1);
qemu-5.1+dfsg/tests/plugin/lockstep.c:224: bi->pc = qemu_plugin_tb_vaddr(tb);
qemu-5.1+dfsg/tests/plugin/lockstep.c-225- bi->insns = qemu_plugin_tb_n_insns(tb);
##############################################
qemu-5.1+dfsg/tests/plugin/mem.c-40- struct qemu_plugin_hwaddr *hwaddr;
qemu-5.1+dfsg/tests/plugin/mem.c:41: hwaddr = qemu_plugin_get_hwaddr(meminfo, vaddr);
qemu-5.1+dfsg/tests/plugin/mem.c-42- if (qemu_plugin_hwaddr_is_io(hwaddr)) {
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/001-23-
qemu-5.1+dfsg/tests/qemu-iotests/001:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/001-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/002-23-
qemu-5.1+dfsg/tests/qemu-iotests/002:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/002-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/003-23-
qemu-5.1+dfsg/tests/qemu-iotests/003:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/003-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/004-23-
qemu-5.1+dfsg/tests/qemu-iotests/004:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/004-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/005-26-
qemu-5.1+dfsg/tests/qemu-iotests/005:27:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/005-28-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/007-23-
qemu-5.1+dfsg/tests/qemu-iotests/007:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/007-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/008-23-
qemu-5.1+dfsg/tests/qemu-iotests/008:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/008-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/009-23-
qemu-5.1+dfsg/tests/qemu-iotests/009:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/009-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/010-23-
qemu-5.1+dfsg/tests/qemu-iotests/010:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/010-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/011-23-
qemu-5.1+dfsg/tests/qemu-iotests/011:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/011-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/012-25-
qemu-5.1+dfsg/tests/qemu-iotests/012:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/012-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/013-23-
qemu-5.1+dfsg/tests/qemu-iotests/013:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/013-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/014-25-
qemu-5.1+dfsg/tests/qemu-iotests/014:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/014-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/015-23-
qemu-5.1+dfsg/tests/qemu-iotests/015:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/015-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/017-23-
qemu-5.1+dfsg/tests/qemu-iotests/017:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/017-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/018-23-
qemu-5.1+dfsg/tests/qemu-iotests/018:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/018-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/019-25-
qemu-5.1+dfsg/tests/qemu-iotests/019:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/019-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/020-23-
qemu-5.1+dfsg/tests/qemu-iotests/020:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/020-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/021-23-
qemu-5.1+dfsg/tests/qemu-iotests/021:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/021-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/022-25-
qemu-5.1+dfsg/tests/qemu-iotests/022:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/022-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/023-23-
qemu-5.1+dfsg/tests/qemu-iotests/023:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/023-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/024-23-
qemu-5.1+dfsg/tests/qemu-iotests/024:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/024-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/025-23-
qemu-5.1+dfsg/tests/qemu-iotests/025:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/025-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/026-23-
qemu-5.1+dfsg/tests/qemu-iotests/026:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/026-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/027-23-
qemu-5.1+dfsg/tests/qemu-iotests/027:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/027-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/028-26-
qemu-5.1+dfsg/tests/qemu-iotests/028:27:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/028-28-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/029-23-
qemu-5.1+dfsg/tests/qemu-iotests/029:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/029-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/031-23-
qemu-5.1+dfsg/tests/qemu-iotests/031:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/031-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/032-25-
qemu-5.1+dfsg/tests/qemu-iotests/032:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/032-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/033-23-
qemu-5.1+dfsg/tests/qemu-iotests/033:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/033-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/034-23-
qemu-5.1+dfsg/tests/qemu-iotests/034:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/034-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/035-24-
qemu-5.1+dfsg/tests/qemu-iotests/035:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/035-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/036-26-
qemu-5.1+dfsg/tests/qemu-iotests/036:27:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/036-28-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/037-23-
qemu-5.1+dfsg/tests/qemu-iotests/037:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/037-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/038-23-
qemu-5.1+dfsg/tests/qemu-iotests/038:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/038-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/039-26-
qemu-5.1+dfsg/tests/qemu-iotests/039:27:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/039-28-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/042-23-
qemu-5.1+dfsg/tests/qemu-iotests/042:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/042-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/043-23-
qemu-5.1+dfsg/tests/qemu-iotests/043:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/043-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/046-23-
qemu-5.1+dfsg/tests/qemu-iotests/046:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/046-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/047-24-
qemu-5.1+dfsg/tests/qemu-iotests/047:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/047-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/048-24-
qemu-5.1+dfsg/tests/qemu-iotests/048:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/048-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/049-23-
qemu-5.1+dfsg/tests/qemu-iotests/049:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/049-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/050-23-
qemu-5.1+dfsg/tests/qemu-iotests/050:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/050-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/051-23-
qemu-5.1+dfsg/tests/qemu-iotests/051:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/051-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/052-23-
qemu-5.1+dfsg/tests/qemu-iotests/052:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/052-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/053-23-
qemu-5.1+dfsg/tests/qemu-iotests/053:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/053-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/054-23-
qemu-5.1+dfsg/tests/qemu-iotests/054:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/054-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/058-25-
qemu-5.1+dfsg/tests/qemu-iotests/058:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/058-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/059-23-
qemu-5.1+dfsg/tests/qemu-iotests/059:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/059-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/061-23-
qemu-5.1+dfsg/tests/qemu-iotests/061:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/061-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/062-24-
qemu-5.1+dfsg/tests/qemu-iotests/062:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/062-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/063-24-
qemu-5.1+dfsg/tests/qemu-iotests/063:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/063-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/064-23-
qemu-5.1+dfsg/tests/qemu-iotests/064:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/064-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/067-23-
qemu-5.1+dfsg/tests/qemu-iotests/067:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/067-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/070-24-
qemu-5.1+dfsg/tests/qemu-iotests/070:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/070-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/073-23-
qemu-5.1+dfsg/tests/qemu-iotests/073:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/073-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/074-24-
qemu-5.1+dfsg/tests/qemu-iotests/074:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/074-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/075-23-
qemu-5.1+dfsg/tests/qemu-iotests/075:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/075-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/076-23-
qemu-5.1+dfsg/tests/qemu-iotests/076:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/076-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/077-23-
qemu-5.1+dfsg/tests/qemu-iotests/077:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/077-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/078-23-
qemu-5.1+dfsg/tests/qemu-iotests/078:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/078-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/079-23-
qemu-5.1+dfsg/tests/qemu-iotests/079:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/079-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/080-23-
qemu-5.1+dfsg/tests/qemu-iotests/080:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/080-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/081-23-
qemu-5.1+dfsg/tests/qemu-iotests/081:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/081-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/082-23-
qemu-5.1+dfsg/tests/qemu-iotests/082:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/082-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/083-23-
qemu-5.1+dfsg/tests/qemu-iotests/083:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/083-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/084-24-
qemu-5.1+dfsg/tests/qemu-iotests/084:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/084-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/085-28-
qemu-5.1+dfsg/tests/qemu-iotests/085:29:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/085-30-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/086-23-
qemu-5.1+dfsg/tests/qemu-iotests/086:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/086-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/087-23-
qemu-5.1+dfsg/tests/qemu-iotests/087:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/087-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/088-23-
qemu-5.1+dfsg/tests/qemu-iotests/088:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/088-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/091-25-
qemu-5.1+dfsg/tests/qemu-iotests/091:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/091-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/092-23-
qemu-5.1+dfsg/tests/qemu-iotests/092:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/092-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/095-26-
qemu-5.1+dfsg/tests/qemu-iotests/095:27:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/095-28-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/101-23-
qemu-5.1+dfsg/tests/qemu-iotests/101:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/101-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/104-23-
qemu-5.1+dfsg/tests/qemu-iotests/104:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/104-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/105-23-
qemu-5.1+dfsg/tests/qemu-iotests/105:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/105-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/116-26-
qemu-5.1+dfsg/tests/qemu-iotests/116:27:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/116-28-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/128-23-
qemu-5.1+dfsg/tests/qemu-iotests/128:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/128-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/131-23-
qemu-5.1+dfsg/tests/qemu-iotests/131:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/131-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/133-23-
qemu-5.1+dfsg/tests/qemu-iotests/133:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/133-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/134-23-
qemu-5.1+dfsg/tests/qemu-iotests/134:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/134-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/135-23-
qemu-5.1+dfsg/tests/qemu-iotests/135:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/135-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/142-23-
qemu-5.1+dfsg/tests/qemu-iotests/142:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/142-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/144-25-
qemu-5.1+dfsg/tests/qemu-iotests/144:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/144-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/145-23-
qemu-5.1+dfsg/tests/qemu-iotests/145:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/145-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/146-23-
qemu-5.1+dfsg/tests/qemu-iotests/146:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/146-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/147-37-
qemu-5.1+dfsg/tests/qemu-iotests/147:38:def flatten_sock_addr(crumpled_address):
qemu-5.1+dfsg/tests/qemu-iotests/147-39- result = { 'type': crumpled_address['type'] }
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/147-117- self.client_test('nbd://localhost:%i' % nbd_port,
qemu-5.1+dfsg/tests/qemu-iotests/147:118: flatten_sock_addr(address))
qemu-5.1+dfsg/tests/qemu-iotests/147-119-
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/147-124- self.client_test('nbd+unix://?socket=' + unix_socket,
qemu-5.1+dfsg/tests/qemu-iotests/147:125: flatten_sock_addr(address))
qemu-5.1+dfsg/tests/qemu-iotests/147-126-
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/147-192- self.client_test('nbd://localhost:%i/%s' % (nbd_port, export_name),
qemu-5.1+dfsg/tests/qemu-iotests/147:193: flatten_sock_addr(address), export_name)
qemu-5.1+dfsg/tests/qemu-iotests/147-194- self._server_down()
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/147-216- self.client_test('nbd://localhost:%i/%s' % (nbd_port, 'exp1'),
qemu-5.1+dfsg/tests/qemu-iotests/147:217: flatten_sock_addr(address), 'exp1', 'node1', False)
qemu-5.1+dfsg/tests/qemu-iotests/147-218- self.client_test('nbd://localhost:%i/%s' % (nbd_port, 'exp2'),
qemu-5.1+dfsg/tests/qemu-iotests/147:219: flatten_sock_addr(address), 'exp2', 'node2', False)
qemu-5.1+dfsg/tests/qemu-iotests/147-220- result = self.vm.qmp('blockdev-del', node_name='node1')
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/147-250- 'export': 'nbd-export',
qemu-5.1+dfsg/tests/qemu-iotests/147:251: 'server': flatten_sock_addr(address)
qemu-5.1+dfsg/tests/qemu-iotests/147-252- } }
qemu-5.1+dfsg/tests/qemu-iotests/147:253: self.client_test(filename, flatten_sock_addr(address), 'nbd-export')
qemu-5.1+dfsg/tests/qemu-iotests/147-254- self._server_down()
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/147-260- self.client_test('nbd+unix:///nbd-export?socket=' + unix_socket,
qemu-5.1+dfsg/tests/qemu-iotests/147:261: flatten_sock_addr(address), 'nbd-export')
qemu-5.1+dfsg/tests/qemu-iotests/147-262- self._server_down()
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/147-282- 'export': 'nbd-export',
qemu-5.1+dfsg/tests/qemu-iotests/147:283: 'server': flatten_sock_addr(address)
qemu-5.1+dfsg/tests/qemu-iotests/147-284- } }
qemu-5.1+dfsg/tests/qemu-iotests/147:285: self.client_test(filename, flatten_sock_addr(address), 'nbd-export')
qemu-5.1+dfsg/tests/qemu-iotests/147-286-
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/154-23-
qemu-5.1+dfsg/tests/qemu-iotests/154:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/154-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/158-23-
qemu-5.1+dfsg/tests/qemu-iotests/158:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/158-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/161-23-
qemu-5.1+dfsg/tests/qemu-iotests/161:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/161-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/171-24-
qemu-5.1+dfsg/tests/qemu-iotests/171:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/171-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/172-23-
qemu-5.1+dfsg/tests/qemu-iotests/172:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/172-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/173-23-
qemu-5.1+dfsg/tests/qemu-iotests/173:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/173-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/174-23-
qemu-5.1+dfsg/tests/qemu-iotests/174:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/174-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/175-23-
qemu-5.1+dfsg/tests/qemu-iotests/175:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/175-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/177-23-
qemu-5.1+dfsg/tests/qemu-iotests/177:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/177-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/178-23-
qemu-5.1+dfsg/tests/qemu-iotests/178:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/178-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/181-23-
qemu-5.1+dfsg/tests/qemu-iotests/181:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/181-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/183-23-
qemu-5.1+dfsg/tests/qemu-iotests/183:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/183-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/184-23-
qemu-5.1+dfsg/tests/qemu-iotests/184:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/184-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/185-23-
qemu-5.1+dfsg/tests/qemu-iotests/185:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/185-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/186-23-
qemu-5.1+dfsg/tests/qemu-iotests/186:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/186-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/187-23-
qemu-5.1+dfsg/tests/qemu-iotests/187:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/187-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/188-23-
qemu-5.1+dfsg/tests/qemu-iotests/188:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/188-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/189-23-
qemu-5.1+dfsg/tests/qemu-iotests/189:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/189-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/190-23-
qemu-5.1+dfsg/tests/qemu-iotests/190:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/190-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/191-23-
qemu-5.1+dfsg/tests/qemu-iotests/191:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/191-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/192-24-
qemu-5.1+dfsg/tests/qemu-iotests/192:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/192-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/195-23-
qemu-5.1+dfsg/tests/qemu-iotests/195:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/195-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/198-23-
qemu-5.1+dfsg/tests/qemu-iotests/198:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/198-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/200-25-
qemu-5.1+dfsg/tests/qemu-iotests/200:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/200-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/201-21-
qemu-5.1+dfsg/tests/qemu-iotests/201:22:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/201-23-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/204-23-
qemu-5.1+dfsg/tests/qemu-iotests/204:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/204-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/226-24-
qemu-5.1+dfsg/tests/qemu-iotests/226:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/226-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/231-25-
qemu-5.1+dfsg/tests/qemu-iotests/231:26:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/231-27-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/232-23-
qemu-5.1+dfsg/tests/qemu-iotests/232:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/232-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/239-23-
qemu-5.1+dfsg/tests/qemu-iotests/239:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/239-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/240-24-
qemu-5.1+dfsg/tests/qemu-iotests/240:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/240-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/247-23-
qemu-5.1+dfsg/tests/qemu-iotests/247:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/247-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/250-23-
qemu-5.1+dfsg/tests/qemu-iotests/250:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/250-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/263-24-
qemu-5.1+dfsg/tests/qemu-iotests/263:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/263-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/267-23-
qemu-5.1+dfsg/tests/qemu-iotests/267:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/267-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/268-24-
qemu-5.1+dfsg/tests/qemu-iotests/268:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/268-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/282-20-
qemu-5.1+dfsg/tests/qemu-iotests/282:21:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/282-22-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/284-23-
qemu-5.1+dfsg/tests/qemu-iotests/284:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/284-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/288-23-
qemu-5.1+dfsg/tests/qemu-iotests/288:24:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/288-25-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/290-24-
qemu-5.1+dfsg/tests/qemu-iotests/290:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/290-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/292-24-
qemu-5.1+dfsg/tests/qemu-iotests/292:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/292-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/293-24-
qemu-5.1+dfsg/tests/qemu-iotests/293:25:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/293-26-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/294-20-
qemu-5.1+dfsg/tests/qemu-iotests/294:21:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/294-22-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qemu-iotests/301-20-
qemu-5.1+dfsg/tests/qemu-iotests/301:21:seq=`basename $0`
qemu-5.1+dfsg/tests/qemu-iotests/301-22-echo "QA output created by $seq"
##############################################
qemu-5.1+dfsg/tests/qtest/boot-sector.c-23-#define BOOT_SECTOR_ADDRESS 0x7c00
qemu-5.1+dfsg/tests/qtest/boot-sector.c:24:#define SIGNATURE_ADDR (BOOT_SECTOR_ADDRESS + SIGNATURE_OFFSET)
qemu-5.1+dfsg/tests/qtest/boot-sector.c-25-
##############################################
qemu-5.1+dfsg/tests/qtest/libqos/i2c-imx.c-32-
qemu-5.1+dfsg/tests/qtest/libqos/i2c-imx.c:33:static void imx_i2c_set_slave_addr(IMXI2C *s, uint8_t addr,
qemu-5.1+dfsg/tests/qtest/libqos/i2c-imx.c-34- enum IMXI2CDirection direction)
##############################################
qemu-5.1+dfsg/tests/qtest/libqos/i2c-imx.c-63- /* set the slave address */
qemu-5.1+dfsg/tests/qtest/libqos/i2c-imx.c:64: imx_i2c_set_slave_addr(s, addr, IMX_I2C_WRITE);
qemu-5.1+dfsg/tests/qtest/libqos/i2c-imx.c-65- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
##############################################
qemu-5.1+dfsg/tests/qtest/libqos/i2c-imx.c-123- /* set the slave address */
qemu-5.1+dfsg/tests/qtest/libqos/i2c-imx.c:124: imx_i2c_set_slave_addr(s, addr, IMX_I2C_READ);
qemu-5.1+dfsg/tests/qtest/libqos/i2c-imx.c-125- status = qtest_readb(i2c->qts, s->addr + I2SR_ADDR);
##############################################
qemu-5.1+dfsg/tests/qtest/libqos/i2c-omap.c-43-
qemu-5.1+dfsg/tests/qtest/libqos/i2c-omap.c:44:static void omap_i2c_set_slave_addr(OMAPI2C *s, uint8_t addr)
qemu-5.1+dfsg/tests/qtest/libqos/i2c-omap.c-45-{
##############################################
qemu-5.1+dfsg/tests/qtest/libqos/i2c-omap.c-58-
qemu-5.1+dfsg/tests/qtest/libqos/i2c-omap.c:59: omap_i2c_set_slave_addr(s, addr);
qemu-5.1+dfsg/tests/qtest/libqos/i2c-omap.c-60-
##############################################
qemu-5.1+dfsg/tests/qtest/libqos/i2c-omap.c-103-
qemu-5.1+dfsg/tests/qtest/libqos/i2c-omap.c:104: omap_i2c_set_slave_addr(s, addr);
qemu-5.1+dfsg/tests/qtest/libqos/i2c-omap.c-105-
##############################################
qemu-5.1+dfsg/tests/qtest/migration-test.c-225-{
qemu-5.1+dfsg/tests/qtest/migration-test.c:226: /* Our ASM test will have been incrementing one byte from each page from
qemu-5.1+dfsg/tests/qtest/migration-test.c-227- * start_address to < end_address in order. This gives us a constraint
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-19-#define MP_FLASH_SIZE_MAX (32 * 1024 * 1024)
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:20:#define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX)
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-21-
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-28-} faddr;
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:29:#define FLASH_ADDR(x) ((faddr) { .addr = (x) })
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-30-
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:31:#define CFI_ADDR FLASH_ADDR(0x55)
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:32:#define UNLOCK0_ADDR FLASH_ADDR(0x555)
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:33:#define UNLOCK1_ADDR FLASH_ADDR(0x2AA)
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-34-
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-148- */
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:149:static inline uint64_t as_byte_addr(const FlashConfig *c, faddr flash_addr)
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-150-{
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-174-{
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:175: flash_write(c, as_byte_addr(c, cmd_addr), replicate(c, cmd));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-176-}
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-179-{
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:180: return flash_read(c, as_byte_addr(c, query_addr));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-181-}
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-195-{
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:196: flash_cmd(c, FLASH_ADDR(0), RESET_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-197-}
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-247-{
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:248: flash_cmd(c, FLASH_ADDR(0), ERASE_SUSPEND_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-249-}
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-252-{
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:253: flash_cmd(c, FLASH_ADDR(0), ERASE_RESUME_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-254-}
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-297- flash_cmd(c, UNLOCK0_ADDR, AUTOSELECT_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:298: g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-299- if (c->bank_width >= 2) {
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-305- */
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:306: g_assert_cmphex(flash_query(c, FLASH_ADDR(1)), ==,
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-307- replicate(c, 0x236D));
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-312- flash_cmd(c, CFI_ADDR, CFI_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:313: g_assert_cmphex(flash_query(c, FLASH_ADDR(0x10)), ==, replicate(c, 'Q'));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:314: g_assert_cmphex(flash_query(c, FLASH_ADDR(0x11)), ==, replicate(c, 'R'));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:315: g_assert_cmphex(flash_query(c, FLASH_ADDR(0x12)), ==, replicate(c, 'Y'));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-316-
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-317- /* Num erase regions. */
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:318: int nb_erase_regions = flash_query_1(c, FLASH_ADDR(0x2C));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-319- g_assert_cmphex(nb_erase_regions, ==,
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-323- /* Check device length. */
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:324: uint32_t device_len = 1 << flash_query_1(c, FLASH_ADDR(0x27));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-325- g_assert_cmphex(device_len, ==, UNIFORM_FLASH_SIZE);
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-327- /* Check that erase suspend to read/write is supported. */
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:328: uint16_t pri = flash_query_1(c, FLASH_ADDR(0x15)) +
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:329: (flash_query_1(c, FLASH_ADDR(0x16)) << 8);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-330- g_assert_cmpint(pri, >=, 0x2D + 4 * nb_erase_regions);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:331: g_assert_cmpint(flash_query(c, FLASH_ADDR(pri + 0)), ==, replicate(c, 'P'));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:332: g_assert_cmpint(flash_query(c, FLASH_ADDR(pri + 1)), ==, replicate(c, 'R'));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:333: g_assert_cmpint(flash_query(c, FLASH_ADDR(pri + 2)), ==, replicate(c, 'I'));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:334: g_assert_cmpint(flash_query_1(c, FLASH_ADDR(pri + 6)), ==, 2); /* R/W */
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-335- reset(c);
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-345- flash_cmd(c, CFI_ADDR, CFI_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:346: uint32_t nb_sectors = flash_query_1(c, FLASH_ADDR(base + 0)) +
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:347: (flash_query_1(c, FLASH_ADDR(base + 1)) << 8) + 1;
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:348: uint32_t sector_len = (flash_query_1(c, FLASH_ADDR(base + 2)) << 8) +
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:349: (flash_query_1(c, FLASH_ADDR(base + 3)) << 16);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-350- g_assert_cmphex(nb_sectors, ==, c->nb_blocs[region]);
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-423- */
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:424: flash_cmd(c, FLASH_ADDR(3 * c->bank_width), PROGRAM_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-425- flash_write(c, 3 * c->bank_width, 0x67);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-426- wait_for_completion(c, 3 * c->bank_width);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:427: flash_cmd(c, FLASH_ADDR(0), UNLOCK_BYPASS_RESET_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-428- bypass_program(c, 4 * c->bank_width, 0x89); /* Should fail. */
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-435- /* Test ignored high order bits of address. */
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:436: flash_cmd(c, FLASH_ADDR(0x5555), UNLOCK0_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:437: flash_cmd(c, FLASH_ADDR(0x2AAA), UNLOCK1_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:438: flash_cmd(c, FLASH_ADDR(0x5555), AUTOSELECT_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:439: g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-440- reset(c);
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-592- flash_cmd(c, UNLOCK0_ADDR, AUTOSELECT_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:593: g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-594-
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-596- flash_cmd(c, CFI_ADDR, CFI_CMD);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:597: g_assert_cmphex(flash_query(c, FLASH_ADDR(0x10)), ==, replicate(c, 'Q'));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:598: g_assert_cmphex(flash_query(c, FLASH_ADDR(0x11)), ==, replicate(c, 'R'));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:599: g_assert_cmphex(flash_query(c, FLASH_ADDR(0x12)), ==, replicate(c, 'Y'));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-600-
##############################################
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-602- reset(c);
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c:603: g_assert_cmphex(flash_query(c, FLASH_ADDR(0)), ==, replicate(c, 0xBF));
qemu-5.1+dfsg/tests/qtest/pflash-cfi02-test.c-604-
##############################################
qemu-5.1+dfsg/tests/qtest/pnv-xscom-test.c-50-
qemu-5.1+dfsg/tests/qtest/pnv-xscom-test.c:51:static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
qemu-5.1+dfsg/tests/qtest/pnv-xscom-test.c-52-{
##############################################
qemu-5.1+dfsg/tests/qtest/pnv-xscom-test.c-66-{
qemu-5.1+dfsg/tests/qtest/pnv-xscom-test.c:67: return qtest_readq(qts, pnv_xscom_addr(chip, pcba));
qemu-5.1+dfsg/tests/qtest/pnv-xscom-test.c-68-}
##############################################
qemu-5.1+dfsg/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py-34- for i in range(0, int(val_i)):
qemu-5.1+dfsg/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py:35: val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i)
qemu-5.1+dfsg/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py-36- report(int(val_z) == i, "z0.b.u[%d] == %d" % (i, i))
qemu-5.1+dfsg/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py-37- for i in range(i + 1, initial_vlen):
qemu-5.1+dfsg/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py:38: val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i)
qemu-5.1+dfsg/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py-39- report(int(val_z) == 0, "z0.b.u[%d] == 0" % (i))
##############################################
qemu-5.1+dfsg/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py-50- global initial_vlen
qemu-5.1+dfsg/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py:51: vg = gdb.parse_and_eval("$vg")
qemu-5.1+dfsg/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py-52- initial_vlen = int(vg) * 8
##############################################
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-1.c-18- for (i = 0; i < TESTS; i++) {
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-1.c:19: asm volatile("pacdza %0" : "=r"(p1) : "0"(p0));
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-1.c-20- prctl(PR_PAC_RESET_KEYS, PR_PAC_APDAKEY, 0, 0, 0);
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-1.c:21: asm volatile("pacdza %0" : "=r"(p2) : "0"(p0));
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-1.c-22-
##############################################
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-2.c-15- for (salt1 = 1; ; salt1++) {
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-2.c:16: asm volatile("pacda %0, %2" : "=r"(encode) : "0"(value), "r"(salt1));
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-2.c-17- if (encode != value) {
##############################################
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-2.c-22- /* A valid salt must produce a valid authorization. */
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-2.c:23: asm volatile("autda %0, %2" : "=r"(decode) : "0"(encode), "r"(salt1));
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-2.c-24- assert(decode == value);
##############################################
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-2.c-31- for (salt2 = salt1 + 1; ; salt2++) {
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-2.c:32: asm volatile("autda %0, %2" : "=r"(decode) : "0"(encode), "r"(salt2));
qemu-5.1+dfsg/tests/tcg/aarch64/pauth-2.c-33- if (decode != value) {
##############################################
qemu-5.1+dfsg/tests/tcg/alpha/test-cond.c-9- \
qemu-5.1+dfsg/tests/tcg/alpha/test-cond.c:10: asm ("cmov"#N" %1,$31,%0" \
qemu-5.1+dfsg/tests/tcg/alpha/test-cond.c-11- : "+r" (res) : "r" (a)); \
##############################################
qemu-5.1+dfsg/tests/tcg/alpha/test-cond.c-21- \
qemu-5.1+dfsg/tests/tcg/alpha/test-cond.c:22: asm ("b"#N" %1,1f\n\t" \
qemu-5.1+dfsg/tests/tcg/alpha/test-cond.c-23- "addq $31,$31,%0\n\t" \
##############################################
qemu-5.1+dfsg/tests/tcg/alpha/test-ovf.c-6-
qemu-5.1+dfsg/tests/tcg/alpha/test-ovf.c:7: asm ("subq/v %1,%2,%0"
qemu-5.1+dfsg/tests/tcg/alpha/test-ovf.c-8- : "=r" (res) : "r" (a), "r" (b));
##############################################
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c-10-{
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c:11: register unsigned int callno asm ("r9") = 1; /* NR_exit */
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c-12-
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c:13: asm volatile ("break 13\n"
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c-14- : /* no outputs */
##############################################
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c-23-{
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c:24: register unsigned int callno asm ("r9") = 4; /* NR_write */
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c:25: register unsigned int r10 asm ("r10") = fd;
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c:26: register const void *r11 asm ("r11") = buf;
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c:27: register size_t r12 asm ("r12") = count;
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c:28: register unsigned int r asm ("r10");
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c-29-
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c:30: asm volatile ("break 13\n"
qemu-5.1+dfsg/tests/tcg/cris/bare/sys.c-31- : "=r" (r)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_abs.c-9- int r;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_abs.c:10: asm ("abs\t%1, %0\n" : "=r" (r) : "r" (n));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_abs.c-11- return r;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-8-{
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:9: asm ("addc\t%1, %0\n" : "+r" (a) : "r" (b));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-10- return a;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-24- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:25: asm volatile ("clearf cz");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-26- verify_addc(0, 0, 0, 0, 0, 0, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-28- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:29: asm volatile ("setf z");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-30- verify_addc(0, 0, 0, 0, 1, 0, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-32- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:33: asm volatile ("setf cz");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-34- verify_addc(0, 0, 1, 0, 0, 0, 0);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-35- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:36: asm volatile ("clearf c");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-37- verify_addc(-1, 2, 1, 0, 0, 0, 1);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-39- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:40: asm volatile ("clearf nzv");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:41: asm volatile ("setf c");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-42- verify_addc(-1, 2, 2, 0, 0, 0, 1);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-44- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:45: asm volatile ("setf c");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-46- verify_addc(0xffff, 0xffff, 0x1ffff, 0, 0, 0, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-48- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:49: asm volatile ("clearf nzvc");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-50- verify_addc(-1, -1, 0xfffffffe, 1, 0, 0, 1);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-52- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c:53: asm volatile ("setf c");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addc.c-54- verify_addc(0x78134452, 0x5432f789, 0xcc463bdc, 1, 0, 1, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-9-{
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c:10: asm volatile ("addc [%1], %0\n" : "+r" (a) : "r" (b));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-11- return a;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-16-{
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c:17: asm volatile ("addc [%1+], %0\n" : "+r" (a), "+b" (*b));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-18- return a;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-45- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c:46: asm volatile ("clearf cz");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-47- verify_addc_m(0, p, 0, 0, 0, 0, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-49- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c:50: asm volatile ("setf z");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-51- verify_addc_m(0, p, 0, 0, 1, 0, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-53- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c:54: asm volatile ("setf c");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-55- verify_addc_m(0, p, 1, 0, 0, 0, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-57- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c:58: asm volatile ("clearf c");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-59- verify_addc_pi_m(0, &p, 0, 0, 1, 0, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-62- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c:63: asm volatile ("setf c");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-64- verify_addc_pi_m(0, &p, 1, 0, 0, 0, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-69- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c:70: asm volatile ("clearf c");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-71- verify_addc_pi_m(-1, &p, 1, 0, 0, 0, 1);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-78- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c:79: asm volatile ("setf c");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addcm.c-80- verify_addc_m(2, p, 2, 0, 0, 0, 1);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-6-
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:7:/* this would be better to do in asm, it's an orgy in GCC inline asm now. */
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-8-
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-9-#define cris_addo_b(o, v) \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:10: asm volatile ("addo.b\t[%0], %1, $acr\n" : : "r" (o), "r" (v) : "acr");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-11-#define cris_addo_w(o, v) \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:12: asm volatile ("addo.w\t[%0], %1, $acr\n" : : "r" (o), "r" (v) : "acr");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-13-#define cris_addo_d(o, v) \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:14: asm volatile ("addo.d\t[%0], %1, $acr\n" : : "r" (o), "r" (v) : "acr");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-15-#define cris_addo_pi_b(o, v) \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:16: asm volatile ("addo.b\t[%0+], %1, $acr\n" \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-17- : "+b" (o): "r" (v) : "acr");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-18-#define cris_addo_pi_w(o, v) \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:19: asm volatile ("addo.w\t[%0+], %1, $acr\n" \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-20- : "+b" (o): "r" (v) : "acr");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-21-#define cris_addo_pi_d(o, v) \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:22: asm volatile ("addo.d\t[%0+], %1, $acr\n" \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-23- : "+b" (o): "r" (v) : "acr");
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-55- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:56: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-57- cris_addo_pi_d(p, t);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-58- cris_tst_cc(1, 1, 1, 1);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:59: asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-60- if (*r != 0x4455aa77)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-66- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:67: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-68- cris_addo_pi_w(p, t);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-69- cris_tst_cc(1, 1, 1, 1);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:70: asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-71- if (*r != 0x4455aa77)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-75- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:76: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-77- cris_addo_d(p, r);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-79- p += 4;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:80: asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-81- if (*r != 0xee19ccff)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-85- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:86: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-87- cris_addo_pi_b(p, t);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-88- cris_tst_cc(0, 0, 0, 0);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:89: asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-90- if (*(uint16_t*)r != 0xff22)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-94- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:95: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-96- cris_addo_b(p, r);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-98- p += 1;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:99: asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-100- if (*r != 0x4455aa77)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-104- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:105: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-106- cris_addo_w(p, r);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-108- p += 2;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:109: asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-110- if (*r != 0xff224455)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-114- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:115: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-116- cris_addo_pi_d(p, t);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-117- cris_tst_cc(0, 0, 0, 0);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c:118: asm volatile ("move.d\t$acr, %0\n" : "=r" (r));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addo.c-119- r = (void*)(((char *)r) + 76789885);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-6-
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c:7:/* this would be better to do in asm, it's an orgy in GCC inline asm now. */
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-8-
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-10-#define cris_addoq(o, v) \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c:11: asm volatile ("addoq\t%1, %0, $acr\n" : : "r" (v), "i" (o) : "acr");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-12-
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-19- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c:20: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-21- cris_addoq(0, t);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-22- cris_tst_cc(1, 1, 1, 1);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c:23: asm volatile ("move.d\t$acr, %0\n" : "=r" (p));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-24- if (*p != 0xccff2244)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-27- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c:28: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-29- cris_addoq(4, t);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-30- cris_tst_cc(0, 0, 0, 0);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c:31: asm volatile ("move.d\t$acr, %0\n" : "=r" (p));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-32- if (*p != 0x88ccee19)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-35- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c:36: asm volatile ("clearf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-37- cris_addoq(-8, t + 1);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-38- cris_tst_cc(0, 0, 0, 0);
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c:39: asm volatile ("move.d\t$acr, %0\n" : "=r" (p));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_addoq.c-40- if (*p != 0x55aa77ff)
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_bound.c-9- int r = v;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_bound.c:10: asm ("bound.b\t%1, %0\n" : "+r" (r) : "ri" (b));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_bound.c-11- return r;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_bound.c-16- int r = v;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_bound.c:17: asm ("bound.w\t%1, %0\n" : "+r" (r) : "ri" (b));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_bound.c-18- return r;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_bound.c-23- int r = v;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_bound.c:24: asm ("bound.d\t%1, %0\n" : "+r" (r) : "ri" (b));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_bound.c-25- return r;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c-9- register unsigned int v asm("$r10") = x;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c:10: asm ("ftagi\t[%0]\n" : : "r" (v) );
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c-11-}
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c-14- register unsigned int v asm("$r10") = x;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c:15: asm ("ftagd\t[%0]\n" : : "r" (v) );
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c-16-}
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c-19- register unsigned int v asm("$r10") = x;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c:20: asm ("fidxi\t[%0]\n" : : "r" (v) );
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c-21-}
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c-24- register unsigned int v asm("$r10") = x;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c:25: asm ("fidxd\t[%0]\n" : : "r" (v) );
qemu-5.1+dfsg/tests/tcg/cris/libc/check_ftag.c-26-}
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_lz.c-8- int r;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_lz.c:9: asm ("lz\t%1, %0\n" : "=r" (r) : "r" (x));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_lz.c-10- return r;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-7-#define cris_moveq(dst, src) \
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c:8: asm volatile ("moveq %1, %0\n" : "=r" (dst) : "i" (src));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-9-
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-16- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c:17: asm volatile ("setf\tzvnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-18- cris_moveq(t, 10);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-24- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c:25: asm volatile ("setf vnc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c:26: asm volatile ("clearf z\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-27- cris_moveq(t, 0);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-34- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c:35: asm volatile ("setf zvc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c:36: asm volatile ("clearf n\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-37- cris_moveq(t, -31);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-42- cris_tst_cc_init();
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c:43: asm volatile ("setf nzvc\n");
qemu-5.1+dfsg/tests/tcg/cris/libc/check_moveq.c-44- cris_moveq(t, 31);
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_settls1.c-16-
qemu-5.1+dfsg/tests/tcg/cris/libc/check_settls1.c:17: asm volatile ("move $pid,%0" : "=r" (old_tp));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_settls1.c-18- old_tp &= ~0xff;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_settls1.c-32-
qemu-5.1+dfsg/tests/tcg/cris/libc/check_settls1.c:33: asm volatile ("move $pid,%0" : "=r" (tp));
qemu-5.1+dfsg/tests/tcg/cris/libc/check_settls1.c-34- tp &= ~0xff;
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c-15- {
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:16: case N: asm ("swapn\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:17: case W: asm ("swapw\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:18: case B: asm ("swapb\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:19: case R: asm ("swapr\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:20: case B|R: asm ("swapbr\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:21: case W|R: asm ("swapwr\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:22: case W|B: asm ("swapwb\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:23: case W|B|R: asm ("swapwbr\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:24: case N|R: asm ("swapnr\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:25: case N|B: asm ("swapnb\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:26: case N|B|R: asm ("swapnbr\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c:27: case N|W: asm ("swapnw\t%0\n" : "+r" (x) : "0" (x)); break;
qemu-5.1+dfsg/tests/tcg/cris/libc/check_swap.c-28- default:
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-17-{
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:18: asm volatile ("bpl _err\n"
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-19- "nop\n");
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-22-{
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:23: asm volatile ("bmi _err\n"
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-24- "nop\n");
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-28-{
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:29: asm volatile ("bne _err\n"
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-30- "nop\n");
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-33-{
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:34: asm volatile ("beq _err\n"
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-35- "nop\n");
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-38-{
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:39: asm volatile ("bvc _err\n"
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-40- "nop\n");
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-43-{
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:44: asm volatile ("bvs _err\n"
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-45- "nop\n");
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-49-{
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:50: asm volatile ("bcc _err\n"
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-51- "nop\n");
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-54-{
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:55: asm volatile ("bcs _err\n"
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-56- "nop\n");
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-62- if (z) cris_tst_cc_z1(); else cris_tst_cc_z0();
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:63: asm volatile ("" : : "g" (_err));
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-64-}
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-72- if (c) cris_tst_cc_c1(); else cris_tst_cc_c0();
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h:73: asm volatile ("" : : "g" (_err));
qemu-5.1+dfsg/tests/tcg/cris/libc/crisutils.h-74-}
##############################################
qemu-5.1+dfsg/tests/tcg/cris/libc/sys.h-14-
qemu-5.1+dfsg/tests/tcg/cris/libc/sys.h:15:#define mb() asm volatile ("" : : : "memory")
qemu-5.1+dfsg/tests/tcg/cris/libc/sys.h-16-
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-523- flags = 0;
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:524: asm volatile ("push %4\n\t"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-525- "popf\n\t"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-541- flags = 0;
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:542: asm volatile ("push %4\n\t"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-543- "popf\n\t"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-560- flags = 0;
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:561: asm volatile ("push %4\n\t"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-562- "popf\n\t"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-578- s1 = op1;\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:579: asm volatile ("push %3\n\t"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-580- "popf\n\t"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-786-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:787: asm volatile ("fnstenv %0\n" : "=m" (float_env32));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-788- float_env32.fpus &= ~0x7f;
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:789: asm volatile ("fldenv %0\n" : : "m" (float_env32));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-790-}
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-835- fpu_clear_exceptions();
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:836: asm volatile("fxam\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-837- "fstsw %%ax\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-863- /* test all roundings */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:864: asm volatile ("fstcw %0" : "=m" (fpuc));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-865- for(i=0;i<4;i++) {
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-867- val16 = (fpuc & ~0x0c00) | (i << 10);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:868: asm volatile ("fldcw %0" : : "m" (val16));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:869: asm volatile ("fist %0" : "=m" (wa) : "t" (a));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:870: asm volatile ("fistl %0" : "=m" (ia) : "t" (a));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:871: asm volatile ("fistpll %0" : "=m" (lla) : "t" (a) : "st");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:872: asm volatile ("frndint ; fstl %0" : "=m" (ra) : "t" (a));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:873: asm volatile ("fldcw %0" : : "m" (fpuc));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-874- printf("(short)a = %d\n", wa);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-911- for(i=0;i<5;i++)\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:912: asm volatile ("fldl %0" : : "m" (dtab[i]));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:913: asm volatile (save " %0\n" : : "m" (*(env)));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:914: asm volatile (restore " %0\n": : "m" (*(env)));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-915- for(i=0;i<5;i++)\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:916: asm volatile ("fstpl %0" : "=m" (rtab[i]));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-917- for(i=0;i<5;i++)\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-957- for(i=0;i<5;i++)
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:958: asm volatile ("fldl %0" : : "m" (dtab[i]));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:959: asm volatile("ffree %st(2)");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:960: asm volatile ("fnstenv %0\n" : : "m" (float_env32));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:961: asm volatile ("fninit");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-962- printf("fptag=%04x\n", float_env32.fptag);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1040- flags = cc_in;\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1041: asm ("push %3\n\t"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1042- "popf\n\t"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1247- res = 0x12345678;\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1248: asm (op " %" size "2, %" size "0\n" \
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1249- "movl $0, %1\n"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1261- b = (op2); \
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1262: asm volatile(op " %" size "3, %" size "0\n"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1263- "movl $0,%1\n"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1314- /* do some tests with fs or gs */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1315: asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1316-
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1319-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1320: asm volatile ("fs movzbl 0x1, %0" : "=r" (res));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1321- printf("FS[1] = %02x\n", res);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1322-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1323: asm volatile ("pushl %%gs\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1324- "movl %1, %%gs\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1332- tmp = 0xa5;
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1333: asm volatile ("pushl %%ebp\n\t"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1334- "pushl %%ds\n\t"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1347- segoff.offset = 0xabcdef12;
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1348: asm volatile("lfs %2, %0\n\t"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1349- "movl %%fs, %1\n\t"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1392- /* call the first function */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1393: asm volatile ("lcall %1, %2"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1394- : "=a" (res)
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1396- printf("func1() = 0x%08x\n", res);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1397: asm volatile ("lcall %2, %3"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1398- : "=a" (res), "=c" (res2)
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1400- printf("func2() = 0x%08x spdec=%d\n", res, res2);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1401: asm volatile ("lcall %1, %2"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1402- : "=a" (res)
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1434- res = 0x12345678;
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1435: asm ("xlat" : "=a" (res) : "b" (table), "0" (res));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1436- printf("xlat: EAX=" FMTLX "\n", res);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1449-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1450: asm volatile ("mov %%cs, %0" : "=r" (cs_sel));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1451-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1452: asm volatile ("push %1\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1453- "call func_lret\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1460-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1461: asm volatile ("xor %%rax, %%rax\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1462- "rex64 lcall *(%%rcx)\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1467-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1468: asm volatile ("push %2\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1469- "mov $ 1f, %%rax\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1479-#else
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1480: asm volatile ("push %%cs ; call %1"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1481- : "=a" (res)
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1484-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1485: asm volatile ("pushf ; push %%cs ; call %1"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1486- : "=a" (res)
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1492- /* specific popl test */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1493: asm volatile ("push $12345432 ; push $0x9abcdef ; pop (%%rsp) ; pop %0"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1494- : "=g" (res));
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1497- /* specific popl test */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1498: asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popl (%%esp) ; popl %0"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1499- : "=g" (res));
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1502- /* specific popw test */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1503: asm volatile ("pushl $12345432 ; pushl $0x9abcdef ; popw (%%esp) ; addl $2, %%esp ; popl %0"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1504- : "=g" (res));
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1519-\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1520: asm volatile ("push $0\n\t"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1521- "popf\n\t"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1765- tab[1] = 10;
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1766: asm volatile ("bound %0, %1" : : "r" (11), "m" (tab[0]));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1767- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1773- /* load an invalid segment */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1774: asm volatile ("movl %0, %%fs" : : "r" ((0x1234 << 3) | 1));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1775- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1777- /* null data segment is valid */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1778: asm volatile ("movl %0, %%fs" : : "r" (3));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1779- /* null stack segment */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1780: asm volatile ("movl %0, %%ss" : : "r" (3));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1781- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1797- /* segment not present */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1798: asm volatile ("movl %0, %%fs" : : "r" (MK_SEL(1)));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1799- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1807- /* we add a nop to test a weird PC retrieval case */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1808: asm volatile ("nop");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1809- /* now store in an invalid address */
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1824- /* now execute an invalid instruction */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1825: asm volatile("ud2");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1826- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1829- /* now execute an invalid instruction */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1830: asm volatile(".byte 0xf0, 0x90");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1831- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1834- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1835: asm volatile ("int $0xfd");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1836- }
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1837- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1838: asm volatile ("int $0x01");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1839- }
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1840- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1841: asm volatile (".byte 0xcd, 0x03");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1842- }
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1843- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1844: asm volatile ("int $0x04");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1845- }
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1846- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1847: asm volatile ("int $0x05");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1848- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1851- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1852: asm volatile ("int3");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1853- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1856- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1857: asm volatile ("cli");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1858- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1861- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1862: asm volatile ("cli");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1863- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1868- /* overflow exception */
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1869: asm volatile ("addl $1, %0 ; into" : : "r" (0x7fffffff));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1870- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1874- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1875: asm volatile ("outb %%al, %%dx" : : "d" (0x4321), "a" (0));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1876- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1879- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1880: asm volatile ("inb %%dx, %%al" : "=a" (val) : "d" (0x4321));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1881- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1884- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1885: asm volatile ("rep outsb" : : "d" (0x4321), "S" (tab), "c" (1));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1886- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1889- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1890: asm volatile ("rep insb" : : "d" (0x4321), "D" (tab), "c" (1));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1891- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1894- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1895: asm volatile ("hlt");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1896- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1900- if (setjmp(jmp_env) == 0) {
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1901: asm volatile ("pushf\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1902- "orl $0x00100, (%%esp)\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1931- sigaction(SIGTRAP, &act, NULL);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:1932: asm volatile ("pushf\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-1933- "orl $0x00100, (%%esp)\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2128-{\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2129: asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2130- printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2154- b.q[0] = test_values[2*i+1][0];\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2155: asm volatile (#op " %2, %0" : "=y" (r.q[0]) : "0" (a.q[0]), "y" (b.q[0]));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2156- printf("%-9s: a=" FMT64X " b=" FMT64X " r=" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2170- b.q[1] = test_values[1][1];\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2171: asm volatile (#op " $" #ib ", %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2172- printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2185- a.q[1] = test_values[2*i][1];\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2186: asm volatile (#op " $" #ib ", %1, %0" : "=x" (r.dq) : "x" (a.dq));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2187- printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2200- a.q[1] = test_values[2*i][1];\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2201: asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2202- printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2218- b.q[1] = 0;\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2219: asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2220- printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2233- a.q[1] = test_values[2*i][1];\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2234: asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2235- printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2255- b.field[0] = b1;\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2256: asm volatile (#op " %2, %1\n"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2257- "pushf\n"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2275-{\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2276: asm volatile (#op " %1, %0" : "=x" (r.dq) : "x" (a.dq));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2277- printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2286-{\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2287: asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq) \
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2288- : "%xmm0"); \
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2289: asm volatile("emms\n"); \
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2290- printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2297-{\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2298: asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2299: asm volatile("emms\n"); \
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2300- printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2307-{\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2308: asm volatile (#op " %1, %0" : "=x" (r.dq) : "r" (a.l[0]));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2309- printf("%-9s: a=%08x r=" FMT64X "" FMT64X "\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2316-{\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2317: asm volatile (#op " %1, %0" : "=r" (r.l[0]) : "x" (a.dq));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2318- printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2449-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2450: asm volatile ("pinsrw $1, %1, %0" : "=y" (r.q[0]) : "r" (0x12345678));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2451- printf("%-9s: r=" FMT64X "\n", "pinsrw", r.q[0]);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2452-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2453: asm volatile ("pinsrw $5, %1, %0" : "=x" (r.dq) : "r" (0x12345678));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2454- printf("%-9s: r=" FMT64X "" FMT64X "\n", "pinsrw", r.q[1], r.q[0]);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2457- a.q[1] = test_values[0][1];
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2458: asm volatile ("pextrw $1, %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2459- printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2460-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2461: asm volatile ("pextrw $5, %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2462- printf("%-9s: r=%08x\n", "pextrw", r.l[0]);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2463-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2464: asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2465- printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2466-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2467: asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2468- printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2477- b.q[1] = test_values[1][1];
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2478: asm volatile("maskmovq %1, %0" :
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2479- : "y" (a.q[0]), "y" (b.q[0]), "D" (&r)
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2485- b.q[0]);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2486: asm volatile("maskmovdqu %1, %0" :
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2487- : "x" (a.dq), "x" (b.dq), "D" (&r)
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2495-
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2496: asm volatile ("emms");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2497-
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2551- uint32_t mxcsr;
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2552: asm volatile("stmxcsr %0" : "=m" (mxcsr));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2553- printf("mxcsr=%08x\n", mxcsr & 0x1f80);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2554: asm volatile("ldmxcsr %0" : : "m" (mxcsr));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2555- }
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2663-#endif
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2664: asm volatile ("emms");
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2665-}
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2673- r = a;\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2674: asm volatile(#op : "=a" (r) : "0" (r));\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2675- printf("%-10s A=" FMTLX " R=" FMTLX "\n", #op, a, r);\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2684- rh = d;\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2685: asm volatile(#op : "=a" (r), "=d" (rh) : "0" (r), "1" (rh)); \
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2686- printf("%-10s A=" FMTLX " R=" FMTLX ":" FMTLX "\n", #op, a, r, rh); \
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2705- a = i2l(0x12345678);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2706: asm volatile("bswapl %k0" : "=r" (r) : "0" (a));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2707- printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapl", a, r);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2712- a = i2l(0x12345678);
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c:2713: asm volatile("bswapq %0" : "=r" (r) : "0" (a));
qemu-5.1+dfsg/tests/tcg/i386/test-i386.c-2714- printf("%-10s: A=" FMTLX " R=" FMTLX "\n", "bswapq", a, r);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c-105-{
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c:106: asm volatile ("fninit\n");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c-107-}
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c-111- long double result;
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c:112: asm volatile ("fprem\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c-113- "fnstsw %1\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c-122- long double result;
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c:123: asm volatile ("fprem1\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c-124- "fnstsw %1\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c-214- fninit();
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c:215: asm volatile ("fprem\n"
qemu-5.1+dfsg/tests/tcg/i386/test-i386-fprem.c-216- "fnstsw %1\n"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.h-8-#define EXECOP2(size, rsize, res, s1, flags) \
qemu-5.1+dfsg/tests/tcg/i386/test-i386.h:9: asm ("push %4\n\t"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.h-10- "popf\n\t"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386.h-19-#define EXECOP1(size, rsize, res, flags) \
qemu-5.1+dfsg/tests/tcg/i386/test-i386.h:20: asm ("push %3\n\t"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386.h-21- "popf\n\t"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h-8- flags = 0;
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h:9: asm ("push %4\n\t"
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h-10- "popf\n\t"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h-26- flags = 0;
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h:27: asm ("push %5\n\t"
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h-28- "popf\n\t"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h-44- flags = 0;
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h:45: asm ("push %5\n\t"
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h-46- "popf\n\t"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h-63- flags = 0;
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h:64: asm ("push %5\n\t"
qemu-5.1+dfsg/tests/tcg/i386/test-i386-muldiv.h-65- "popf\n\t"
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-shift.h-11-#define EXECSHIFT(size, rsize, res, s1, s2, flags) \
qemu-5.1+dfsg/tests/tcg/i386/test-i386-shift.h:12: asm ("push %4\n\t"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386-shift.h-13- "popf\n\t"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-shift.h-20-#define EXECSHIFT(size, rsize, res, s1, s2, flags) \
qemu-5.1+dfsg/tests/tcg/i386/test-i386-shift.h:21: asm ("push %4\n\t"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386-shift.h-22- "popf\n\t"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-shift.h-72-#define EXECSHIFT(size, rsize, res, s1, s2, flags) \
qemu-5.1+dfsg/tests/tcg/i386/test-i386-shift.h:73: asm ("push %4\n\t"\
qemu-5.1+dfsg/tests/tcg/i386/test-i386-shift.h-74- "popf\n\t"\
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-19- /* pshufb mm1/xmm1, mm2/xmm2 */
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:20: asm volatile ("movq (%0), %%mm0" : : "r" (ehlo) : "mm0", "mm1");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:21: asm volatile ("movq %0, %%mm1" : : "m" (mask));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:22: asm volatile ("pshufb %mm1, %mm0");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:23: asm volatile ("movq %%mm0, %0" : "=m" (hello));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-24- printf("%s\n", hello);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-26- /* pshufb mm1/xmm1, m64/m128 */
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:27: asm volatile ("movq (%0), %%mm0" : : "r" (ehlo) : "mm0");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:28: asm volatile ("pshufb %0, %%mm0" : : "m" (mask));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:29: asm volatile ("movq %%mm0, %0" : "=m" (hello));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-30- printf("%s\n", hello);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-32- /* psubsw mm1/xmm1, m64/m128 */
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:33: asm volatile ("movq %0, %%mm0" : : "r" (a) : "mm0");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:34: asm volatile ("phsubsw %0, %%mm0" : : "m" (b));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:35: asm volatile ("movq %%mm0, %0" : "=m" (a));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-36- printf("%i - %i = %i\n", 9, 7, -(int16_t) a);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-38- /* palignr mm1/xmm1, m64/m128, imm8 */
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:39: asm volatile ("movdqa (%0), %%xmm0" : : "r" (e) : "xmm0");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:40: asm volatile ("palignr $14, (%0), %%xmm0" : : "r" (f));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:41: asm volatile ("movdqa %%xmm0, (%0)" : : "r" (hello));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-42- printf("%5.5s\n", hello);
##############################################
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-45- /* popcnt r64, r/m64 */
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:46: asm volatile ("movq $0x8421000010009c63, %%rax" : : : "rax");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:47: asm volatile ("popcnt %%ax, %%dx" : : : "dx");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:48: asm volatile ("popcnt %%eax, %%ecx" : : : "ecx");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:49: asm volatile ("popcnt %rax, %rax");
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:50: asm volatile ("movq %%rax, %0" : "=m" (a));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:51: asm volatile ("movl %%ecx, %0" : "=m" (c));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c:52: asm volatile ("movw %%dx, %0" : "=m" (d));
qemu-5.1+dfsg/tests/tcg/i386/test-i386-ssse3.c-53- printf("%i = %i\n%i = %i = %i\n", 13, (int) a, 9, c, d + 1);
##############################################
qemu-5.1+dfsg/tests/tcg/multiarch/gdbstub/sha1.py-31- # hopefully we came back
qemu-5.1+dfsg/tests/tcg/multiarch/gdbstub/sha1.py:32: end_pc = gdb.parse_and_eval('$pc')
qemu-5.1+dfsg/tests/tcg/multiarch/gdbstub/sha1.py-33- report(bp.hit_count == 1,
##############################################
qemu-5.1+dfsg/tests/tcg/multiarch/gdbstub/sha1.py-67-
qemu-5.1+dfsg/tests/tcg/multiarch/gdbstub/sha1.py:68:if gdb.parse_and_eval('$pc') == 0:
qemu-5.1+dfsg/tests/tcg/multiarch/gdbstub/sha1.py-69- print("SKIP: PC not set")
##############################################
qemu-5.1+dfsg/tests/tcg/s390x/csst.c-16-
qemu-5.1+dfsg/tests/tcg/s390x/csst.c:17: asm volatile(
qemu-5.1+dfsg/tests/tcg/s390x/csst.c-18- " lghi %%r0,%[flags]\n"
##############################################
qemu-5.1+dfsg/tests/tcg/s390x/exrl-trt.c-19- }
qemu-5.1+dfsg/tests/tcg/s390x/exrl-trt.c:20: asm volatile(
qemu-5.1+dfsg/tests/tcg/s390x/exrl-trt.c-21- " j 2f\n"
##############################################
qemu-5.1+dfsg/tests/tcg/s390x/exrl-trtr.c-19- }
qemu-5.1+dfsg/tests/tcg/s390x/exrl-trtr.c:20: asm volatile(
qemu-5.1+dfsg/tests/tcg/s390x/exrl-trtr.c-21- " j 2f\n"
##############################################
qemu-5.1+dfsg/tests/tcg/s390x/ipm.c-9-
qemu-5.1+dfsg/tests/tcg/s390x/ipm.c:10: asm volatile(
qemu-5.1+dfsg/tests/tcg/s390x/ipm.c-11- " clc 0(4,%[op1]),0(%[op2])\n"
##############################################
qemu-5.1+dfsg/tests/tcg/s390x/mvc.c-19-{
qemu-5.1+dfsg/tests/tcg/s390x/mvc.c:20: asm volatile (
qemu-5.1+dfsg/tests/tcg/s390x/mvc.c-21- " mvc 0(256,%[dst]),0(%[src])\n"
##############################################
qemu-5.1+dfsg/tests/tcg/s390x/mvo.c-10-
qemu-5.1+dfsg/tests/tcg/s390x/mvo.c:11: asm volatile (
qemu-5.1+dfsg/tests/tcg/s390x/mvo.c-12- " mvo 0(4,%[dest]),0(3,%[src])\n"
##############################################
qemu-5.1+dfsg/tests/tcg/s390x/pack.c-8-
qemu-5.1+dfsg/tests/tcg/s390x/pack.c:9: asm volatile(
qemu-5.1+dfsg/tests/tcg/s390x/pack.c-10- " pack 2(4,%[data]),2(4,%[data])\n"
##############################################
qemu-5.1+dfsg/ui/spice-core.c-716- spice_server = spice_server_new();
qemu-5.1+dfsg/ui/spice-core.c:717: spice_server_set_addr(spice_server, addr ? addr : "", addr_flags);
qemu-5.1+dfsg/ui/spice-core.c-718- if (port) {
##############################################
qemu-5.1+dfsg/ui/vnc.c-147-
qemu-5.1+dfsg/ui/vnc.c:148:static void vnc_init_basic_info_from_server_addr(QIOChannelSocket *ioc,
qemu-5.1+dfsg/ui/vnc.c-149- VncBasicInfo *info,
##############################################
qemu-5.1+dfsg/ui/vnc.c-167-
qemu-5.1+dfsg/ui/vnc.c:168:static void vnc_init_basic_info_from_remote_addr(QIOChannelSocket *ioc,
qemu-5.1+dfsg/ui/vnc.c-169- VncBasicInfo *info,
##############################################
qemu-5.1+dfsg/ui/vnc.c-239- info = g_malloc0(sizeof(*info));
qemu-5.1+dfsg/ui/vnc.c:240: vnc_init_basic_info_from_server_addr(vd->listener->sioc[0],
qemu-5.1+dfsg/ui/vnc.c-241- qapi_VncServerInfo_base(info), &err);
##############################################
qemu-5.1+dfsg/ui/vnc.c-272-
qemu-5.1+dfsg/ui/vnc.c:273:static void vnc_client_cache_addr(VncState *client)
qemu-5.1+dfsg/ui/vnc.c-274-{
##############################################
qemu-5.1+dfsg/ui/vnc.c-277- client->info = g_malloc0(sizeof(*client->info));
qemu-5.1+dfsg/ui/vnc.c:278: vnc_init_basic_info_from_remote_addr(client->sioc,
qemu-5.1+dfsg/ui/vnc.c-279- qapi_VncClientInfo_base(client->info),
##############################################
qemu-5.1+dfsg/ui/vnc.c-325-
qemu-5.1+dfsg/ui/vnc.c:326: vnc_init_basic_info_from_remote_addr(client->sioc,
qemu-5.1+dfsg/ui/vnc.c-327- qapi_VncClientInfo_base(info),
##############################################
qemu-5.1+dfsg/ui/vnc.c-3089-
qemu-5.1+dfsg/ui/vnc.c:3090: vnc_client_cache_addr(vs);
qemu-5.1+dfsg/ui/vnc.c-3091- vnc_qmp_event(vs, QAPI_EVENT_VNC_CONNECTED);
##############################################
qemu-5.1+dfsg/ui/vnc.c-3273-
qemu-5.1+dfsg/ui/vnc.c:3274:static void vnc_display_print_local_addr(VncDisplay *vd)
qemu-5.1+dfsg/ui/vnc.c-3275-{
##############################################
qemu-5.1+dfsg/ui/vnc.c-4034- if (qemu_opt_get(opts, "to")) {
qemu-5.1+dfsg/ui/vnc.c:4035: vnc_display_print_local_addr(vd);
qemu-5.1+dfsg/ui/vnc.c-4036- }
##############################################
qemu-5.1+dfsg/util/cacheinfo.c-124- entire hierarchy, and is used by userspace cache flushing. */
qemu-5.1+dfsg/util/cacheinfo.c:125: asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
qemu-5.1+dfsg/util/cacheinfo.c-126- if (*isize == 0) {
##############################################
qemu-5.1+dfsg/util/oslib-win32.c-244-{
qemu-5.1+dfsg/util/oslib-win32.c:245: uint32_t addr = inet_addr(cp);
qemu-5.1+dfsg/util/oslib-win32.c-246- if (addr == 0xffffffff) {
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-208-
qemu-5.1+dfsg/util/qemu-sockets.c:209:static int inet_listen_saddr(InetSocketAddress *saddr,
qemu-5.1+dfsg/util/qemu-sockets.c-210- int port_offset,
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-356-
qemu-5.1+dfsg/util/qemu-sockets.c:357:static int inet_connect_addr(struct addrinfo *addr, Error **errp);
qemu-5.1+dfsg/util/qemu-sockets.c-358-
qemu-5.1+dfsg/util/qemu-sockets.c:359:static int inet_connect_addr(struct addrinfo *addr, Error **errp)
qemu-5.1+dfsg/util/qemu-sockets.c-360-{
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-386-
qemu-5.1+dfsg/util/qemu-sockets.c:387:static struct addrinfo *inet_parse_connect_saddr(InetSocketAddress *saddr,
qemu-5.1+dfsg/util/qemu-sockets.c-388- Error **errp)
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-443- */
qemu-5.1+dfsg/util/qemu-sockets.c:444:int inet_connect_saddr(InetSocketAddress *saddr, Error **errp)
qemu-5.1+dfsg/util/qemu-sockets.c-445-{
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-449-
qemu-5.1+dfsg/util/qemu-sockets.c:450: res = inet_parse_connect_saddr(saddr, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-451- if (!res) {
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-457- local_err = NULL;
qemu-5.1+dfsg/util/qemu-sockets.c:458: sock = inet_connect_addr(e, &local_err);
qemu-5.1+dfsg/util/qemu-sockets.c-459- if (sock >= 0) {
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-485-
qemu-5.1+dfsg/util/qemu-sockets.c:486:static int inet_dgram_saddr(InetSocketAddress *sraddr,
qemu-5.1+dfsg/util/qemu-sockets.c-487- InetSocketAddress *sladdr,
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-704- if (!inet_parse(addr, str, errp)) {
qemu-5.1+dfsg/util/qemu-sockets.c:705: sock = inet_connect_saddr(addr, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-706- }
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-711-#ifdef CONFIG_AF_VSOCK
qemu-5.1+dfsg/util/qemu-sockets.c:712:static bool vsock_parse_vaddr_to_sockaddr(const VsockSocketAddress *vaddr,
qemu-5.1+dfsg/util/qemu-sockets.c-713- struct sockaddr_vm *svm,
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-737-
qemu-5.1+dfsg/util/qemu-sockets.c:738:static int vsock_connect_addr(const struct sockaddr_vm *svm, Error **errp)
qemu-5.1+dfsg/util/qemu-sockets.c-739-{
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-764-
qemu-5.1+dfsg/util/qemu-sockets.c:765:static int vsock_connect_saddr(VsockSocketAddress *vaddr, Error **errp)
qemu-5.1+dfsg/util/qemu-sockets.c-766-{
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-768-
qemu-5.1+dfsg/util/qemu-sockets.c:769: if (!vsock_parse_vaddr_to_sockaddr(vaddr, &svm, errp)) {
qemu-5.1+dfsg/util/qemu-sockets.c-770- return -1;
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-772-
qemu-5.1+dfsg/util/qemu-sockets.c:773: return vsock_connect_addr(&svm, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-774-}
qemu-5.1+dfsg/util/qemu-sockets.c-775-
qemu-5.1+dfsg/util/qemu-sockets.c:776:static int vsock_listen_saddr(VsockSocketAddress *vaddr,
qemu-5.1+dfsg/util/qemu-sockets.c-777- int num,
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-782-
qemu-5.1+dfsg/util/qemu-sockets.c:783: if (!vsock_parse_vaddr_to_sockaddr(vaddr, &svm, errp)) {
qemu-5.1+dfsg/util/qemu-sockets.c-784- return -1;
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-832-
qemu-5.1+dfsg/util/qemu-sockets.c:833:static int vsock_connect_saddr(VsockSocketAddress *vaddr, Error **errp)
qemu-5.1+dfsg/util/qemu-sockets.c-834-{
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-838-
qemu-5.1+dfsg/util/qemu-sockets.c:839:static int vsock_listen_saddr(VsockSocketAddress *vaddr,
qemu-5.1+dfsg/util/qemu-sockets.c-840- int num,
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-856-
qemu-5.1+dfsg/util/qemu-sockets.c:857:static int unix_listen_saddr(UnixSocketAddress *saddr,
qemu-5.1+dfsg/util/qemu-sockets.c-858- int num,
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-946-
qemu-5.1+dfsg/util/qemu-sockets.c:947:static int unix_connect_saddr(UnixSocketAddress *saddr, Error **errp)
qemu-5.1+dfsg/util/qemu-sockets.c-948-{
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1010-
qemu-5.1+dfsg/util/qemu-sockets.c:1011:static int unix_listen_saddr(UnixSocketAddress *saddr,
qemu-5.1+dfsg/util/qemu-sockets.c-1012- int num,
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1019-
qemu-5.1+dfsg/util/qemu-sockets.c:1020:static int unix_connect_saddr(UnixSocketAddress *saddr, Error **errp)
qemu-5.1+dfsg/util/qemu-sockets.c-1021-{
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1035- saddr->path = g_strdup(str);
qemu-5.1+dfsg/util/qemu-sockets.c:1036: sock = unix_listen_saddr(saddr, 1, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-1037- qapi_free_UnixSocketAddress(saddr);
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1047- saddr->path = g_strdup(path);
qemu-5.1+dfsg/util/qemu-sockets.c:1048: sock = unix_connect_saddr(saddr, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-1049- qapi_free_UnixSocketAddress(saddr);
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1126- case SOCKET_ADDRESS_TYPE_INET:
qemu-5.1+dfsg/util/qemu-sockets.c:1127: fd = inet_connect_saddr(&addr->u.inet, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-1128- break;
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1130- case SOCKET_ADDRESS_TYPE_UNIX:
qemu-5.1+dfsg/util/qemu-sockets.c:1131: fd = unix_connect_saddr(&addr->u.q_unix, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-1132- break;
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1138- case SOCKET_ADDRESS_TYPE_VSOCK:
qemu-5.1+dfsg/util/qemu-sockets.c:1139: fd = vsock_connect_saddr(&addr->u.vsock, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-1140- break;
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1154- case SOCKET_ADDRESS_TYPE_INET:
qemu-5.1+dfsg/util/qemu-sockets.c:1155: fd = inet_listen_saddr(&addr->u.inet, 0, num, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-1156- break;
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1158- case SOCKET_ADDRESS_TYPE_UNIX:
qemu-5.1+dfsg/util/qemu-sockets.c:1159: fd = unix_listen_saddr(&addr->u.q_unix, num, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-1160- break;
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1166- case SOCKET_ADDRESS_TYPE_VSOCK:
qemu-5.1+dfsg/util/qemu-sockets.c:1167: fd = vsock_listen_saddr(&addr->u.vsock, num, errp);
qemu-5.1+dfsg/util/qemu-sockets.c-1168- break;
##############################################
qemu-5.1+dfsg/util/qemu-sockets.c-1206- case SOCKET_ADDRESS_TYPE_INET:
qemu-5.1+dfsg/util/qemu-sockets.c:1207: fd = inet_dgram_saddr(&remote->u.inet,
qemu-5.1+dfsg/util/qemu-sockets.c-1208- local ? &local->u.inet : NULL, errp);
##############################################
qemu-5.1+dfsg/util/vfio-helpers.c-395-{
qemu-5.1+dfsg/util/vfio-helpers.c:396: void *host_addr = qemu_ram_get_host_addr(rb);
qemu-5.1+dfsg/util/vfio-helpers.c-397- ram_addr_t length = qemu_ram_get_used_length(rb);
##############################################
qemu-5.1+dfsg/debian/changelog-3465- #467106).
qemu-5.1+dfsg/debian/changelog:3466: * debian/patches/35_syscall_sockaddr.patch: fix sockaddr (Closes:
qemu-5.1+dfsg/debian/changelog-3467- #469351).
##############################################
qemu-5.1+dfsg/debian/changelog-3806- [ Josh Triplett ]
qemu-5.1+dfsg/debian/changelog:3807: * Fix FTBFS on PowerPC caused by asm constraint problem. (Closes: #361727)
qemu-5.1+dfsg/debian/changelog-3808- - debian/patches/64_ppc_asm_constraints.patch.
##############################################
qemu-5.1+dfsg/debian/patches/openbios-use-source_date_epoch-in-makefile.patch-22-- @DATE="$(shell echo `LC_ALL=C TZ=UTC date +'%b %e %Y %H:%M'`)" ; \
qemu-5.1+dfsg/debian/patches/openbios-use-source_date_epoch-in-makefile.patch:23:+ @DATE="$(shell echo `LC_ALL=C date --utc --date=@$(SOURCE_DATE_EPOCH) +'%b %e %Y %H:%M'`)" ; \
qemu-5.1+dfsg/debian/patches/openbios-use-source_date_epoch-in-makefile.patch-24- ( echo ": builddate \" $$DATE\" ; " ; \
##############################################
qemu-5.1+dfsg/debian/patches/openbios-use-source_date_epoch-in-makefile.patch-30-- @DATE="$(shell echo `LC_ALL=C TZ=UTC date +'%b %e %Y %H:%M'`)" ; \
qemu-5.1+dfsg/debian/patches/openbios-use-source_date_epoch-in-makefile.patch:31:+ @DATE="$(shell echo `LC_ALL=C date --utc --date=@$(SOURCE_DATE_EPOCH) +'%b %e %Y %H:%M'`)" ; \
qemu-5.1+dfsg/debian/patches/openbios-use-source_date_epoch-in-makefile.patch-32- ( echo "#define OPENBIOS_BUILD_DATE \"$$DATE\"" ; \
##############################################
qemu-5.1+dfsg/debian/qemu-make-debian-root-129-# Try to remove all libraries: some won't be removable.
qemu-5.1+dfsg/debian/qemu-make-debian-root:130:chroot $TMP_DIR dpkg --remove `chroot $TMP_DIR dpkg --get-selections | sed -n 's/^\(lib[^ \t]*\)[\t ]*install/\1/p'` 2>/dev/null || true
qemu-5.1+dfsg/debian/qemu-make-debian-root-131-
##############################################
qemu-5.1+dfsg/.pc/qboot-stop-using-inttypes.patch/roms/qboot/include/bios.h-85-{
qemu-5.1+dfsg/.pc/qboot-stop-using-inttypes.patch/roms/qboot/include/bios.h:86: asm volatile("cli; hlt");
qemu-5.1+dfsg/.pc/qboot-stop-using-inttypes.patch/roms/qboot/include/bios.h-87- for(;;);
##############################################
qemu-5.1+dfsg/.pc/seabios-hppa-fno-ipa-sra.patch/roms/seabios-hppa/Makefile.parisc-62-# Default compiler flags
qemu-5.1+dfsg/.pc/seabios-hppa-fno-ipa-sra.patch/roms/seabios-hppa/Makefile.parisc:63:cc-option=$(shell if test -z "`$(1) $(2) -S -o /dev/null -xc /dev/null 2>&1`" \
qemu-5.1+dfsg/.pc/seabios-hppa-fno-ipa-sra.patch/roms/seabios-hppa/Makefile.parisc-64- ; then echo "$(2)"; else echo "$(3)"; fi ;)
##############################################
qemu-5.1+dfsg/.pc/slof-remove-user-and-host-from-release-version.patch/roms/SLOF/Makefile.gen-40-
qemu-5.1+dfsg/.pc/slof-remove-user-and-host-from-release-version.patch/roms/SLOF/Makefile.gen:41:FLASH_SIZE_MB = `echo $$[ $(FLASH_SIZE)/1024/1024 ]`
qemu-5.1+dfsg/.pc/slof-remove-user-and-host-from-release-version.patch/roms/SLOF/Makefile.gen-42-
##############################################
qemu-5.1+dfsg/.pc/slof-ensure-ld-is-called-with-C-locale.patch/roms/SLOF/Makefile.gen-40-
qemu-5.1+dfsg/.pc/slof-ensure-ld-is-called-with-C-locale.patch/roms/SLOF/Makefile.gen:41:FLASH_SIZE_MB = `echo $$[ $(FLASH_SIZE)/1024/1024 ]`
qemu-5.1+dfsg/.pc/slof-ensure-ld-is-called-with-C-locale.patch/roms/SLOF/Makefile.gen-42-