data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:83: hander ==> handler
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:543: unneccessary ==> unnecessary
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:779: unitialized ==> uninitialized
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:887: modul ==> module
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:1111: mor ==> more
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:1115: overlayed ==> overlaid
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:1151: interupt ==> interrupt
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:1191: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:1199: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog:1263: unneccessary ==> unnecessary
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog.old:75: inconsitent ==> inconsistent
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog.old:174: writting ==> writing
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog.old:364: compatability ==> compatibility
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog.old:713: allready ==> already, all ready
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog.old:801: tripple ==> triple
data/simulavr-1.0.0+git20160221.e53413b/ChangeLog.old:809: arround ==> around
data/simulavr-1.0.0+git20160221.e53413b/README:18: Plattforms ==> Platforms
data/simulavr-1.0.0+git20160221.e53413b/README:20: plattform ==> platform
data/simulavr-1.0.0+git20160221.e53413b/README:26: plattform ==> platform
data/simulavr-1.0.0+git20160221.e53413b/README.gdb:5: otherwice ==> otherwise
data/simulavr-1.0.0+git20160221.e53413b/TODO:65: simlified ==> simplified
data/simulavr-1.0.0+git20160221.e53413b/TODO:79: diplay ==> display
data/simulavr-1.0.0+git20160221.e53413b/configure.ac:111: automaticaly ==> automatically
data/simulavr-1.0.0+git20160221.e53413b/configure.ac:152: modul ==> module
data/simulavr-1.0.0+git20160221.e53413b/configure.ac:263: modul ==> module
data/simulavr-1.0.0+git20160221.e53413b/create-sigmap.py:21: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/create-sigmap.py:23: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/delivery-check:74: usefull ==> useful
data/simulavr-1.0.0+git20160221.e53413b/delivery-check:76: carefull ==> careful, carefully
data/simulavr-1.0.0+git20160221.e53413b/delivery-check:338: successfull ==> successful
data/simulavr-1.0.0+git20160221.e53413b/tab-check.py:20: wich ==> which
data/simulavr-1.0.0+git20160221.e53413b/doc/README:62: exeptions ==> exceptions
data/simulavr-1.0.0+git20160221.e53413b/doc/README:63: sucessfull ==> successful
data/simulavr-1.0.0+git20160221.e53413b/doc/build.rst:65: Prerequsites ==> Prerequisites
data/simulavr-1.0.0+git20160221.e53413b/doc/build.rst:134: want's ==> wants
data/simulavr-1.0.0+git20160221.e53413b/doc/build.rst:203: successfull ==> successful
data/simulavr-1.0.0+git20160221.e53413b/doc/build.rst:203: cann ==> can
data/simulavr-1.0.0+git20160221.e53413b/doc/build_simple.rst:12: informations ==> information
data/simulavr-1.0.0+git20160221.e53413b/doc/build_simple.rst:51: Enabeling ==> Enabling
data/simulavr-1.0.0+git20160221.e53413b/doc/download.rst:57: sytem ==> system
data/simulavr-1.0.0+git20160221.e53413b/doc/download.rst:69: Dosn't ==> Doesn't
data/simulavr-1.0.0+git20160221.e53413b/doc/download.rst:74: Dosn't ==> Doesn't
data/simulavr-1.0.0+git20160221.e53413b/doc/examples.rst:24: grahic ==> graphic
data/simulavr-1.0.0+git20160221.e53413b/doc/examples.rst:81: interprete ==> interpret
data/simulavr-1.0.0+git20160221.e53413b/doc/examples.rst:95: incomming ==> incoming
data/simulavr-1.0.0+git20160221.e53413b/doc/features.rst:37: ot ==> to, of, or
data/simulavr-1.0.0+git20160221.e53413b/doc/formatcode.js:7: pres ==> press
data/simulavr-1.0.0+git20160221.e53413b/doc/formatcode.js:9: pres ==> press
data/simulavr-1.0.0+git20160221.e53413b/doc/formatcode.js:10: pres ==> press
data/simulavr-1.0.0+git20160221.e53413b/doc/intro.rst:14: compatibile ==> compatible
data/simulavr-1.0.0+git20160221.e53413b/doc/intro.rst:39: correponds ==> corresponds
data/simulavr-1.0.0+git20160221.e53413b/doc/intro.rst:42: correponds ==> corresponds
data/simulavr-1.0.0+git20160221.e53413b/doc/log2html.py:150: successfull ==> successful
data/simulavr-1.0.0+git20160221.e53413b/doc/log2html.py:152: successfull ==> successful
data/simulavr-1.0.0+git20160221.e53413b/doc/tclgui.rst:103: charcters ==> characters
data/simulavr-1.0.0+git20160221.e53413b/doc/tclgui.rst:110: smll ==> small, smell
data/simulavr-1.0.0+git20160221.e53413b/doc/tclgui.rst:143: diplay ==> display
data/simulavr-1.0.0+git20160221.e53413b/doc/tclgui.rst:157: specifc ==> specific
data/simulavr-1.0.0+git20160221.e53413b/doc/tclgui.rst:172: specifc ==> specific
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:547: ifset ==> if set
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:1225: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:1384: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:1385: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:1386: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:1387: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:1388: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:1389: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:1583: adn ==> and
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:3705: ifset ==> if set
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:3814: ifset ==> if set
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:3814: ifset ==> if set
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:3817: ifset ==> if set
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:3819: ifset ==> if set
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:3820: ifset ==> if set
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:3831: ifset ==> if set
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:4430: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:4439: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:4850: achive ==> achieve, archive
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:5549: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:5587: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:7284: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:7420: ifset ==> if set
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:7457: fo ==> of, for
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:7528: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:7874: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:7890: openin ==> opening
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:8036: ba ==> by, be
data/simulavr-1.0.0+git20160221.e53413b/doc/texinfo.tex:8157: ba ==> by, be
data/simulavr-1.0.0+git20160221.e53413b/doc/todo.rst:99: simlified ==> simplified
data/simulavr-1.0.0+git20160221.e53413b/doc/todo.rst:114: diplay ==> display
data/simulavr-1.0.0+git20160221.e53413b/doc/usage.rst:50: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:58: begining ==> beginning
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:98: compatibile ==> compatible
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:133: ot ==> to, of, or
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:459: charcters ==> characters
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:464: smll ==> small, smell
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:498: diplay ==> display
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:514: specifc ==> specific
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:528: specifc ==> specific
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:728: want's ==> wants
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:774: successfull ==> successful
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:774: cann ==> can
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:868: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:935: grahic ==> graphic
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:994: interprete ==> interpret
data/simulavr-1.0.0+git20160221.e53413b/doc/simulavr.texi:1008: incomming ==> incoming
data/simulavr-1.0.0+git20160221.e53413b/doc/_templates/index.html:20: compatibile ==> compatible
data/simulavr-1.0.0+git20160221.e53413b/doc/_templates/index.html:23: informations ==> information
data/simulavr-1.0.0+git20160221.e53413b/doc/_templates/index.html:32: unter ==> under
data/simulavr-1.0.0+git20160221.e53413b/doc/web/copy-to-cvs.sh:16: prerequsites ==> prerequisites
data/simulavr-1.0.0+git20160221.e53413b/examples/gui.tcl.in:79: seperate ==> separate
data/simulavr-1.0.0+git20160221.e53413b/examples/gui.tcl.in:191: ist ==> is, it, its, it's, sit, list
data/simulavr-1.0.0+git20160221.e53413b/examples/simulavr.tcl.in:25: extenions ==> extension, extensions
data/simulavr-1.0.0+git20160221.e53413b/examples/simulavr.tcl.in:33: varn ==> warn
data/simulavr-1.0.0+git20160221.e53413b/examples/simulavr.tcl.in:39: varn ==> warn
data/simulavr-1.0.0+git20160221.e53413b/examples/simulavr.tcl.in:373: CREAT ==> CREATE
data/simulavr-1.0.0+git20160221.e53413b/examples/anacomp/README:32: programm ==> program, programme
data/simulavr-1.0.0+git20160221.e53413b/examples/atmega48/README:22: recenet ==> recent
data/simulavr-1.0.0+git20160221.e53413b/examples/feedback/uart.c:12: Refere ==> Refer, referee
data/simulavr-1.0.0+git20160221.e53413b/examples/python/README:63: conected ==> connected
data/simulavr-1.0.0+git20160221.e53413b/examples/simple_ex1/fred.c:9: correponds ==> corresponds
data/simulavr-1.0.0+git20160221.e53413b/examples/simple_ex1/fred.c:14: correponds ==> corresponds
data/simulavr-1.0.0+git20160221.e53413b/examples/spi/README:20: recenet ==> recent
data/simulavr-1.0.0+git20160221.e53413b/examples/stdiodemo/stdiodemo.dox:146: accomodate ==> accommodate
data/simulavr-1.0.0+git20160221.e53413b/examples/stdiodemo/uart.h:32: invokation ==> invocation
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/Makefile.am:24: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/Makefile.am:25: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/Makefile.am:26: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/Makefile.am:26: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/Makefile.am:27: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/Makefile.am:28: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/Makefile.am:74: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/Makefile.am:75: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/Makefile.am:78: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/csinglepincomm.h:38: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:81: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:93: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:97: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:102: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:106: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:110: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:114: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:119: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:123: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.h:129: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.s:228: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.s:231: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.s:239: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.s:240: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.s:260: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.s:265: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.s:269: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/singlepincomm.s:272: rcall ==> recall
data/simulavr-1.0.0+git20160221.e53413b/examples/verilog/vst.cpp:28: independend ==> independent
data/simulavr-1.0.0+git20160221.e53413b/m4/avr_tcl.m4:59: prefered ==> preferred
data/simulavr-1.0.0+git20160221.e53413b/m4/avr_tcl.m4:74: prefered ==> preferred
data/simulavr-1.0.0+git20160221.e53413b/m4/ax_prog_doxygen.m4:24: seperate ==> separate
data/simulavr-1.0.0+git20160221.e53413b/m4/ax_prog_doxygen.m4:460: Seperate ==> Separate
data/simulavr-1.0.0+git20160221.e53413b/m4/ax_prog_doxygen.m4:461: seperate ==> separate
data/simulavr-1.0.0+git20160221.e53413b/m4/az_python.m4:139: Ouput ==> Output
data/simulavr-1.0.0+git20160221.e53413b/m4/az_python.m4:401: equivalant ==> equivalent
data/simulavr-1.0.0+git20160221.e53413b/m4/az_python.m4:462: Ouput ==> Output
data/simulavr-1.0.0+git20160221.e53413b/regress/regress.py.in:186: defaul ==> default
data/simulavr-1.0.0+git20160221.e53413b/regress/avrtest/avrtest_help.c:8: correponds ==> corresponds
data/simulavr-1.0.0+git20160221.e53413b/regress/avrtest/avrtest_help.c:13: correponds ==> corresponds
data/simulavr-1.0.0+git20160221.e53413b/regress/avrtest/avrtest_help.c:18: correponds ==> corresponds
data/simulavr-1.0.0+git20160221.e53413b/regress/extinttest/ext_int0.py:180: successfull ==> successful
data/simulavr-1.0.0+git20160221.e53413b/regress/extinttest/ext_int0.py:180: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/CONTRIBUTORS:37: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/CONTRIBUTORS:37: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/README:355: supportted ==> supported
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-death-test.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-death-test.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-death-test.h:152: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-message.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-message.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-printers.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-printers.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-printers.h:621: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-spi.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-spi.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-typed-test.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest-typed-test.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest.h:1207: funcions ==> functions
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest_prod.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/gtest_prod.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-death-test-internal.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-death-test-internal.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-death-test-internal.h:159: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-filepath.h:199: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-internal.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-internal.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-internal.h:1175: represenation ==> representation
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-linked_ptr.h:65: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-port.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-port.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-port.h:348: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-port.h:642: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-port.h:645: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-port.h:725: outter ==> outer
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-port.h:835: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-port.h:934: Synopsys ==> Synopsis
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-port.h:968: convertable ==> convertible
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-string.h:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-string.h:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-string.h:61: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-string.h:205: hel ==> help, hell, heal
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-tuple.h:32: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-tuple.h:32: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-type-util.h:34: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/include/gtest/internal/gtest-type-util.h:34: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-death-test.cc:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-death-test.cc:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-death-test.cc:722: Retuned ==> Returned
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-death-test.cc:723: Retuned ==> Returned
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-filepath.cc:126: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-filepath.cc:248: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-filepath.cc:348: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-internal-inl.h:32: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-internal-inl.h:32: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-internal-inl.h:218: containt ==> contain, content
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-internal-inl.h:394: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-port.cc:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-port.cc:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-port.cc:234: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-port.cc:479: creat ==> create
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-port.cc:504: creat ==> create
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-printers.cc:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-printers.cc:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-printers.cc:96: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-printers.cc:130: hexidecimal ==> hexadecimal
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-printers.cc:233: hexidecimal ==> hexadecimal
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-typed-test.cc:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest-typed-test.cc:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:30: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:30: Wan ==> Want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:411: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:465: separater ==> separator
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:506: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:509: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:512: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:515: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:909: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:1045: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:1397: upto ==> up to
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:1430: containt ==> contain, content
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:2021: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:2065: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:2066: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:2067: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:2067: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:2069: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:2096: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:3092: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:3122: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:3223: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/gtest-1.6.0/src/gtest.cc:4668: wan ==> want
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/session_irq_check/tc1.s:23: normaly ==> normally
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/session_irq_check/tc2.s:24: normaly ==> normally
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/session_irq_check/tc3.s:25: normaly ==> normally
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/session_irq_check/tc4.s:29: finsihed ==> finished
data/simulavr-1.0.0+git20160221.e53413b/regress/gtest/session_irq_check/tc5.cpp:64: invers ==> inverse, invert
data/simulavr-1.0.0+git20160221.e53413b/regress/modtest/anacomp_int.c:54: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/regress/modtest/anacomp_int.c:57: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/regress/modtest/anacomp_int.c:59: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/regress/modules/avr_target.py:33: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/regress/modules/avr_target.py:72: sav ==> save
data/simulavr-1.0.0+git20160221.e53413b/regress/modules/vcdreader.py:1: Modul ==> Module
data/simulavr-1.0.0+git20160221.e53413b/regress/modules/gdb_rsp.py:39: implemntation ==> implementation
data/simulavr-1.0.0+git20160221.e53413b/regress/tcl/main.c:19: correponds ==> corresponds
data/simulavr-1.0.0+git20160221.e53413b/regress/tcl/main.c:24: correponds ==> corresponds
data/simulavr-1.0.0+git20160221.e53413b/regress/test_opcodes/TODO:46: SER ==> SET
data/simulavr-1.0.0+git20160221.e53413b/regress/test_opcodes/TODO:71: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/regress/test_opcodes/test_BRBC.py:49: interrested ==> interested
data/simulavr-1.0.0+git20160221.e53413b/regress/test_opcodes/test_BRBS.py:49: interrested ==> interested
data/simulavr-1.0.0+git20160221.e53413b/regress/test_opcodes/test_BSET.py:29: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/regress/test_opcodes/test_ORI.py:108: SER ==> SET
data/simulavr-1.0.0+git20160221.e53413b/regress/test_opcodes/test_RCALL.py:26: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/regress/test_opcodes/test_RCALL.py:35: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/regress/test_opcodes/test_RCALL.py:39: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit.c:1: programm ==> program, programme
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_ext.c:1: programm ==> program, programme
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_fastpwm.py:64: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_fastpwm.py:80: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_fastpwm.py:83: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_fastpwm.py:86: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_fastpwm.py:102: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_fastpwm.py:105: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_fastpwm.py:116: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_fastpwm.py:120: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_icap.c:1: programm ==> program, programme
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_normal.py:57: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_normal.py:73: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_16bit_normal.py:76: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit.c:1: programm ==> program, programme
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit_ctc.c:1: programm ==> program, programme
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit_ctc.py:65: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit_ctc.py:81: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit_ctc.py:84: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit_ctc.py:94: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit_ctc.py:98: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit_normal.py:57: occurence ==> occurrence
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit_normal.py:73: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_8bit_normal.py:76: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_tX5_8bit.c:1: programm ==> program, programme
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_tX5_8bit.c:8: allways ==> always
data/simulavr-1.0.0+git20160221.e53413b/regress/timertest/timer_tX5_8bit.c:76: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/src/adcpin.cpp:64: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/src/at8515.cpp:55: internaly ==> internally
data/simulavr-1.0.0+git20160221.e53413b/src/avrdevice.cpp:303: immediatly ==> immediately
data/simulavr-1.0.0+git20160221.e53413b/src/avrdevice.h:42: transfered ==> transferred
data/simulavr-1.0.0+git20160221.e53413b/src/avrdevice.h:46: transfered ==> transferred
data/simulavr-1.0.0+git20160221.e53413b/src/avrdevice.h:106: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/src/decoder.cpp:2155: SER ==> SET
data/simulavr-1.0.0+git20160221.e53413b/src/decoder.cpp:2246: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/src/decoder_trace.cpp:179: SEH ==> SHE
data/simulavr-1.0.0+git20160221.e53413b/src/decoder_trace.cpp:567: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/src/externalirq.h:55: interupt ==> interrupt
data/simulavr-1.0.0+git20160221.e53413b/src/flash.h:37: informations ==> information
data/simulavr-1.0.0+git20160221.e53413b/src/flash.h:43: inaccesible ==> inaccessible
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:88: reseted ==> reset
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:94: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:100: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:106: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:107: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:107: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:107: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:117: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:119: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:119: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:158: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:169: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.cpp:184: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwacomp.h:75: ACI ==> ACPI
data/simulavr-1.0.0+git20160221.e53413b/src/hwpinchange.h:135: chages ==> changes, charges
data/simulavr-1.0.0+git20160221.e53413b/src/hwport.h:39: thats ==> that's
data/simulavr-1.0.0+git20160221.e53413b/src/hwstack.h:90: poping ==> popping, pooping
data/simulavr-1.0.0+git20160221.e53413b/src/hwstack.h:97: adresses ==> addresses
data/simulavr-1.0.0+git20160221.e53413b/src/hwuart.cpp:66: allready ==> already, all ready
data/simulavr-1.0.0+git20160221.e53413b/src/hwuart.cpp:178: controling ==> controlling
data/simulavr-1.0.0+git20160221.e53413b/src/hwuart.cpp:331: allready ==> already, all ready
data/simulavr-1.0.0+git20160221.e53413b/src/hwuart.cpp:351: allways ==> always
data/simulavr-1.0.0+git20160221.e53413b/src/hwuart.cpp:387: TRANCEIVER ==> TRANSCEIVER
data/simulavr-1.0.0+git20160221.e53413b/src/hwuart.h:62: controling ==> controlling
data/simulavr-1.0.0+git20160221.e53413b/src/hwusi.cpp:207: dout ==> doubt
data/simulavr-1.0.0+git20160221.e53413b/src/hwusi.cpp:213: dout ==> doubt
data/simulavr-1.0.0+git20160221.e53413b/src/hwusi.cpp:364: dout ==> doubt
data/simulavr-1.0.0+git20160221.e53413b/src/hwusi.cpp:368: dout ==> doubt
data/simulavr-1.0.0+git20160221.e53413b/src/hwusi.h:146: dout ==> doubt
data/simulavr-1.0.0+git20160221.e53413b/src/hwusi.h:190: dout ==> doubt
data/simulavr-1.0.0+git20160221.e53413b/src/hwwado.cpp:38: allways ==> always
data/simulavr-1.0.0+git20160221.e53413b/src/irqsystem.cpp:45: seperated ==> separated
data/simulavr-1.0.0+git20160221.e53413b/src/memory.h:35: informations ==> information
data/simulavr-1.0.0+git20160221.e53413b/src/memory.h:36: informations ==> information
data/simulavr-1.0.0+git20160221.e53413b/src/memory.h:76: exeption ==> exception, exemption
data/simulavr-1.0.0+git20160221.e53413b/src/memory.h:91: informations ==> information
data/simulavr-1.0.0+git20160221.e53413b/src/memory.h:93: informations ==> information
data/simulavr-1.0.0+git20160221.e53413b/src/pin.cpp:191: transfered ==> transferred
data/simulavr-1.0.0+git20160221.e53413b/src/rwmem.h:255: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/src/rwmem.h:293: theres ==> there's
data/simulavr-1.0.0+git20160221.e53413b/src/rwmem.h:295: possibillity ==> possibility
data/simulavr-1.0.0+git20160221.e53413b/src/rwmem.h:343: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/src/rwmem.h:347: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/src/systemclock.h:74: completly ==> completely
data/simulavr-1.0.0+git20160221.e53413b/src/systemclock.h:78: implementated ==> implemented
data/simulavr-1.0.0+git20160221.e53413b/src/systemclock.h:91: asynchron ==> asynchronous
data/simulavr-1.0.0+git20160221.e53413b/src/traceval.cpp:69: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/src/traceval.cpp:77: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/src/traceval.h:105: unitialized ==> uninitialized
data/simulavr-1.0.0+git20160221.e53413b/src/vpi.cpp:300: adress ==> address
data/simulavr-1.0.0+git20160221.e53413b/src/vpi.cpp:320: adress ==> address
data/simulavr-1.0.0+git20160221.e53413b/src/cmd/gdbserver.cpp:366: hexidecimal ==> hexadecimal
data/simulavr-1.0.0+git20160221.e53413b/src/cmd/gdbserver.cpp:877: ist ==> is, it, its, it's, sit, list
data/simulavr-1.0.0+git20160221.e53413b/src/cmd/gdbserver.cpp:878: thi ==> the, this
data/simulavr-1.0.0+git20160221.e53413b/src/cmd/gdbserver.cpp:1255: woth ==> worth
data/simulavr-1.0.0+git20160221.e53413b/src/cmd/gdbserver.cpp:1458: everytime ==> every time
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/README:3: dependant ==> dependent
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elf_types.hpp:142: microprocesspr ==> microprocessor
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:88: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:124: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:185: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:252: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:256: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:273: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:276: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:296: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:299: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:369: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:372: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio.hpp:615: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dump.hpp:142: microprocesspr ==> microprocessor
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dump.hpp:346: LOOS ==> LOOSE, LOSE
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dump.hpp:366: LOOS ==> LOOSE, LOSE
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dynamic.hpp:126: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dynamic.hpp:139: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dynamic.hpp:163: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dynamic.hpp:179: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dynamic.hpp:189: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dynamic.hpp:215: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dynamic.hpp:231: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_dynamic.hpp:235: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_header.hpp:78: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_header.hpp:90: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_header.hpp:92: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_header.hpp:93: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_header.hpp:96: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_header.hpp:97: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_header.hpp:141: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:60: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:61: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:62: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:64: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:86: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:89: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:91: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:93: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:118: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:132: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_note.hpp:134: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:294: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:299: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:300: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:315: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:320: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:321: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:324: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:332: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:335: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:336: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:346: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:352: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:353: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_relocation.hpp:354: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_section.hpp:72: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_section.hpp:125: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_section.hpp:217: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_section.hpp:232: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_section.hpp:269: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_segment.hpp:68: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_segment.hpp:152: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_segment.hpp:167: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_segment.hpp:178: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:218: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:222: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:226: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:227: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:230: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:246: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:249: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:251: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:253: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:254: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:255: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_symbols.hpp:256: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_utils.hpp:29: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_utils.hpp:35: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_utils.hpp:40: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/elfio/elfio/elfio_utils.hpp:45: convertor ==> converter
data/simulavr-1.0.0+git20160221.e53413b/src/hwtimer/hwtimer.cpp:1618: dosn't ==> doesn't
data/simulavr-1.0.0+git20160221.e53413b/src/hwtimer/hwtimer.h:62: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/src/hwtimer/hwtimer.h:612: allways ==> always
data/simulavr-1.0.0+git20160221.e53413b/src/hwtimer/hwtimer.h:675: allways ==> always
data/simulavr-1.0.0+git20160221.e53413b/src/hwtimer/hwtimer.h:821: modul ==> module
data/simulavr-1.0.0+git20160221.e53413b/src/hwtimer/hwtimer.h:822: modul ==> module
data/simulavr-1.0.0+git20160221.e53413b/src/hwtimer/prescalermux.h:45: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/src/hwtimer/timerirq.h:54: occured ==> occurred
data/simulavr-1.0.0+git20160221.e53413b/src/python/pysimulationmember.h:37: allways ==> always
data/simulavr-1.0.0+git20160221.e53413b/src/python/pysimulationmember.h:51: overlayed ==> overlaid
data/simulavr-1.0.0+git20160221.e53413b/src/python/setup.py.in:41: modul ==> module
data/simulavr-1.0.0+git20160221.e53413b/src/python/setup.py.in:42: modul ==> module
data/simulavr-1.0.0+git20160221.e53413b/src/ui/keyboard.cpp:163: comand ==> command
data/simulavr-1.0.0+git20160221.e53413b/src/ui/lcd.cpp:188: Safty ==> Safety
data/simulavr-1.0.0+git20160221.e53413b/src/ui/lcd.cpp:252: comand ==> command
data/simulavr-1.0.0+git20160221.e53413b/src/ui/lcd.cpp:278: comand ==> command
data/simulavr-1.0.0+git20160221.e53413b/src/ui/ui.cpp:122: reenable ==> re-enable
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr.v:41: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATmega32.v:25: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATmega32.v:26: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATmega32.v:27: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATmega32.v:28: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATmega8.v:26: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATmega8.v:27: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATmega8.v:28: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATtiny2313.v:26: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATtiny2313.v:27: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATtiny2313.v:28: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/src/verilog/avr_ATtiny25.v:26: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/debian/changelog:96: Readd ==> Re-add, read
data/simulavr-1.0.0+git20160221.e53413b/debian/patches/0004-Convert-python-test-files-to-python-3.patch:46: Modul ==> Module
data/simulavr-1.0.0+git20160221.e53413b/debian/patches/spelling.patch:10: hexidecimal ==> hexadecimal
data/simulavr-1.0.0+git20160221.e53413b/debian/patches/spelling.patch:21: informations ==> information
data/simulavr-1.0.0+git20160221.e53413b/.pc/spelling.patch/src/cmd/gdbserver.cpp:366: hexidecimal ==> hexadecimal
data/simulavr-1.0.0+git20160221.e53413b/.pc/spelling.patch/src/cmd/gdbserver.cpp:379: hexidecimal ==> hexadecimal
data/simulavr-1.0.0+git20160221.e53413b/.pc/spelling.patch/src/cmd/gdbserver.cpp:877: ist ==> is, it, its, it's, sit, list
data/simulavr-1.0.0+git20160221.e53413b/.pc/spelling.patch/src/cmd/gdbserver.cpp:878: thi ==> the, this
data/simulavr-1.0.0+git20160221.e53413b/.pc/spelling.patch/src/cmd/gdbserver.cpp:1255: woth ==> worth
data/simulavr-1.0.0+git20160221.e53413b/.pc/spelling.patch/src/cmd/gdbserver.cpp:1458: everytime ==> every time
data/simulavr-1.0.0+git20160221.e53413b/.pc/spelling.patch/src/cmd/main.cpp:110: informations ==> information
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:53: begining ==> beginning
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:93: compatibile ==> compatible
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:128: ot ==> to, of, or
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:454: charcters ==> characters
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:459: smll ==> small, smell
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:493: diplay ==> display
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:509: specifc ==> specific
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:523: specifc ==> specific
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:723: want's ==> wants
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:769: successfull ==> successful
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:769: cann ==> can
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:863: inout ==> input, in out
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:930: grahic ==> graphic
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:989: interprete ==> interpret
data/simulavr-1.0.0+git20160221.e53413b/.pc/info_fixes.patch/doc/simulavr.texi:1003: incomming ==> incoming
data/simulavr-1.0.0+git20160221.e53413b/.pc/0001-Convert-regression-tests-to-python-3.patch/regress/regress.py.in:185: defaul ==> default
data/simulavr-1.0.0+git20160221.e53413b/.pc/0001-Convert-regression-tests-to-python-3.patch/regress/modules/gdb_rsp.py:38: implemntation ==> implementation
data/simulavr-1.0.0+git20160221.e53413b/.pc/0001-Convert-regression-tests-to-python-3.patch/regress/test_opcodes/test_BRBC.py:49: interrested ==> interested
data/simulavr-1.0.0+git20160221.e53413b/.pc/0001-Convert-regression-tests-to-python-3.patch/regress/test_opcodes/test_BRBS.py:49: interrested ==> interested
data/simulavr-1.0.0+git20160221.e53413b/.pc/0001-Convert-regression-tests-to-python-3.patch/regress/test_opcodes/test_BSET.py:29: SEH ==> SHE
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data/simulavr-1.0.0+git20160221.e53413b/.pc/0001-Convert-regression-tests-to-python-3.patch/regress/test_opcodes/test_RCALL.py:35: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/.pc/0001-Convert-regression-tests-to-python-3.patch/regress/test_opcodes/test_RCALL.py:39: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/.pc/0004-Convert-python-test-files-to-python-3.patch/regress/modules/vcdreader.py:1: Modul ==> Module
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data/simulavr-1.0.0+git20160221.e53413b/.pc/0006-Replace-usr-bin-env-python3-with-usr-bin-env-python-.patch/regress/test_opcodes/test_BRBC.py:49: interrested ==> interested
data/simulavr-1.0.0+git20160221.e53413b/.pc/0006-Replace-usr-bin-env-python3-with-usr-bin-env-python-.patch/regress/test_opcodes/test_BRBS.py:49: interrested ==> interested
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data/simulavr-1.0.0+git20160221.e53413b/.pc/0006-Replace-usr-bin-env-python3-with-usr-bin-env-python-.patch/regress/test_opcodes/test_ORI.py:108: SER ==> SET
data/simulavr-1.0.0+git20160221.e53413b/.pc/0006-Replace-usr-bin-env-python3-with-usr-bin-env-python-.patch/regress/test_opcodes/test_RCALL.py:26: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/.pc/0006-Replace-usr-bin-env-python3-with-usr-bin-env-python-.patch/regress/test_opcodes/test_RCALL.py:35: RCALL ==> RECALL
data/simulavr-1.0.0+git20160221.e53413b/.pc/0006-Replace-usr-bin-env-python3-with-usr-bin-env-python-.patch/regress/test_opcodes/test_RCALL.py:39: RCALL ==> RECALL
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