===========================================================
                                      .___ __  __   
          _________________  __ __  __| _/|__|/  |_ 
         / ___\_` __ \__  \ |  |  \/ __ | | \\_  __\
        / /_/  >  | \// __ \|  |  / /_/ | |  ||  |  
        \___  /|__|  (____  /____/\____ | |__||__|  
       /_____/            \/           \/           
              grep rough audit - static analysis tool
                  v2.8 written by @Wireghoul
=================================[justanotherhacker.com]===
verilog-mode-20161124.fd230e6/config_rev.pl-16-my $rev = 'UNKNOWN_REV';
verilog-mode-20161124.fd230e6/config_rev.pl:17:my $data = `git log --pretty=format:'%ad-%h' --date=short -1 $file`;
verilog-mode-20161124.fd230e6/config_rev.pl-18-if ($data =~ /(^20.*)/i) {
##############################################
verilog-mode-20161124.fd230e6/config_rev.pl-21-
verilog-mode-20161124.fd230e6/config_rev.pl:22:$data = `git status $file`;
verilog-mode-20161124.fd230e6/config_rev.pl-23-if ($data =~ /Changed but not updated/i
##############################################
verilog-mode-20161124.fd230e6/makechangelog-42-    $Opt_FileB = $now;
verilog-mode-20161124.fd230e6/makechangelog:43:    system("git show HEAD:${now} > $Opt_FileA");
verilog-mode-20161124.fd230e6/makechangelog-44-}
##############################################
verilog-mode-20161124.fd230e6/tests_ok/autoinst_ding.v-66-           .cpu_wr                              (cpu_wr),
verilog-mode-20161124.fd230e6/tests_ok/autoinst_ding.v:67:           .cpu_addr                    (cpu_addr[4:0]),
verilog-mode-20161124.fd230e6/tests_ok/autoinst_ding.v-68-           .cpu_wdata                   (cpu_wdata[7:0]));
##############################################
verilog-mode-20161124.fd230e6/tests_ok/autoinst_genvar.v-50-           .cpu_wr                              (cpu_wr),
verilog-mode-20161124.fd230e6/tests_ok/autoinst_genvar.v:51:           .cpu_addr                    (cpu_addr[4:0]),
verilog-mode-20161124.fd230e6/tests_ok/autoinst_genvar.v-52-           .cpu_wdata                   (cpu_wdata[7:0]));
##############################################
verilog-mode-20161124.fd230e6/verilog-mode.el-8580-		      (not rvalue)
verilog-mode-20161124.fd230e6/verilog-mode.el:8581:		      (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
verilog-mode-20161124.fd230e6/verilog-mode.el-8582-		 (when (match-end 2) (goto-char (match-end 2)))
##############################################
verilog-mode-20161124.fd230e6/verilog-mode.el-9244-	(beginning-of-line)
verilog-mode-20161124.fd230e6/verilog-mode.el:9245:	(if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
verilog-mode-20161124.fd230e6/verilog-mode.el-9246-	    ;;(if (looking-at "^\\(.+\\)$")
##############################################
verilog-mode-20161124.fd230e6/verilog-mode.el-10798-    ;; It's hard to distinguish modules; we'll instead search for pins.
verilog-mode-20161124.fd230e6/verilog-mode.el:10799:    (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_$]+\\s *(\\s *[a-zA-Z0-9`_$]+\\s *)" nil t)
verilog-mode-20161124.fd230e6/verilog-mode.el-10800-      (verilog-backward-open-paren)  ; Inst start